Fan-out Wafer Level Packaging Technology Research Articles

High-Q Ku-band Microstrip Spiral Resonator in Fan-out Wafer-Level Packaging (FoWLP) Technology for VCO Applications

In this paper, a planar spiral resonator operating at 13 GHz is investigated. The resonator was fabricated using fan-out wafer level packaging (FoWLP) technology. The field analysis highlights the importance of via fence. Two thick film resistors suppress an undesired resonance in proximity of targeted one. The measurements demonstrate a very good correlation in comparison with full-wave simulations. The measured Q-factor defined based on analysis of feedback oscillatory system is about 48. The proposed configuration is suitable for voltage-controlled oscillators (VCOs) with a resonator realized in package.

Characterizations for eWLB (Embedded Wafer Level Ball Grid Array) Antenna in Molded Package Integrations in 77GHz Automotive Applications

The worldwide IC market has had a significant growth rate in recent years, driving diversified package solutions in the segments of communication, computing, consumer, automotive, industrial, etc. Among these market segments, the automotive market is forecast to have the strongest CAGR (Compound Annual Growth Rate) of any of the end-use segments in the next 5 years, which results in more IC packages and components being designed into automotive vehicle systems such as infotainment, ADAS (Advance Driving Assistance System), instrumentation, body systems, battery control systems and so on. In these applications, the 77GHz short-range radar sensor application that can enable higher EIRP (Effective Isotropic Radiated Power) and adaptive cruise control performance has become more attractive to be commercialized. Due to the benefits of shorter interconnection length, lower conductive loss with smooth Cu surface as well as a lower dielectric constant and dielectric loss of materials in a fan-out wafer level package (FOWLP) technology, the FOWLP is proven as a suitable packaging solution to achieve the high speed and frequency requirements in 5G and mmWave applications. The eWLB Embedded Wafer Level Ball Grid Array) is a versatile FOWLP technology, providing a robust package platform in a space-efficient design with the very dense interconnection and routing of multiple dies as well as a smaller footprint and lower package profile providing a reliable package solution. Meanwhile, since the utilization of an antenna that is integrated into the packages has been studied as a lowcost solution because the packages can be tested in normal FR4 printed circuit board (PCB) instead of the RF function integrated PCB, the eWLB integrated with molded antenna chip packages (called eWLB antenna in molded package) technology is introduced in this paper. The characterizations for assembly process challenges are evaluated and illustrate the process optimizations of equipment handling, antenna molded chip package fabrication, reconstitution process control and warpage characterization of the molded wafer. In addition, the radio frequency (RF) test validation is performed to verify the performance of scattering parameter (S-parameter), radiation pattern, impedance and detection range of the antenna. In order to prove the reliable quality and yield of the evaluated eWLB antenna in molded packages, package-level reliability tests are studied. Through these results, it will show that this eWLB antenna in molded package integration is a robust and costeffective solution for 77GHz automotive applications.

Ultrathin Antenna-in-Package Based on TMV-Embedded FOWLP for 5G mm-Wave Applications

In this paper, a novel through mold via (TMV)-embedded fan-out wafer-level package (FOWLP) technology was demonstrated to manufacture the well-designed Antenna in Package (AiP) with ultrathin thickness (0.04 λ0). Double-sided redistribution layers (RDLs) were employed to build the patch antenna, while a TMV interposer was used to connect the front and back RDLs. By optimizing the AiP’s parameters, the patch antenna can achieve a wide impedance bandwidth of 17.8% from 24.2 to 28.5 GHz, which can cover the 5G frequency bands. Compared with previous works, the proposed AiP has significant benefits in terms of its ultralow profile, easy processing, and high gain. Hence, the TMV-embedded FOWLP should be a promising technology for fifth generation (5G) millimeter wave (mm-Wave) applications.

FOWLP and Flip Chip Cost Comparison: Impact of the Supply Chain Crunch

The impact of the pandemic on the semiconductor and electronics packaging supply chains has been in the news for over a year now. Current projections suggest the supply chain crunch could impact various industries through 2022 and 2023. While there are many ramifications of this shortage, one is certainly the impact on cost. Pricing for packages built with more mature technologies, such as wire bond and flip chip, has changed dramatically. Both of these mature technologies have typically been seen as lower cost options than newer technologies, such as fan-out wafer level packaging (FOWLP). Due to the recent shortages, the cost comparison is no longer as straight-forward as it was before. This paper will analyze the cost of building various packages using flip chip, wire bond, and FOWLP technologies. Factory overhead, indirect costs, and profit margins will be taken into account to turn this into a price comparison, rather than just a comparison of direct costs. The analyses will include the price of a package built using FOWLP technology, the price of flip chip and wire bond packages built before recent supply chain disruptions, and the new expected prices of flip chip and wire bond packages. Activity based cost modeling will be used for this analysis. This is a bottom-up, detailed approach to cost that accounts for the many cost components associated with every step of the process flow, such as material, labor, and capital depreciation. The goal of this analysis is to understand how supply chain disruptions have changed the cost parity points of wire bond, flip chip, and FOWLP packages.

A Wideband Co-Linearly Polarized Full-Duplex Antenna-in-Package With High Isolation for Integrated Sensing and Communication

In this letter, a novel co-linearly polarized full-duplex antenna-in-package (AiP) with high Tx/Rx isolation and wide decoupled bandwidth is proposed for integrated sensing and communication (ISAC). Fan-out wafer-level packaging technology is employed, and the preparation process is discussed in details. To improve Tx/Rx isolation, the current direction of the patch elements is orthogonal to that of the feeding ports. Two identical 1×2 patch antenna arrays are used as Tx and Rx antennas, respectively. To further suppress mutual coupling, a decoupling loop is proposed to enhance Tx/Rx isolation. In addition, a wideband full-duplex AiP with high isolation and wide decoupled bandwidth is also proposed by using the parasitic technique and the proposed decoupling method. Prototypes are fabricated and measured to verify the proposed AiPs. The measurement results demonstrate that the proposed AiP possesses the merits of high Tx/Rx isolation (up to 53 dB), wide isolation bandwidth (up to 9.2%) and low cost, providing a foundation for chip-level applications in ISAC.

High Gain and Wideband Antenna-in-Package Solution Using Fan-Out Technology

AbstractThe technology of fan-out wafer level packaging (FOWLP) has been widely adopted for millimeter wave antenna-in-package (AiP) system integration with low interconnection parasitic parameters. Present AiP solutions using FOWLP technology generally form antenna pattern on redistribution layer, which brings design inconvenience. In our work, a low-cost printed circuit board RO4350B laminate for substrate-integrated waveguide (SIW) antenna with a relatively large size is integrated, forms a three-dimensional stacked structure. The AiP employs a right-angle transition board embedded in epoxy molding compound (EMC), which transmits millimeter-wave signal to the SIW antenna stacked on the backside of EMC. The SIW antenna consists of 4 × 4 radiation slots with modified magneto-electric dipole for bandwidth enhancement. The measured gain is 14dBi at 60 GHz with bandwidth beyond 55–65 GHz. The three-dimensional AiP structure improves heat dissipation, no extra thermal design is needed for applications under 0.5 W mm-wave chip power consumption. The AiP module is manufactured and measured on the test board. The proposed approach is a convenient solution for wide band and high gain millimeter wave AiP system integration.

A K-Band Hybrid-Packaged Temperature-Compensated Phased-Array Receiver and Integrated Antenna Array

This article presents an eight-channel 1.9-dB noise figure (NF) <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$K$ </tex-math></inline-formula> -band phased-array receiver (RX) for satellite communication (SATCOM). It employs the hybrid-packaged 65-nm CMOS beamformer and 0.1- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> GaAs low-noise amplifiers (LNAs) based on the fan-out wafer-level chip-scale packaging (WLCSP) technology. For the power-efficient RX implementation, the power consumption of gain and phase tuning blocks is discussed, and the fully passive phase shifter (PS) and attenuator (ATT) are employed in this work. A global biasing scheme is proposed to ensure performance uniformity across temperature variations. Across the SATCOM band of 17.7–20.2 GHz, the proposed hybrid-packaged phased-array RX IC only consumes 30.2-mW dc power per channel and achieves < 1.2-dB gain variation and < 0.9-dB NF variation from −40° to 85 °C. Based on the RX IC, a dual-polarized 1024-element RX antenna array is further introduced. The measured gain-to-noise temperature ratios (G/Ts) are 6.22 and 6.51 dB/K at 19.7 GHz for left- and right-hand circular polarizations, respectively.

(Invited) Fan-out Wafer-Level Packaging: Opportunities and Challenges Towards Heterogeneous Systems

This article describes opportunities and challenges towards heterogeneous systems integration by the so-called fan-out wafer-level packaging (FOWLP) technology. An introduction on the technology is given, before we describe specific developments built up at CEA-Leti. Recent assessments of a multi-chip SiP for 5G applications and scalable three-dimensional interconnects are presented.

Suppression strategy for process-induced warpage of novel fan-out wafer level packaging

In the study, the novel fan-out wafer level packaging (FOWLP) technology is presented in which the through silicon via (TSV) array interposer layer is manufactured. Compared to conventional FOWLP technology, the present novel FOWLP technology has several advantages of better signal integrity, higher electrical performance, and easier customization. However, similar to the conventional FOWLP technology, the process-induced warpage resulted from the mismatch of the coefficient of thermal expansion (CTE) among the constituent materials is also an essential issue during the fan-out fabrication process, which is notably for successful process integration. This study proposes a comprehensive assessment of the process-induced warpage of the novel FOWLP during the fan-out fabrication process. A process-dependent simulation methodology is introduced, which integrates nonlinear finite element (FE) analysis incorporated with the element death-birth technique. The study starts from establishing a silicon interposer layer with TSV array, attachment of glass carrier, multiple redistribution layers (RDLs), and dielectric layers. The warpage evolution during the fan-out fabrication process is thoroughly evaluated according to the temperature loading profile. To demonstrate the effectiveness of the proposed theoretical model, the novel FOWLP test vehicle is manufactured for experimental measurement. Finally, the parametric study together with response surface methodology is further applied to provide guidelines for suppressing the warpage. Overall, the simulation modeling represents a feasible approach for predicting the process-induced warpage during the fan-out fabrication process.

A 1.9-dB NF K-Band Temperature-Healing Phased-Array Receiver Employing Hybrid Packaged 65-nm CMOS Beamformer and 0.1-μm GaAs LNAs

A 1.9-dB NF K-band phased-array receiver (RX) is presented, which employs the hybrid packaged 65-nm CMOS beamformer and 0.1- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> GaAs LNAs based on the fan-out wafer-level chip-scale packaging (WLCSP) technology. Power-efficient gain and phase tuning blocks are utilized to reduce power consumption. Temperature-healing design methodology is adopted to ensure nearly constant gain response versus temperature variations. The proposed phased-array RX only consumes 30.2-mW dc power per channel and achieves < 1.2-dB gain variation and < 0.9-dB NF variation from −40 °C to 85 °C.

Experimental and Numerical Investigations of the Warpage of Fan-Out Wafer-Level Packaging With SAW Filters

Fan-out wafer-level package (FOWLP) technology is an ideal scheme for the surface acoustic wave (SAW) filter packaging due to its potential to achieve extensive numbers of interconnects with standard pitches at any shrink pattern of the wafer. Nevertheless, predicting the wafer warpage in the processes timeline is an intractable but instructive issue. This article focuses on the evolution of the wafer warpage in different packaging processes and on ameliorating the warpage control scheme for the FOWLP with the (SAW) filters. Combined with the meso-mechanical model and the transversely isotropic model (TIM) of composite material, curing deformation is taken into account. Given the anisotropy coefficient thermal expansion (CTE) of the LiTaO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> , experiments and simulations are performed to analyze the influence of the process, structure, and material effects on the warpage. In addition, a new experimental process is proposed to reduce the impact of significant mismatches with submillimeter dies. Compared with the theoretical simulations, a class of warpage tests performed are achieved consensus. Finally, the warpage of the 8-in wafer is controlled within 2 mm.

Warpage Analysis and Prediction of the Advanced Fan-Out Technology Based on Process Mechanics

Moore’s law has remarkably promoted the development of semiconductor technology over the last decades. The advanced packaging involving novel materials, structures, and processes has contributed significantly to achieving excellent performance. Among various forms of advanced packaging, wafer-level-fan-out packaging is superior to standard wafer-level packaging in that it allows more input/output (I/O) connections, leading to landmark development for high-end devices. Furthermore, fan-out wafer-level package (FOWLP) technology enables heterogeneous integration of chiplets fabricated with different manufacturing processes, which provides integrated, sophisticated, and multifunctional dies with higher performance, lower cost, and tinier size. In packaging materials, processes, and structures, a thorough understanding of the process mechanics is necessary to ensure accuracy, while multiphysical field and multiscale modeling are beneficial to clarifying the internal mechanism of warpage. Process mechanics was applied to FOWLP and the characteristics were systematically expounded. Focusing on the warpage analysis of the embedded silicon fan-out (FO) wafer-level package, we introduced the principle of process mechanics and explored the material–structure–process interaction. The typical processes (including: 1) cleaning and litho cavity; 2) die attach and assignment; 3) dry film and dielectric layer 1 and patterning; 4) physical vapor deposition (PVD) seed layer 1 and patterning copper plating and redistribution layer (RDL) 1; 5) dielectric layer 2 and patterning; 6) PVD seed layer 2 and patterning copper plating and RDL 2; and 7) passivation layer, drop ball back grinding, and dicing) of the embedded silicon FO packaging are analyzed in detail to explore the warping evolution of individual processes. In addition, a material equivalent model of representative volume element (RVE) and an extended theoretical model of a multilayer structure were proposed. The comprehensive comparison for the extended theoretical model, experimental measurement, and finite element model (FEM) showed that the theoretical model is effective and relatively accurate. Overall, both the theoretical model and FEM are feasible approaches for predicting the warpage during the manufacturing process.

A Wideband mmWave Antenna in Fan-Out Wafer Level Packaging With Tall Vertical Interconnects for 5G Wireless Communication

A novel fan-out wafer-level packaging (FOWLP) technology with double-sided redistribution layers (RDLs) and tall copper vertical interconnects is described. The design of a dual-polarized magnetoelectric (ME) dipole antenna based on this new packaging technology is presented. It is shown that the antenna with a size of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$10\times10$ </tex-math></inline-formula> mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> achieves good impedance matching and a stable radiation pattern over a wide bandwidth from 25 to 43 GHz, which can cover most of the millimeter-wave (mmWave) bands of the fifth-generation (5G) mobile networks in different countries. The measurement results demonstrate that the antenna is well suited for FOWLP technology and can be used for phased-array modules in 5G wireless communication systems.

A Hybrid Antenna in Package Solution Using FOWLP Technology

Abstract Widespread millimeter wave applications have promoted rapid development of system in package (SiP) and antenna in package (AiP). Most AiP structures take the form of flip chip onto antenna substrate, where signal interconnect losses are introduced by solder bumps. The integration may be unavailable for chips with fine pad pitches. Fan-out wafer level package (FOWLP) with antenna patterning on redistributed layers (RDL) is another method for millimeter wave AiP. In this project, a hybrid integration AiP structure is developed. The microwave monolithic integrated circuit (MMIC) chip and antenna unit are integrated with chip-first FOWLP process. Multilayer organic substrate with fine pitch RDL interconnections meets the requirements of wideband antenna design. Modified coplanar waveguide is adopted to feed 2 × 2 aperture array formed on RDL layer. Package warpage is measured using Shadow Moire techniques. The antenna forms an aperture-coupled stacked patch array with bandwidth 25% and gain 8.5dBi for 60 GHz digital communication system. The proposed approach is a convenient hybrid integration solution adopting FOWLP process for millimeter wave AiP systems.

5-in-1 Fan-Out Wafer-Level Packaging Technology with One AI Chip and Four Memory Chips for Internet of Things Modules

5-in-1 Fan-Out Wafer-Level Packaging Technology with One AI Chip and Four Memory Chips for Internet of Things Modules

A Low-Loss and High-Isolation Transformer-Based mm-Wave SPDT with Integrated Fan-out Wafer Level Packaging

This paper proposes a low-loss and high-isolation transformer (TF)-based mm-wave single-pole double-throw (SPDT) switch. The center-tapped technique is employed at the secondary coil of TF to improve isolation performance. The TF is implemented with the metals in redistribution layers (RDLs) in integrated fan-out (InFO) wafer level packaging technology to obtain low insertion loss (IL) and small chip size as the TF usually dominates the area of SPDT. The control device of the SPDT is realized in 40[Formula: see text]nm bulk CMOS process. The simulated result shows the proposed SPDT achieves a minimum IL of 1.34[Formula: see text]dB and the IL is less than 2.2[Formula: see text]dB at 24–31[Formula: see text]GHz. The isolations are better than 27[Formula: see text]dB between two double-throw ports and better than 20[Formula: see text]dB between single-pole and double-throw ports, respectively. The proposed SPDT has a compact silicon size of 220[Formula: see text][Formula: see text] (with PADs) and its return losses are better than [Formula: see text]9[Formula: see text]dB at 24–31[Formula: see text]GHz and. This work explores a new chip-package co-design method for the SPDT and may have some guidance for the co-design of SPDT and antenna in package (AiP).

(Invited) Enabling Fan-out Wafer-Level Package (FOWLP) through Innovative Copper Electrodeposition Processes

IC packaging technology has evolved in a quite diverse manner over the past decade, addressing both high-end and low-end applications, resulting in approaches such as package-on-package (PoP), fan-out wafer-level package (FOWLP), 3D IC integration with through-silicon via (TSV), and 2.5D with TSV-Si interposer. FOWLP technology offers significant cost and performance advantages relative to other packaging approaches and is therefore receiving widespread adoption throughout the industry for applications such baseband processor and applications processor (AP). It is anticipated that this technology may be extended for high-end devices such as field-programmable gate array (FPGA) and graphics processing unit (GPU). As a result, FOWLP technology is expected to ramp at a strong growth rate over the immediate future. FOWLP technology comprises conventional under-bump metallization (UBM) and pillar/micro-pillar, as well as new routing/connection applications such as fine-line redistribution layer (RDL) (sub 5x5 mm), integrated via-RDL structures, and mega pillars (>150 mm). These new applications drive fundamental challenges in electrodeposition. Fine-line RDL applications present challenges for both lithography and electrochemical deposition (ECD) processes. For wafer handling, the reconstituted wafers used in FOWLP can exhibit significant warpage and maintaining feature dimensions across wafer topography becomes challenging. New electroplating technology is required to prevent physical degradation of the fine-line RDL. Etchants used for copper (Cu) wet etch will preferentially attack the interface between the Cu ECD line and the Cu physical vapor deposition (PVD) seed layer, resulting in an undercut that degrades the mechanical reliability. This undercut can be minimized by using innovative electroplating technology to reduce the thickness of the Cu PVD seed layer. Thermal cracking of the Cu line has also been posed as a key integration challenge. Grain engineering is discussed as one potential solution to overcome this issue. Many of the current FOWLP approaches include the adoption of multi-layer RDL which are fabricated from low dielectric polymer passivation layers and Cu ECD lines. Multi-layer RDL patterns can result in significant topography variation, which can impact other process integration challenges such as control of critical dimensions (CDs). To minimize topography variation, a new ECD reactor design is used to provide ultra-uniform Cu ECD. Mega pillars consist of 180-220 mm (200 mm average) Cu thickness while standard Cu pillar applications typically vary between 20 and 40 μm (30 mm average) thickness. This large disparity in thickness can translate to approximately 6x longer plating times if a similar deposition rate is used. The process of plating large features employed as interconnects often encounters mass transport limitations that can curtail the deposition rate. This effect is explored in detail via computational modeling. The aspect ratio of through-resist features is shown to have a severe impact on minimum fill time, where a high (4:1) aspect ratio feature takes more than 7.5 times as long to fill as a low (1.2:1) aspect ratio feature. Convection of the electrolyte above the surface of the photoresist, which is largely influenced by the ECD reactor design, is shown to have a pronounced impact on fill times over the range of feature dimensions. Furthermore, some integration requirements for mega pillars warrant extremely high within-die uniformities and flat bump shape. Attaining such high-quality plating performance can greatly minimize the downstream planarization requirements. This paper will focus on new innovations in Cu ECD processes for fine line RDL, multi-layer RDL, and mega pillar to enable FOWLP technology.

Simulation and Experimental Study of the Warpage of Fan-Out Wafer-Level Packaging: The Effect of the Manufacturing Process and Optimal Design

In this paper, warpage of fan-out wafer-level packaging (FOWLP) throughout the manufacturing process is investigated to minimize the warpage. FOWLP technology has the advantages of low cost, small form factor, efficient electrical performance, and increased input–output counts. The main benefit of fan-out packaging is that it utilizes the redistribution layer to interconnect the die and solder joints instead of using the substrate. However, warpage control is still a critical issue in the wafer molding process. Warpage is induced by the coefficient of thermal expansion mismatch between the die and the molding compound. Throughout the manufacturing process, the warpage of each step was recorded by utilizing the continuity simulation. The debonding process, grinding process, and annealing process at room temperature were analyzed via the simulation results and the experimental results. To simulate the wafer molding process in a continuous manner, the element birth and death technique was employed using finite-element modeling. This method can be used to reactive and deactivate elements when the material is added to or removed from the system. The results of the measurement and simulation were highly similar, with a difference of less than 10%. However, the results differed considerably when the wafer thickness was small. The results revealed a gap between the experimental testing and simulation modeling. Because of the wafer stiffness, the wafer is too thin to support the gravity force in the experimental testing process. Therefore, it is important to determine the calibration factor to decrease the gap between experimental testing and simulation modeling. In addition, it is crucial to determine the key factor controlling the warpage behavior and to minimize the warpage by evaluating the die arrangement and the die size in this paper. Overall, the simulation modeling represents a feasible approach for predicting the warpage during the manufacturing process.

Process and characterization of photo-definable organic–inorganic dielectric for wafer level packaging

The introduction of an organic–inorganic dielectric material into the redistribution layers in fan-out wafer level packaging technology has been investigated to improve mechanical stress, thermal stability, and electrical breakdown compared to organic dielectric materials. A photo-definable organic–inorganic dielectric material called polysilsesquioxane (PSSQ) has been studied in this work. The photo-definable PSSQ dielectric allows a simultaneous UV patterning and curing process. A PSSQ sample was prepared by spin-coating on a 6-in. Si wafer, pre-baking at 100 °C for 5 min, UV exposure, and then PGMA developing. The cured PSSQ films have a dielectric constant from 2.0 to 2.38 and dielectric loss from 0.0001 to 0.005. In addition, the 2 μm line patterns were obtained after 10 min of UV exposure. It has been demonstrated that PSSQ dielectric materials can provide excellent process capability of simultaneous UV patterning and curing process.

An Electromagnetic Bandgap Structure Integrated With RF LNA Using Integrated Fan-Out Wafer-Level Package for Gigahertz Noise Suppression

This paper presents a periodic electromagnetic bandgap (EBG) structure in the integrated fan-out wafer-level package (InFO-WLP) technology for gigahertz-band noise suppression. The proposed EBG structure consists of an $LC$ resonator with two symmetrical spiral inductors in series and a shunt metal–insulator–metal capacitor between power and ground planes. The third-order equivalent model of the EBG structure is also proposed and extracted by field solver ANSYS Q3D to model the performance. In addition, the EBG arrays with different sizes of unit cell and the corresponding stopband bandwidth and isolation were characterized. The measurement results show that the proposed $1 \times 4$ EBG array of 600- $\mu \text{m}$ square unit cell can achieve a 29.5-GHz stopband bandwidth together with an over 30-dB isolation level. Furthermore, by using the InFO-WLP technology, the proposed EBG structure is integrated with an RF low-noise amplifier (LNA) fabricated in a 16-nm FinFET technology as a case study to validate the power noise immunity. The experimental results show that the measured output spectrum of LNA integrated with the proposed EBG structure at the power plane can suppress the noise tone from −37.37 to −68.65 dBm.