Family Of Circuits Research Articles

Static performance and parasitic analysis of tapped‐inductor converters

Tapped-inductor provides the property of wider voltage conversion range similar to an auto-transformer and can be integrated to a switched-mode power converter to enhance the power conversion efficiency. Its low component count has attracted applications with extreme voltage conversion ratios. Circuit family is presented and a general tapping concept for diode, transistor or both has been described. Its boost converter version is used as an example for the study. Detailed comparisons between tapped-inductor boost and conventional boost are carried out, which include the comparison of voltage gain, component stress and efficiency with the presence of the parasitic components. Experimental results present solid verification of the analysis of performance of tapped-inductor boost converter under extreme conversion ratios. The proposed study has introduced formulations for both transistor and diode tapping and can be extended to other tapped-inductor DC-DC converters as a family of circuits, and thus provides an understanding of the effect of the parasitic components that affect the efficiency under extreme conversion ratio.

Nonuniform ACC Circuit Lower Bounds

The class ACC consists of circuit families with constant depth over unbounded fan-in AND, OR, NOT, and MOD m gates, where m > 1 is an arbitrary constant. We prove the following. ---NEXP, the class of languages accepted in nondeterministic exponential time, does not have nonuniform ACC circuits of polynomial size. The size lower bound can be slightly strengthened to quasipolynomials and other less natural functions. ---E NP , the class of languages recognized in 2 O(n) time with an NP oracle, doesn’t have nonuniform ACC circuits of 2 n o(1) size. The lower bound gives an exponential size-depth tradeoff: for every d, m there is a δ > 0 such that E NP doesn’t have depth- d ACC circuits of size 2 n δ with MOD m gates. Previously, it was not known whether EXP NP had depth-3 polynomial-size circuits made out of only MOD 6 gates. The high-level strategy is to design faster algorithms for the circuit satisfiability problem over ACC circuits, then prove that such algorithms entail these lower bounds. The algorithms combine known properties of ACC with fast rectangular matrix multiplication and dynamic programming, while the second step requires a strengthening of the author’s prior work.

COMPARISON OF LOGIC FAMILIES USING NAND GATE

A digital circuit is constructed from small electro nic circuits called logic gates that can be used to create combinational l is an idealized or physical device which implements a Boolean function . It is an arrangement of electrically controlled swi tches, They are the fundamental building block for high pe rformance data path circuits. integrated circuit devices can be constructed using several different designs methods which use differ ent logic families. different logic circuit families are compared. Powe r, delay and power -delay product are some of the performance paramet A digital circuit is constructed from small electro nic circuits called logic gates that can be used to create combinational l ogic. A logic It is an arrangement of electrically controlled swi tches, They are the fundamental building block for high pe rformance data path circuits. The monolithic digital integrated circuit devices can be constructed using several different designs methods which use differ ent logic families. In this paper delay product are some of the performance parameters used for

AND and/or OR: Uniform Polynomial-Size Circuits

We investigate the complexity of uniform OR circuits and AND circuits of polynomial-size and depth. As their name suggests, OR circuits have OR gates as their computation gates, as well as the usual input, output and constant (0/1) gates. As is the norm for Boolean circuits, our circuits have multiple sink gates, which implies that an OR circuit computes an OR function on some subset of its input variables. Determining that subset amounts to solving a number of reachability questions on a polynomial-size directed graph (which input gates are connected to the output gate?), taken from a very sparse set of graphs. However, it is not obvious whether or not this (restricted) reachability problem can be solved, by say, uniform AC^0 circuits (constant depth, polynomial-size, AND, OR, NOT gates). This is one reason why characterizing the power of these simple-looking circuits in terms of uniform classes turns out to be intriguing. Another is that the model itself seems particularly natural and worthy of study. Our goal is the systematic characterization of uniform polynomial-size OR circuits, and AND circuits, in terms of known uniform machine-based complexity classes. In particular, we consider the languages reducible to such uniform families of OR circuits, and AND circuits, under a variety of reduction types. We give upper and lower bounds on the computational power of these language classes. We find that these complexity classes are closely related to tallyNL, the set of unary languages within NL, and to sets reducible to tallyNL. Specifically, for a variety of types of reductions (many-one, conjunctive truth table, disjunctive truth table, truth table, Turing) we give characterizations of languages reducible to OR circuit classes in terms of languages reducible to tallyNL classes. Then, some of these OR classes are shown to coincide, and some are proven to be distinct. We give analogous results for AND circuits. Finally, for many of our OR circuit classes, and analogous AND circuit classes, we prove whether or not the two classes coincide, although we leave one such inclusion open.

On Best-Possible Obfuscation

An obfuscator is a compiler that transforms any program (which we will view in this work as a boolean circuit) into an obfuscated program (also a circuit) that has the same input-output functionality as the original program, but is unintelligible. Obfuscation has applications for cryptography and for software protection. Barak et al. (CRYPTO 2001, pp. 1---18, 2001) initiated a theoretical study of obfuscation, which focused on black-box obfuscation, where the obfuscated circuit should leak no information except for its (black-box) input-output functionality. A family of functionalities that cannot be obfuscated was demonstrated. Subsequent research has showed further negative results as well as positive results for obfuscating very specific families of circuits, all with respect to black box obfuscation. This work is a study of a new notion of obfuscation, which we call best-possible obfuscation. Best possible obfuscation makes the relaxed requirement that the obfuscated program leaks as little information as any other program with the same functionality (and of similar size). In particular, this definition allows the program to leak information that cannot be obtained from a black box. Best-possible obfuscation guarantees that any information that is not hidden by the obfuscated program is also not hidden by any other similar-size program computing the same functionality, and thus the obfuscation is (literally) the best possible. In this work we study best-possible obfuscation and its relationship to previously studied definitions. Our main results are: (1) A separation between black-box and best-possible obfuscation. We show a natural obfuscation task that can be achieved under the best-possible definition, but cannot be achieved under the black-box definition. (2) A hardness result for best-possible obfuscation, showing that strong (information-theoretic) best-possible obfuscation implies a collapse in the Polynomial-Time Hierarchy. (3) An impossibility result for efficient best-possible (and black-box) obfuscation in the presence of random oracles. This impossibility result uses a random oracle to construct hard-to-obfuscate circuits, and thus it does not imply impossibility in the standard model.

Black box measurements – Using a family of electrical circuits as a tool for self-guided learning in acoustical engineering

A partnership between Brazil’s first undergraduate program in Acoustical Engineering and the Institute of Technical Acoustics of RWTH Aachen University yielded in a didactic project that uses the engineering software MATLAB with the ITA-Toolbox to teach acoustic measurements. Simple electrical circuits are used to mimic typical behavior of acoustical systems. This low-cost solution has proven to be didactically very effective since it helps students to identify themselves with the measurement tasks. Two hardware solutions were developed-a simple oscillator circuit integrated into connectors of audio cables and a desktop box containing seven different transfer characteristics ranging from ideal linear and time-invariant to nonlinear and time-varying behavior. Undergraduate students of Acoustical Engineering used both devices in classroom experiments for self-guided learning by comparing their results to published results. Students were able to learn the fundamental concepts of acoustical measurements and to handle measurement tasks. Besides the practical experiences and the learning effect, the students were also encouraged to step into the open source routines of the software, understand the signal processing steps, adapt routines, and even write their own ones, e.g., a GUI that provides effective control of the measurement via touch-screens.

A class of almost-optimal size-independent parallel prefix circuits

Prefix computation is one of the fundamental problems that can be used in many applications such as fast adders. Most proposed parallel prefix circuits assume that the circuit is of the same width as the input size.In this paper, we present a class of parallel prefix circuits that perform well when the input size, n, is more than the width of the circuit, m. That is, the proposed circuit is almost optimal in speed when n>m. Specifically, we derive a lower bound for the depth of the circuit, and prove that the circuit requires one time step more than the optimal number of time steps needed to generate its first output. We also show that the size of the circuit is optimal within one. The input is divided into subsets, each of width m−1, and presented to the circuit in subsequent time steps. The circuit is compared with functionally similar circuits of (Lin, 1999 [9]; Lin and Hung, 2009 [12]) to show its outperforming speed. When n>m, the circuit is shown to be faster than the family of waist-size optimal circuits with waist 1 (WSO-1) of the same width and fan-out.

The dynamics of hybrid metabolic-genetic oscillators

The synthetic construction of intracellular circuits is frequently hindered by a poor knowledge of appropriate kinetics and precise rate parameters. Here, we use generalized modeling (GM) to study the dynamical behavior of topological models of a family of hybrid metabolic-genetic circuits known as "metabolators." Under mild assumptions on the kinetics, we use GM to analytically prove that all explicit kinetic models which are topologically analogous to one such circuit, the "core metabolator," cannot undergo Hopf bifurcations. Then, we examine more detailed models of the metabolator. Inspired by the experimental observation of a Hopf bifurcation in a synthetically constructed circuit related to the core metabolator, we apply GM to identify the critical components of the synthetically constructed metabolator which must be reintroduced in order to recover the Hopf bifurcation. Next, we study the dynamics of a re-wired version of the core metabolator, dubbed the "reverse" metabolator, and show that it exhibits a substantially richer set of dynamical behaviors, including both local and global oscillations. Prompted by the observation of relaxation oscillations in the reverse metabolator, we study the role that a separation of genetic and metabolic time scales may play in its dynamics, and find that widely separated time scales promote stability in the circuit. Our results illustrate a generic pipeline for vetting the potential success of a circuit design, simply by studying the dynamics of the corresponding generalized model.

Solving search problems by strongly simulating quantum circuits

Simulating quantum circuits using classical computers lets us analyse the inner workings of quantum algorithms. The most complete type of simulation, strong simulation, is believed to be generally inefficient. Nevertheless, several efficient strong simulation techniques are known for restricted families of quantum circuits and we develop an additional technique in this article. Further, we show that strong simulation algorithms perform another fundamental task: solving search problems. Efficient strong simulation techniques allow solutions to a class of search problems to be counted and found efficiently. This enhances the utility of strong simulation methods, known or yet to be discovered, and extends the class of search problems known to be efficiently simulable. Relating strong simulation to search problems also bounds the computational power of efficiently strongly simulable circuits; if they could solve all problems in P this would imply that all problems in NP and #P could be solved in polynomial time.

Development of a Quick Dynamic Response Maximum Power Point Tracking Algorithm for Off-Grid System With Adaptive Switching (On–Off) Control of dc/dc Converter

This paper presents a new approach of Adaptive Search Control Method to perform maximum power point tracking (MPPT) in solar panels (SP). The suggested approach adapts the operation point (current I and voltage V) of the solar panel so quickly that it tracks MPP under the harshest environmental conditions by incorporating a flexible switching in a Boost dc/dc converter, which connects the photovoltaic (PV) panel to the load. The usage of a flexible switching control increases the dynamic response of MPPT and the efficiency of tracking. A dedicated simulink (matlab) model was developed for validation of the proposed MPPT method which was verified through multiple simulation conditions. Based on these results, the prototype system for evaluating the suggested method was developed and assembled. This prototype was developed on the base of a photonic integrated circuit (PIC) family microcontroller unit with an external circuit for accurate voltage and current measurements. The technical characteristics of the developed system (efficiency and tracking speed) have been verified experimentally with a 100 W c-Si solar panel under various environmental conditions. The results of measured and estimated MPPT efficiency were represented.

Permanent does not have succinct polynomial size arithmetic circuits of constant depth

We show that over fields of characteristic zero there does not exist a polynomial p(n) and a constant-free succinct arithmetic circuit family {Φn} using division by constants,3 where Φn has size at most p(n) and depth O(1), such that Φn computes the n×n permanent. A circuit family {Φn} is succinct if there exists a nonuniform Boolean circuit family {Cn} with O(logn) many inputs and size no(1) such that Cn can correctly answer direct connection language queries about Φn – succinctness is a relaxation of uniformity.To obtain this result we develop a novel technique that further strengthens the connection between black-box derandomization of polynomial identity testing and lower bounds for arithmetic circuits. From this, we obtain the lower bound by giving an explicit construction, computable in the polynomial hierarchy, of a hitting set for arithmetic circuits.

Gauge invariants of eigenspace and eigenvalue anholonomies: examples in hierarchical quantum circuits

A set of gauge invariants are identified for the gauge theory of quantum anholonomies, which comprise both the Berry phase and an exotic anholonomy in eigenspaces. We examine these invariants for hierarchical families of quantum circuits whose qubit size can be arbitrarily large. It is also found that a hierarchical family of quantum circuits generally involves an NP-complete problem.

Uniform derandomization from pathetic lower bounds

The notion of probabilistic computation dates back at least to Turing, who also wrestled with the practical problems of how to implement probabilistic algorithms on machines with, at best, very limited access to randomness. A more recent line of research, known as derandomization, studies the extent to which randomness is superfluous. A recurring theme in the literature on derandomization is that probabilistic algorithms can be simulated quickly by deterministic algorithms, if one can obtain impressive (i.e. superpolynomial, or even nearly exponential) circuit size lower bounds for certain problems. In contrast to what is needed for derandomization, existing lower bounds seem rather pathetic. Here, we present two instances where 'pathetic' lower bounds of the form n(1+ε) would suffice to derandomize interesting classes of probabilistic algorithms. We show the following: -If the word problem over S(5) requires constant-depth threshold circuits of size n(1+ε) for some ε > 0, then any language accepted by uniform polynomial size probabilistic threshold circuits can be solved in subexponential time (and, more strongly, can be accepted by a uniform family of deterministic constant-depth threshold circuits of subexponential size). -If there are no constant-depth arithmetic circuits of size n(1+ε) for the problem of multiplying a sequence of n 3×3 matrices, then, for every constant d, black-box identity testing for depth-d arithmetic circuits with bounded individual degree can be performed in subexponential time (and even by a uniform family of deterministic constant-depth AC(0) circuits of subexponential size).

A generalized Pólya urn and limit laws for the number of outputs in a family of random circuits

We introduce a generalized Polya urn model with the feature that the evolution of the urn is governed by a function which may change depending on the stage of the process, and we obtain a Strong Law of Large Numbers and a Central Limit Theorem for this model, using stochastic recurrence techniques. This model is used to represent the evolution of a family of acyclic directed graphs, called random circuits, which can be seen as logic circuits. The model provides asymptotic results for the number of outputs, that is, terminal nodes, of this family of random circuits.

A MODULAR SYNTHETIC DEVICE TO CALIBRATE PROMOTERS

In this contribution, a design of a synthetic calibration genetic circuit to characterize the relative strength of different sensing promoters is proposed and its specifications and performance are analyzed via an effective mathematical model. Our calibrator device possesses certain novel and useful features like modularity (and thus the possibility of being used in many different biological contexts), simplicity, being based on a single cell, high sensitivity and fast response. To uncover the critical model parameters and the corresponding parameter domain at which the calibrator performance will be optimal, a sensitivity analysis of the model parameters was carried out over a given range of sensing protein concentrations (acting as input). Our analysis suggests that the half saturation constants for repression, sensing and difference in binding cooperativity (Hill coefficients) for repression are the key to the performance of the proposed device. They furthermore are determinant for the sensing speed of the device, showing that it is possible to produce detectable differences in the repression protein concentrations and in turn in the corresponding fluorescence in less than two hours. This analysis paves the way for the design, experimental construction and validation of a new family of functional genetic circuits for the purpose of calibrating promoters.

Level-Shifting Multiple-Input Switched-Capacitor Voltage Copier

In this paper, a level-shifting voltage-copier circuitry is introduced to convert one or two input voltage levels to eight voltage levels. The voltage copier consists of five kinds of conversion circuits. Each circuit includes only six to seven electronic components, which can ensure the simplicity and reliability of the voltage copier. A resonant inductor is further added to improve the performance of these circuits. A high-efficiency resonant voltage copier is introduced. Simulation and experimental results verify the performance of the voltage copier and the design method. The circuit family provides a useful method for voltage conversion under multiple-input sources to multiple outputs.

Locality from Circuit Lower Bounds

We study the locality of an extension of first-order logic that captures graph queries computable in ${AC}^0}$, i.e., by families of polynomial-size constant-depth circuits. The extension considers first-order formulas over relational structures which may use arbitrary numerical predicates in such a way that their truth value is independent of the particular interpretation of the numerical predicates. We refer to such formulas as Arb-invariant first-order. We consider the two standard notions of locality, Gaifman and Hanf locality. Our main result gives a Gaifman locality theorem: An Arb-invariant first-order formula cannot distinguish between two tuples that have the same neighborhood up to distance $(\log n)^c$, where $n$ represents the number of elements in the structure and $c$ is a constant depending on the formula. When restricting attention to string structures, we achieve the same quantitative strength for Hanf locality. In both cases we show that our bounds are tight. We also present an application of our results to the study of regular languages. Our proof exploits the close connection between first-order formulas and the complexity class ${AC}^0}$ and hinges on the tight lower bounds for parity on constant-depth circuits.

Digital and Analogue Integrated Circuits in Silicon Carbide for High Temperature Operation

A need for high temperature integrated circuits is emerging in a number of application areas. As Silicon Carbide power discrete devices become more widely available, there is a growing need for control ICs capable of operating at the same temperatures and mounted on the same modules. Also, the use of high temperature sensors, in, for example, aero engines and in deep hydrocarbon and geothermal drilling applications results in a demand for high temperature sensor interface ICs. This paper presents new results on a range of simple logic and analogue circuits fabricated on a developing Silicon Carbide CMOS process which is intended for mixed signal integrated circuit applications such as those above. A small family of logic circuits, pin compatible with the 74xx series TTL logic parts, has been designed, fabricated and tested and includes, for example, a Quad Nand gate and a Dual D-type flip-flop. These have been found to be functional from room temperature up to 400°C. Analogue blocks have been investigated with a view to using switched capacitor or autozero techniques to compensate for temperature and time induced drifts, allowing very high temperature operation.

ON THE CIRCUIT-SIZE OF INVERSES

We reprove a result of Boppana and Lagarias: If [Formula: see text] then there exists a partial function f that is computable by a polynomial-size family of circuits, but no inverse of f is computable by a polynomial-size family of circuits. We strengthen this result by showing, if [Formula: see text], that there exist length-preserving total functions that are one-way by circuit size and that are computable in uniform polynomial time. We also prove, if [Formula: see text], that there exist polynomially balanced total surjective functions that are one-way by circuit size; here non-uniformity is used.

Investigation of the relationship between the gray zone and the clock frequency of aJosephson comparator

The Josephson comparator is one of the fundamental building blocks of rapid single fluxquantum (RSFQ) electronics. Within this circuit family it is the exclusive device whichprovides logical data processing. The Josephson comparator is also the basic decisionelement for very fast analog-to-digital converters and sampler circuits for low input powerand high-bandwidth signals based on the RSFQ technique. The performance of thosedevices is fundamentally determined by the characteristics of the Josephson comparator. Inthis study the gray zone dependency on the clock frequency of a Josephson comparatoris investigated by simulations concerning the influence of thermal noise. Thisinvestigation is performed for a series of operating points defined by the biascurrent and different noise levels defined by the operating temperature. In contrastto former investigations, we analyzed the comparator embedded in a realisticenvironment for output data processing. We identified a characteristic clock frequencyfc for a comparatortopology designed for a 1 kA cm − 2 niobium fabrication technology. The gray zone of 8 µA remains constant forclock frequencies below fc = 15 GHz and starts to increase for larger frequencies. We also found out that this characteristicfrequency is independent of the intensity of thermal noise and therefore independent oftemperature.