False Paths Research Articles

On the History of Modern Philosophy (review)

BOOK REVIEWS 621 can be already found in his lectures: dialectic in formal logic leads to the illusions of sophistry. Logic cannot be used as an organon. It is only a canon, a negative criterion of truth. Conrad's book deals only with the architectonic of the first Cr/t/que and its roots in Kant's conception of formal logic on the highest level of generality. Questions about the substructures of the architectonic are never mentioned. Why is it, for instance, that the copulative judgment, and with it conjunction, present in the logical textbooks of the time, in Meier, and in Kant's reflections, vanishes somewhere in the development leading to the first Cr/t/que and the Jaesche Logic? Was it dropped only because there was no place for it in the construction of a balanced architectonic of the table of judgments? Is this another of the surprising movements in Kant's logic, like the move from the disjunctive judgment to the category of reciprocal causation? A student of logic knows that the biconditional is the natural logical counterpart of reciprocal causality, but also that the biconditional is precisely the negation of strict disjunction. Even logical problems belonging to the highest level of the architectonic analyzed in the book are not mentioned. Definition and division of concepts had their place in the textbooks of the time, in Meier, and in Kant's lectures in the chapter on concept in the doctrine of elements. Its place in the Jaesche Logic is taken by the doctrine of method. Virtually nothing else can be found in the doctrine of method, i.e., this doctrine has no function at all in formal logic except as a replacement for definition and division. The author is an excellent philologist and her skill in the techniques of the historical reconstruction of terminological and conceptual developments is outstanding . But she has, it seems, no interest in genuine logical questions. The book is a serious disappointment for readers interested in formal logic in the narrower sense and, therefore, also in transcendental logic. THOMAS M. Sv.EBOH~t Johannes Gutenberg-Universitiit, Mainz F. W. J. von Schelling. On the History of Modern Philosophy. Translation, Introduction, and Notes by Andrew Bowie. Cambridge: Cambridge University Press, 1994. Pp. xi + 195. Cloth, $54.95. Paper, $17.95. As long as Schelling's philosophical achievement was framed within the familiar dialectical structure of German idealism as defined by Hegel, it was perhaps inevitable that his later philosophy, much of which explicitly challenged and went beyond that tradition , could be dismissed as a lengthy and bizarre false path. Walter Schulz's and, more recently, Manfred Frank's efforts to reconsider the significance of the later Schelling have elicited considerable critical reaction in Germany and France but as yet have found few echoes among English-language scholars. Therefore the appearance of the present translation is an especially welcome event, even if one does not share Bowie's view that the lectures On theHistory ofModern Philosophy is "the best text through which [to] approach the work of the later Schelling" (x). Bowie bases this claim on the fact that the Lectures, as he calls them, contain the most extended version of Schelling's insight- 622 JOURNAL OF THE HISTORY OF PHILOSOPHY 34:4 OCTOBER 1996 ful and influential critique of Hegel, and that parts of the Lectures, for which he gives a probable date of 1833-34 or 1836-37, were adopted almost verbatim in Schelling's 1841-42 Berlin lectures, showing that Schelling thought well enough of these criticisms to repeat them even while occupying what had formerly been Hegel's chair in philosophy. Bowie's introduction situates Schelling in his historical moment, and retells the history of German idealism not as the story of the triumphant Hegelian synthesis, but as a developing demonstration of why Hegel's attempt to reach a final resolution in philosophy did not and could not succeed. This effort is carried on in greater detail in Bowie's Schelling and Modern European Philosophy (London, 1993), which also presents an audacious yet elegant argument for Schelling's relevance to our present postmetaphysical plight. The signal achievement of the introduction to...

Efficient logic-level timing analysis using constraint-guided critical path search

As the operating speed of digital circuits dramatically increases with the advance of VLSI technology, it is becoming more critical to ensure that the circuits are free from timing-related design errors. In a traditional static timing approach nonfunctional paths cannot be distinguished from functional ones since the functionality of a circuit is ignored. This often results in overestimation of circuit delay and can degrade the circuit performance. In today's design methodology where the use of automated logic synthesis and module-based design are popular, circuits with a very large number of nonfunctional (false) paths are common. This paper describes an efficient logic-level timing analysis approach that can provide an accurate delay estimate of a digital circuit which may have many long false paths. By using logic incompatibilities in a circuit as constraints for critical path search, the algorithm determines the longest sensitizable path without explicit path enumeration. Since the number of false paths that can be implicitly eliminated is potentially exponential to the number of path constraints, performance improvement is significant.

Valid clock frequencies and their computation in wavepipelined circuits

It is known that wavepipelined circuits offer high performance, because their maximum clock frequencies are limited only by the path delay differences of the circuits, as opposed to the longest path delays. For proper operation, precision in clock frequency is essential. Using a new representation, Timed Boolean Functions, we derive analytical expressions for valid clocking intervals in terms of topological, 2-vector, and single vector delays, both the longest and the shortest. These intervals take into account both circuit functionality and timing characteristics, thus eliminating the pessimism caused by long and short false paths, and include effects of circuit parameters such as delay variations, clock skews, and setup and hold times of flip flops. In addition, we show that these intervals subsume Cotten's lower bound on valid clock period. Further, we study the problem of computing all enact valid clocking intervals and its computational complexity by demonstrating discontinuity and nonmonotonicity of the harmonic number H(/spl tau/) (the number of valid simultaneous data waves allowed) as a function of the clock period /spl tau/. Finally, we propose algorithms to compute the exact valid intervals for a given set of harmonic numbers and demonstrate performance enhancement of balanced circuits from ISCAS benchmarks with gate delay variations.

Photography, Allegory, and Labor

There is a story about photography that we all know. It is the tale of photography's struggle to be regarded as a fine art. After numerous setbacks and false paths, the story suggests, the banner of photography was eventually planted firmly on the pinnacle of art. The problem is not so much that this tale is wrong, but rather that it is one part of a much more complex narrative. Photography was, and is, an allotropic mode of representation that, like the element carbon, exists in two different forms. It too has both its precious and commonplace forms because the elevated art picture and the vulgar document make up two parts of a historical process. An adequate account of photography in the nineteenth century must reflect this dual existence. To do so will not leave the traditional story of photographic art untouched. This essay seeks to open out photography onto a series of wider and deeper historical questions than those offered by the familiar tale of its relation to art. In particular, I am concerned with deploying the example of photography in order to examine the emerging narratives of industry in nineteenth-century England. Studied in this manner, photography will lead us directly into matters of substance—namely, into the taxonomy of industrial knowledge and its relation to the fetishism of commodities.

A polynomial-time heuristic approach to solving the false path problem

In this paper we present a new approach to solving the false path problem. The method is based on our previous work on Timed Boolean Algebra [13]. Given a logic circuit, we first derive timed Boolean expressions to model its dynamic behavior. Then, for each term in the expressions, we compute its corresponding sensitizability function, expressed in conjunction normal form; and use an expression in product form to approximate the function. Finally we remove the redundant terms whose sensitizability functions are not satisfiable and determine the maximal delays from the terms remained. Complexity analysis shows that our method identifies false paths and computes delays for sensitizable paths in polynomial time, while experimental results on ISCAS benchmark circuits prove its better efficiency and effectiveness.

The dangers of simplistic delay models

The identification of sensitizable paths and the determination of path delays play key roles in many delay fault testing schemes. In this paper we examine a range of gate delay models with respect to their impact on identifying both sensitizable paths and maximum circuit delays in combinational logic circuits. We provide recommendations on the “minimum acceptable” model for identifying critical paths, and a minimum acceptable model for determining maximum circuit delays. In particular, we recommend against the use of delay models which fail to distinguish between rise and fall delays. Such models, including the commonly-used “unit-delay” model, are shown to significantly misrepresent circuit delay behaviour, particularly with respect to critical paths and long false paths.

Fast true delay estimation during high level synthesis

This paper addresses the problem of true delay estimation during high level design. The true delay is the delay of the longest sensitizable path in the resulting circuit, as opposed to the topological delay which is the delay of the longest path in the circuit. The existing delay estimation techniques either estimate the topological delay, which may be pessimistic if the longest path is unsensitizable or false, or estimate the true delay using gate-level timing analysis which may be prohibitively expensive. Resource sharing in high level synthesis can create false paths in the circuit implementation. Hence, determining the clock period using topological delay can be unduly conservative, resulting in excessive hardware to meet tight timing specifications. In this paper, we introduce an efficient technique to compute an estimate of the true delay. The proposed technique relies on partitioning the paths in the circuit and topological delay computation, and not on path sensitization. The paths in the implementation are partitioned into two sets given the high level information on scheduling and resource sharing: the complete determining path set (CDP/sub R/) and the nondetermining path set (NDP/sub R/). We prove that the delay of the longest path in CDP/sub R/ is lower bounded by the true delay and upper bounded by the topological delay of the circuit. Consequently, an estimate of the true delay of the resulting circuit can be computed by measuring the topological delay of the longest path in CDP/sub R/. We have developed a Functional delay ESTimation tool (FEST). Experimental results on a set of benchmarks reveal the following: approximately 50% of all paths are in NDP/sub R/ and can be ignored for true delay estimation, and the true delay estimates are on the average 15% less than the topological delay. The high level true delay estimates are accurate, as verified by comparing with the true delays obtained by gate-level timing analysis on actual implementations. Furthermore, results reveal that high level true delay estimation can be done very fast, even when gate-level true delay estimation becomes infeasible.

Exploiting multicycle false paths in the performance optimization of sequential logic circuits

This paper addresses the performance optimization problem for sequential logic circuits. It is shown how the notion of false paths, traditionally defined for combinational logic circuits, can be extended to the sequential context by considering the operation of the circuit over multiple clock-cycles. These multicycle false paths can be removed from the circuit using techniques similar to those proposed for combinational logic circuits. This observation offers new techniques to improve the performance of sequential logic circuits. An implementation of an algorithm that uses these ideas shows significant performance improvement on some typical benchmark circuits at a modest area overhead.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Functional timing analysis using ATPG

Paths that are never exercised are referred to as false paths and timing analysis that ignores the delay contribution of these paths is referred to as functional timing analysis. Such timing analysis provides a more accurate estimate of circuit delay compared to conventional static timing analysis. We show how unmodified conventional Automatic Test Pattern Generators (ATPG) for stuck-at faults can be used for functional timing analysis without sacrificing computational efficiency in comparison with existing approaches to the same problem. This is a significant result since it enables us to use the entire body of work in ATPG for this problem and relieves us from re-inventing new solutions for this problem. The basic algorithm can be used under an arbitrary delay model. We provide delay computation results for all the ISCAS benchmark examples under the unit-delay and the mapped-delay models.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A LOOP-BASED SCHEDULING ALGORITHM FOR HARDWARE DESCRIPTION LANGUAGES

This paper presents Dynamic Loop Scheduling (DLS), a loop-based algorithm that can efficiently schedule large, control-flow dominated designs. It compares favourably with results produced for traditional path-based approaches and at the same time requires much less overhead to implement. The high-performance of DLS is due mainly to the inclusion of loop feedback edges in the control-flow graph and the interruption of the path generation on the fly. The latter eliminates the generation of false paths thereby avoiding the path explosion problem.

Circuit structure relations to redundancy and delay

The existence of redundant stuck-faults in a logic circuit is potentially detrimental to high-speed operation, especially when there are false paths that are longer than the circuit delay. Keutzer, Malik, and Saldanha (KMS) in IEEE transactions of Computer Aided Design, vol. 10, no. 4, p. 427, April 1991 have proved that redundancy is not necessary to reduce delay by presenting an algorithm that derives an equivalent irredundant circuit from a given redundant circuit, with no increase in delay. The KMS algorithm consists of an iterative loop of timing analysis, gate duplications, and redundancy removal to successively eliminate long false paths. In this paper we resolve the main bottlenecks of the KMS algorithm by providing an efficient single-pass algorithm to simultaneously remove all long false paths from a given circuit. We achieve this by relating a circuit structure property based on path lengths to the testability (redundancy) and delay. The application of this algorithm to a variety of related logic synthesis problems is described.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

An efficient parallel critical path algorithm

The problem of identifying one of the longest sensitizable paths in a circuit is called a critical path problem. Several critical path algorithms have been proposed in the last few years. However, due to the long computation time required to produce accurate results, these algorithms may not be able to generate any result for large designs with many long false paths unless the accuracy of the results is compromised. Parallel processing seems to be an appropriate way to speed up the required computation. In this paper, we study the parallel algorithms for critical path problem. We first present a sensitization criterion. Based on this sensitization criterion an algorithm called DT-algorithm, which is a variation of the D-algorithm with stable time range of signals also taken into consideration, is developed. The DT-algorithm is especially suitable and can be used to determine the sensitizability of a given path in a parallel processing environment. We also present an implementation of parallel DT-algorithm that can be executed on a shared memory multiprocessor. The experimental results show that a reasonable speed-up can be obtained.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Timed Boolean calculus and its applications in timing analysis

Introduces a formalism, called timed Boolean calculus (TBC), and its applications to solving the false path problem in timing analysis. TBC is an extension of conventional Boolean algebra with a delay operator to facilitate modeling the timing behavior of logic circuits. By performing algebraic manipulations on timed Boolean expressions, the actual maximal delays of logic circuits can be obtained. The delay information can then be used by a path reporting algorithm to detect the long false paths, thereby identifying the paths which need be optimized to meet timing constraints. The authors have developed a timing analysis tool based on TBC and tested on ISCAS benchmarks. Experimental results are shown to justify the effectiveness and efficiency of the proposed TBC and algorithms.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Combined topological and functionality-based delay estimation using a layout-driven approach for high-level applications

We discuss the problem of accurate delay estimation of cell-based designs, prior to any physical design tasks. For this purpose, we require accurate wire-length estimates, since wire delays contribute significantly to the overall delay. We present a new technique for wire-length estimation based on a combination of analytical and constructive approaches. Given these wire-length estimates and the cell delays, it is possible to provide worst case delay paths in the design based on the circuit topology. We have also extended our technique to consider false paths, which provides a more accurate functionality based estimate that takes into account the estimated layout information. We validate our technique using the standard MCNC benchmarks. Our results indicate an average 7% accuracy in the worst case delay predictions for designs with up to about 2800 cells.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Statistical timing analysis of combinational logic circuits

Efficient methods for computing an exact probability distribution of the delay of a combinational circuit, given probability distributions for the gate and wire delays, are developed. The derived distribution can give the probability that a combinational circuit will achieve a certain performance, across the possible range. This information can then be used to predict the expected performance of the entire circuit. The techniques presented target fast analysis as well as reduced memory requirements. The notion of a correct approximation, based on convex inequality, which never overestimates the percentage of circuits that will achieve any given performance is defined. It is shown that given the assumption that all the topologically longest paths are responsible for the delay, the computation technique provides a correct probabilistic measure in the sense given above. Methods are given to identify and to ignore false paths in the probabilistic analysis, so as to obtain correct and less pessimistic answers to the performance prediction question. Some practical results are given for a number of benchmark combinational circuits.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Computation of floating mode delay in combinational circuits: practice and implementation

Delay computation in combinational logic circuits is complicated by the existence of unsensitizable (false) paths and this problem is arising with increasing frequency in circuits produced by high-level synthesis procedures. Various sensitization conditions have been proposed in the past to eliminate false paths in logic circuits, but the authors use a recently developed single-vector condition, that is known to be necessary and sufficient for a path to be responsible for the delay of a circuit (i.e., true) in the floating delay model. They build on this theory and develop an efficient and correct delay computation algorithm, for the floating mode delay. The algorithm uses a technique called timed-test generation and can be incorporated into any stuck-at fault test generation framework. The authors describe in detail an implementation of the timed-test generation algorithm that uses both logical and timed forward/backward implication and backtrace procedures to simultaneously prove the truth or falsity of sets of paths in the circuit. Logical and temporal conflict detection during implication and backtrace are used to speed up the algorithm. Unlike previous techniques, the algorithm remains highly efficient: even when a large number of distinct gate and path delays exist in the given circuit.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

The use of RTL descriptions in accurate timing verification and test generation (VLSI)

The authors discuss the use of high-level information in two major problems of VLSI system design: (1) accurate timing verification to eliminate false paths due to reconvergent fan-out, redundancy, and control signal constraints, and (2) testing for stuck-at-faults. The register-transfer-level (RTL) descriptions provide the set of control signals for valid data operations. Using this set of control signals, the timing verifier can perform an efficient estimation of critical path delays for only valid data transfers. This approach to critical path justification can be extended to test generation for a class of sequential circuits where all latches and memory elements can be explicitly identified. Test generation for complex VLSI circuits composed of many interconnected modules is discussed. Sequential propagation and justification of signals are carried out using the data flow information. Results based on an implementation of the algorithms are presented. >

Timing verification using statically sensitizable paths

A new approach to the false path problem in timing verifiers is presented. This approach is based on the modeling of both the logic and timing behavior of a circuit. Using the logic propagation conditions associated with each delay, efficient algorithms have been developed to find statically sensitizable paths. These algorithms simultaneously perform a longest path search and a partial verification of the sensitization of the paths. The resulting paths undergo a final and complete sensitization. The algorithms find the longest statically sensitizable path, whose length is a lower bound to the critical path length, and its associated sensitizing input vector. The algorithms can be easily modified to provide an ordered list of all the statically sensitizable paths above a given threshold. An initial analysis of the circuit by the PERT algorithm guides the critical path search and allows pruning of subgraphs that cannot lead to the solution. Results show that these techniques succeed in curbing the combinatorial explosion associated with the longest statically sensitizable path search. >

Efficient false path elimination algorithms for timing verification by event graph preprocessing

Accurate timing verification and optimization methods require algorithms that exclude false paths. Recently published methods for critical path searches that eliminate false paths, can take long evaluation times for complex time-optimized circuits. In this paper a new

Back to Full Employment: Old Instruments, New Methods

The old Keynesian instruments of monetary and fiscal policies aimed at full employment are currently ineffective. But the monetary instrument can be freed by writing off rather than rescheduling the developing-country debts that cannot be paid and by replacing the private U.S. dollar currency system with a system in which debt limits are specified and controlled by the International Monetary Fund and special drawing rights. Fiscal policy also can make an important contribution to national full employment, despite budgetary constraints. This it can do by promoting human capital rather than real capital and by not treating the black economy as a false path from growth but as its continuation and extension into postindustrial times.