Fall Delay Research Articles

Contention Mitigation based Level Shifter Architecture

Energy efficiency is one of the most important issues that needs to be solved in the current system on chip design. To overcome this issue, many circuits inside the chip run at low power. However there are some blocks like memories that run at relatively higher voltages. This means, modern day SOC contains different voltages running through it. The problem arises when two blocks operating at different voltages want to communicate with each other. This problem is solved by using Level Shifters as an interfacer between the blocks. The function of Level Shifter is to convert voltage level of input signal to that of the output. In this paper a cross coupled architecture of Level Shifter is proposed which operates between 1.5v and 5v. The speciality of this architecture is there is less contention between pull up network and pull down network, which reduces the rise and fall delay significantly. The proposed design is simulated at different operating conditions and the functionality is checked.

FPGA LUT delay degradation due to HCI: Experiment and simulation results

Reliability of advanced VLSI circuits becomes more and more important as both product designers and manufactures relentlessly pursue technology advantages and stretch device physical limits to capitalize the consumer electronic market. In this paper, we focus on aging degradation of the Look-Up Table (LUT) on FPGAs. We have characterized the delay degradation of LUT dependent on the duty cycle and the frequency of stress signal. We have identified that the HCI degradation mechanism affects the fall delay more than the rise delay, it is related directly to the frequency stress and independent from the duty cycle. In addition, we built a model of the delay degradation due to HCI depending on switching frequency of stress signal and the aging time. Furthermore, we identified the relation between the effect of each aging transistor and the LUT delay for the HCI aging mechanism. This work is ideal for modelling the LUT aging mechanisms in FPGA.

Comparative Analysis of Metastability with D FLIP FLOP in CMOS Circuits

appropriate choice of flip-flop topologies is of essential importance in the design of integrated circuits for CMOS VLSI high-performance and high-speed circuits. The understanding of the suitability of the flip-flops and select the best topology for a given application is important to meet the need of the design to meet low power and high performance circuit subject. This work shows a wide area comparison exist in D flip-flop, this provides a wide study of the topologies in terms of power dissipation, delay, and rise delay and fall delay time. KeywordsD Latch, Flip-Flop, Microwind.

Area-efficient reconfigurable ring oscillator for device and circuit level characterization of static and dynamic variations

Accurate characterization of transistor variation under dynamic switching condition has become important for reliable digital circuit design. This paper proposes a reconfigurable ring oscillator (RO) structure which enables measurement of transistor level variation. Each inverter stage in the RO can be configured into several delay modes. The delay of a particular inverting stage can be made dominant by configuring an inhomogeneous RO structure. By scanning the inhomogeneous stage, delay variation of each stage can be measured. Furthermore, pMOSFET and nMOSFET variation can be measured separately by making only rise or fall delay dominant. Specific transistor with random telegraph noise (RTN) in the inhomogeneous stage can be identified by reconfiguring the inhomogeneous stage. Thus, using a single RO, static delay variation as well as dynamic variation such as RTN can be measured. The area for a 127-staged reconfigurable RO including peripheral circuits is only 0.0085 mm2 thus area-efficient measurement becomes possible. Measurement results from a 65-nm test chip shows the validity of the proposed circuit structure.

Impact of Temperature Variations on the Device and Circuit Performance of Tunnel FET: A Simulation Study

The paper presents a comprehensive comparison study of p-i-n and p-n-p-n tunnel field-effect transistor (TFET) architectures and the impact of temperature on their dc and circuit performance. The impact of a hetero-gate (HG) dielectric on the circuit performance also forms the part of the study. The device performance of p-i-n and p-n-p-n TFET with high-k dielectric and HG dielectric and the effect of temperature on the drain current characteristics, Ion/Ioff, and threshold voltage has been investigated and compared with MOSFET. Furthermore, the variations in the inverter (n-TFET with resistive load) transient characteristics and the fall delay due to temperature variations are studied using mixed mode simulations carried out with ATLAS device simulation software. Results reveal that TFET exhibits weak temperature dependence when the current conduction is band-to-band tunneling dominated, while the temperature dependence increases in the off-state regime, and the fall delay of resistive load n-TFET inverter decreases with increasing temperature.

A gate-delay model focusing on current fluctuation over wide range of process–voltage–temperature variations

This paper proposes a gate-delay model suitable for timing analysis that takes into consideration wide-ranging process–voltage–temperature (PVT) variations. The proposed model translates an output-current fluctuation due to PVT variations into modifications of the output load and input waveform. After translation, any conventional model can compute delay taking into account PVT variations by using the modified output load and reshaped input waveform. Experimental results with 90- and 45-nm technologies demonstrate that the average error of the fall and rise delay estimation in single- and multi-stage gates was approximately 5% on average over a wide range of input slews, output loads, and PVT variations. The proposed model can be used in Monte Carlo STA (static timing analysis) in addition to corner-based timing analysis. It can be also used in statistical STA to calculate the sensitivities of delays to variation parameters on-the-fly even when the nominal operating condition changes as well.

Transistor network restructuring against NBTI degradation

Negative Bias Temperature Instability (NBTI) has become a critical reliability concern for nanometer PMOS transistors. A logic function can be designed by alternative transistor networks. This work evaluates the impact of the NBTI effect in the delay of CMOS gates considering both the effect of intra-cell pull-up structures and the effect of decomposing the function into multiple stages. Intra-cell pull-up PMOS transistor arrangements have been restructured to minimize the number of devices under severe NBTI degradation. Also, circuits decomposed into more than one stage have been compared to their single stage design version. Electrical simulation results reveal that the restructuring of intra-cell transistor networks recovers up to 15% of rise delay degradation due to NBTI, while the decomposition of single stage circuit topologies into multi-stage topologies tends to reduce the rise degradation delay at a cost of fall delay degradation.

Design of a short electro-optic modulator based on SiGe HBT structure

A SiGe electro-optic modulator operating at wavelength of 1.55 microm is proposed. The "ON" state voltage is set at 1.4V. The arm of the MZI waveguide required to generate a pi phase shift is 73.6 microm, and the total attenuation loss is 3.95 dB. The rise and fall delay time is 70.9 ps and 24.5 ps, respectively.

Compact Thermally Tunable Silicon Wavelength Switch: Modeling and Characterization

A wavelength-selective photonic switch is developed based on a Si microring resonator using thermooptic effect. The 10-mum-diameter microring resonator uses single-mode strip Si waveguides of dimension 0.25 mum times 0.45 mum operating at 1.5 mum. Full-width at half-maximum are in the range 0.1-0.2 nm. The ultrawide tunable range (>6.4 nm) and wide free spectral range (~18 nm) of the switch element enables wavelength reconflgurable multichannel matrix switch by wavelength multiplexing/demultiplexing. Average rise delay time of 14 mus with low switching power of 3.15 mW has been achieved with 0.2-nm wavelength tuning and 78 mus, 104 mW for 6.4-nm tuning. Fall delay times are usually less than 10 mus. Thermal simulations show 10%-20% agreement with the measurements up to 3.2-nm tuning. The compact size of the switch shows its potential as an active element in photonic integrated circuits.

Beneficiaries Can Delay Fall Into Medicare's `Donut Hole'

Back to table of contents Previous article Next article Government NewsFull AccessBeneficiaries Can Delay Fall Into Medicare's `Donut Hole'Mark MoranMark MoranSearch for more papers by this authorPublished Online:6 Oct 2006https://doi.org/10.1176/pn.41.19.0017aMedicare patients with Alzheimer's disease who use generics and mail-service pharmacies can potentially add an additional 13 days to their Medicare Part D coverage and delay entry into the Medicare Part D coverage gap, or “donut hole.”That was one finding from an analysis of the effect of generic-drug use on prescription drug costs for patients with five common conditions. The analysis was performed by the Pharmaceutical Care Management Association (PCMA).PCMA is the national association representing the nation's pharmacy benefit managers.The donut hole refers to the gap in coverage between $2,250 and $3,600 in yearly expenses for prescription drugs. Under the Medicare Modernization Act of 2003, a beneficiary may not be covered for prescription drug costs beyond $2,250 in one year; once costs reach $3,600, coverage begins again.Not all Medicare Part D prescription drug plans have a donut hole, however. The Centers for Medicare and Medicaid Services reported in August that 28 percent of individuals enrolled in Medicare Part D are in plans that have a coverage gap. Thus, the majority of Part D beneficiaries are not subject to the donut hole.For patients with Alzheimer's, the total out-of-pocket savings by using generics and mail-order services would be relatively small at $38, or only 1 percent (see table). Part of the reason for the relatively small savings in this category is that there are very few generic alternatives, according to PCMABut PCMA found that overall, increased use of generic drugs and mail-service pharmacies by Medicare beneficiaries has the potential to delay entry into the Medicare Part D coverage gap by an average of 74 days.“Regrettably, too many beneficiaries are not taking full advantage of the cost-saving tools within their Medicare drug plans,” said PCMA President Mark Merritt in a statement accompanying release of the analysis.“ All stakeholders need to work together to make beneficiaries better aware of how to maximize their Medicare prescription drug coverage, including increased use of generics and mail-service pharmacies.”In the analysis, PCMA assembled five patient profiles using both brand-name and generic drugs to treat five primary conditions and assorted related conditions. The conditions were high-blood pressure, diabetes, heart disease, chronic obstructive pulmonary disease, and Alzheimer's disease.PCMA examined four national Medicare prescription drug plans that provide coverage to more than 50 percent of Medicare's prescription drug plan beneficiaries.On average, beneficiaries can save in total about 38 percent—or more than $1,200 in 2006—in out-of-pocket costs through the increased use of generic drugs and mail-service pharmacies.Additional days of coverage and costs saved for the other four conditions, according to analysis, are as follows:High-blood pressure. Sixty-one additional days of Part D drug coverage, with total out-of-pocket savings of $1,226, or about 36 percent.Diabetes and other related conditions. An additional 157 days of Part D drug coverage, with total out-of-pocket savings of $2,081, or about 57 percent.Heart disease and other related conditions. An additional 76 days of Part D drug coverage, with total out-of-pocket savings of $1,221, or about 57 percent. For this profile, patients would avoid entering the donut hole altogether, according PCMA.Chronic obstructive pulmonary disease and other related conditions. An additional 65 days of Part D drug coverage, with total out-of-pocket savings of $1,504, or about 42 percent.A report of the PCMA analysis and methodology is posted at<www.pcmanet.org/newsroom/index.htm>.▪ ISSUES NewArchived

SIZING CMOS INVERTERS WITH MILLER EFFECT AND THRESHOLD VOLTAGE VARIATIONS

The maximum speed of synchronous circuits is generally constrained by the worst case propagation delay, which limits the system clock frequency. Various techniques exist to manage the circuit delay, trading off speed for other system resources. One such approach is to equalize the rise and fall delay times. The primary design parameter for equalizing these delay times is the ratio between the width of the PMOS and NMOS transistors, which determines the relationship between the currents passed along the pull-up and pull-down paths. The variation of the pull-up to pull-down ratio for different circuit parameters is discussed in this paper under the constraint of equal rise and fall delay times. It is shown that the short-circuit current and the Miller capacitance affect the ideal linear relationship between the CMOS inverter delay times and the load capacitance, requiring the pull-up to pull-down ratio to be adjusted as circuit parameters are varied. These effects are more pronounced in deep submicrometer technologies with significant parasitic MOSFET capacitances and threshold voltage variations. Based on analytic and experimental observations, circuit design guidelines are proposed to minimize the Miller effect.

Design of an Inter‐plane Circuit for Clocked PLAs

Since the Programmable Logic Arrays (PLAs) can implement almost any Boolean function, they have become popular devices in realization of both combinational and sequential circuits. We present a power‐saving fast half swing CMOS circuit implementation for NOR–NOR PLA implementation. An additional 1/2 VDD voltage source and buffering transmission gates are inserted between the NOR planes to erase the racing problem and shorten the rise delay as well as the fall delay of the output response such that the speed is enhanced and the dynamic power is reduced. Detailed simulation results reveal appropriate L/W guidelines. The analysis of effects of the 1/2 VDD on power and speed is also provided in this work.

An accurate and efficient delay time modeling for MOS logic circuits using polynomial approximation

A delay model for multiple delay simulation for NMOS and CMOS logic circuits is proposed. For the simple inverter the rise or fall delay time is approximated by a product of polynomials of the input waveform slope, the output loading capacitance, and the device configuration ratio, with the polynomial coefficients determined so as to best fit the SPICE simulation results for a given fabrication process. This approach can easily be extended to the case of multiple-input transitions. The simulation results show that the proposed modes can predict the delay times within 5% error and with a speedup of three orders of magnitude for several circuits tested as compared with the SPICE simulation.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Digital Waveform Generator and Potentistat Controller for Pulse Electrochemical Techniques

ABSTRACT An instrument which uses two computers operating in parallel for waveform generation, data acquisition, and general control of an electrochemical potentiostat is described. It is presently programmed to perform eight different pulse methods, but other methods can be tried and then included in the program, if desired. Liquid or solid electrodes, either dropping or stationary, may be used. Step times down to 31 μs (sweep rates in excess of 100 V/s) are available with total timing errors of less than 20 ns. Exact control of step time, time between step application and current integration, length of integration, and delay between drop fall and experiment beginning is provided. Different values of the above parameters, except for drop fall delay, may be selected for the anodic and cathodic steps in differential methods, allowing unsymmetrical operation. Circuits to provide drop profile data in tast polarography and to record drop times for surface tension measurements are included.

Observation of Nanosecond Carrier Pulses

The present paper describes theory and experiments on the observation of nanosecond carrier pulses in the microwave region. The advancement of microwave nanosecond techniques requires measurement of waveforms which is more accurate than conventional methods. The measuring method described here was developed to satisfy this requirement. The new method, using a synchronous or heterodyne detector, gives accurate and complete information on nanosecond pulse waveforms in the microwave region. Applying this method, we constructed an experimental system to generate and observe the nanosecond pulses in the 11-Gc region. The over-all rise and fall time and delay resolution of this system are as small as 0.5 nsec. Pulse modulators, detectors and filters were measured or adjusted with this experimental system. The experimental results are described in this paper. The pulse generation and observation system developed here is expected to be useful for measuring and adjusting microwave nanosecond pulse devices with accuracy.