Failure Analysis Of Solder Joints Research Articles

Design guideline on board-level thermomechanical reliability of 2.5D package

A vast range of electronics products have utilized 2.5D packages for better performance and miniaturization. As multi-level assembly technologies are getting mature, 2.5D packaging technology becomes affordable. In this work, design guideline for board-level reliability of a 2.5D package was provided with respect to accelerated thermal cycling (ATC) and power cycling (PC). Finite element models were built and validated step-by-step by warpage measurement. Solder fatigue life in power cycling was investigated with temperature mapping technique merged into the process of scripting, which conducts load transfers from computational fluid dynamics (CFD) simulation to finite element analysis (FEA). ATC test was conducted with solder joint failure analysis. Fatigue life projection model was determined by correlation between tested life data and simulation results. Parametric studies regarding geometry factors and material properties were performed including PCB, substrate, thermal interface material (TIM) and lid adhesive, to give design suggestions to improve board-level thermal reliability. It is found that CTE mismatch between the substrate and the PCB is the major factor affecting board-level reliability in accelerated thermal cycling. Maximum junction temperature of a 2.5D FPGA package is dependent on application scenarios and working environment. Designed maximum junction temperature and applied heatsink clamping force have considerable influences on board-level reliability.

In-situ service load monitoring of automotive electronic systems using silicon-based piezoresistive stress sensor

It is expected that more and more complex (integrated) automotive electronics will be adopted in systems. These advanced electronics are critical for passenger safety. Documenting the in-situ loading is, thus, very important for accurate reliability prognostics. In this study, we propose a piezoresistive stress sensor to detect the in-situ loading of an automotive electronic control unit (ECU). A load metric directly related to the in-situ loading is defined by considering the in-situ stress values of twelve measurement cells in each sensor. The sensor and the proposed load metric are implemented to document the in-situ loading that results from the local coefficient of thermal expansion mismatch between the electrical components and printed circuit board (PCB) in advanced ECUs. The validity of the proposed metric is corroborated by failure analysis of solder joints of multilayer ceramic capacitors (MLCCs).

Reliability and failure analysis of solder joints in flip chip LEDs via thermal impedance characterisation

Flip chip technology has made significant improvements to LED chip on board (COB) packages and modules by reducing thermal resistance compared with traditional wire bonded LEDs. However, one of the critical issues of flip chip packaged LEDs is the reliability of their solder interconnects, which are responsible for the heat transfer to the substrate. Based on a supply switching test, also called power cycle test, a model for monitoring and reliability was done to describe the remaining lifetime and additional the solder fatigue. Therefore, changes in thermal resistance of the LED-module were measured and correlated with solder fatigue of the LED flip chip package. Thermal impedance measurements were performed to monitor the status of the LED-module. Detailed analyses, comparing with the initial state, allow the evaluation of the occurring temperature swing of each LED chip. Single chip analysis combined with a thermal resistance driven monitoring model allows the calculation of remaining lifetime at each time during testing and beyond the first chip failure in a multi chip LED-module. Accordingly, it could be shown that the thermal impedance is a powerful tool for reliability monitoring and failure analysis.

Investigation and prediction of solder joint failure analysis for ball grid array package subject to mechanical bending environment

PurposeThe purpose of this study was to investigate the changes in solder joint stress when subjected to mechanical bending. The analytical theory pertaining to the stresses in the solder joint between the components (including the molding compound, the chip and the substrate) was described, and the printed circuit board (PCB) with a discontinuity function when the PCB assembly is subjected to mechanical bending was developed. Thus, the findings reported here may lead to a better understanding of the solder joint failure based on the Physics of Failure model.Design/methodology/approachThis paper discusses the analytical model for calculating the stress in solder joints, as well as presents a simulation model that can be used for calculating the strain energy density of solder joint. First, the multilayer plate theory is used in discussing the composite material for the component, including the molding compound, the silicon chip and the substrate, or the PCB, including the copper layers, the fiber and the epoxy. Finally, the complete structure of the analytical model developed as a part of this current work is presented.FindingsFor the analytical model of multilayer structures in which the interconnection layer is discrete, mechanical bending has been modeled with respect to varying silicon chip length. The analytical model that describes the stress of the outermost solder joint experiences is chosen, as this is the typical solder joint failure. The analytical model can be applied to discrete solder joints, which are evaluated by calculating the matrix form. Owing to its use of the matrix equation, the analytical model can be highly combinatorial and thus more capable of calculating the solution.Research limitations/implicationsThe analytical solution based on a simple concept was presented and validated using the finite element model for the stress experienced by solder joints subjected to mechanical bending. To verify that the simulation represents a real PCB case, the authors use the finite element method (FEM) to compare their case with the multilayer plate theory. Owing to the good agreement between the theory and simulation results, the authors conclude that the multilayer plate theory can be correctly applied in multilayer PCB and be used in an analytical model for the PCB assembly subjected to mechanical bending.Practical implicationsOwing to the good agreement between the theory and simulation results, the authors conclude that the multilayer plate theory can be correctly applied in multilayer PCB and be used in an analytical model for the PCB assembly subjected to mechanical bending.Social implicationsThe analytical model is validated with the FEM model and provides the way to physically examine the solder joint failure mechanism. In this paper, the analytical model is developed as a means to assess the solder joint stress subjected to mechanical bending.Originality/valueThe analytical model treats the solder joint as discrete and has been successfully validated against the finite element model. The complete structure model (the second analytical model) is presented to discuss the effects of varying silicon chip length on the normal stress in solder joints. When the silicon chip length exceeds to 80 per cent of the total package length, the stress of the outermost solder joint increases rapidly. The design analysis findings have suggested that the failure of the outermost solder joint subjected to mechanical bending on the PCB assembly can be reduced by analyzing the analytical model.

Failure analysis techniques for lead‐free solder joints

PurposeThis paper aims to describe and document the application of commonly utilized solder joint failure analysis techniques to lead‐free solder joints.Design/methodology/approachTraditional failure analysis techniques, including visual inspection, X‐ray radiography, mechanical strength testing, dye and pry, metallography, microscopy and photomicrography, are reviewed. These techniques are demonstrated as applied to lead‐free and tin lead solder joints. Common failure modes observed in lead‐free and tin lead solder joints are described and compared.FindingsIt is shown that the traditional failure analysis techniques previously utilized for tin lead solder joints are widely applicable to the analysis of lead‐free solder joints. The changes required to effectively apply these techniques to the analysis of lead‐free solder joints are described.Originality/valueThis paper will be instrumental to the process, quality, reliability and failure analysis engineering disciplines in furthering understanding of the application of failure analysis techniques of both tin lead and lead‐free solder joints.

Failure analysis of solder joints with a damage‐coupled viscoplastic model

AbstractThis paper presents failure analysis of solder joints with a damage‐coupled viscoplastic model. A material model is developed to characterize the elasticity, plasticity, creep and damage of solder. A semi‐implicit time‐integration approach is adopted for the numerical implementation of the solder model. This solder model has been implemented into finite element codes developed at Sandia National Laboratories and into the commercial, finite element code ABAQUSTM with its user‐defined material subroutine UMAT. Finite element analyses are performed on solder joints with the new solder constitutive model and mesh dependency of these analyses is investigated. Copyright © 2003 John Wiley & Sons, Ltd.

Metallographic Examination of Soldered Joints

Metallographic sections are an indispensable tool in the assessment and failure analysis of solder joints, as surface appearance is an unreliable guide to their internal state. This paper outlines methods for the preparation of sections through solder joints, and gives some guidelines for their interpretation. Finally, some typical features and defects are discussed.