Fabrication Of High Electron Mobility Transistors Research Articles

Reduction of interface defects in gate-recessed GaN HEMTs by neutral beam etching

This study investigates and compares the impact of different etching techniques on the fabrication of GaN high electron mobility transistors (HEMTs) between the inductively coupled plasma reactive ion etching (ICP-RIE) and the neutral beam etching (NBE) for the gate recess. By conducting direct current analysis, it was found that devices manufactured using the NBE exhibited superior electrical performance as compared with those produced using the ICP-RIE. These enhanced electrical characteristics include a transconductance of up to 100.4 mS/mm, a threshold voltage (Vth) of −2.3 V, an on/off current ratio of 1.1 × 109, a subthreshold swing (S.S.) of 99.63 mV/dec, and a remarkably low gate leakage current. Additionally, we noted varying degrees of hysteresis in the I–V characteristics were related to process disparities possibly leading to interface defects. Multi-frequency capacitance-voltage (C–V) measurements were used to identify the interface defects at the oxide/AlGaN interface of the gate. The results revealed that devices fabricated using the NBE exhibited a lower interface defect density as compared with those fabricated using the ICP-RIE, thereby elucidating the reduced hysteresis observed in the I–V characteristics. These findings indicated the significant advantages of the NBE process in the fabrication of GaN HEMTs.

Fabrication of AlGaN/GaN heterostructures on halide vapor phase epitaxy AlN/SiC templates for high electron mobility transistor application

GaN films were grown on hydride vapor phase epitaxy (HVPE) AlN/SiC templates by metalorganic CVD (MOCVD) without annealing the reactor to eliminate the memory effect. A step-terrace structure and smooth surface were obtained for the GaN film, which had a thickness of ∼200 nm. Subsequently, AlGaN/GaN heterostructures for application in high electron mobility transistors (HEMTs) with thin GaN channels were fabricated without a C- or Fe-doped GaN buffer layer. The interface quality at the AlGaN/GaN heterostructure was good enough for a two-dimensional electron gas to exhibit Shubnikov–de Haas oscillation in a magnetic field at 1.8 K. The GaN HEMTs with a thin channel on the AlN/SiC templates exhibited both a pinch-off character and conventional properties. In view of both the shorter epitaxial growth time and higher thermal conduction, HVPE AlN/SiC templates are applicable to the fabrication of GaN HEMTs by MOCVD.

Electronic properties and passivation mechanism of AlGaN/GaN heterojunction with vacancies: a DFT study

A significant issue for GaN-based high-electron-mobility transistors (HEMTs) in high power devices is the material defect, particularly the defect states generated by the defects, which has a negative impact on the device carrier concentration and carrier transport. Based on density functional theory (DFT), we investigate the microscopic properties of different type point vacancies in the AlGaN/GaN heterojunction. It is found that N vacancy introduces defect states near the conduction band minimum (CBM) of the GaN layer and AlGaN/GaN interface. Ga and Al vacancies introduce defect states near the valence band maximum (VBM) in bulk and interface of AlGaN/GaN heterojunction. Moreover, Al vacancy is more likely to be an effective candidate for acceptor defect than Ga vacancy. We further study several AlGaN/GaN interface passivation schemes by introducing F, V group element P, and III group element B at the AlGaN/GaN heterojunction interface to analyze the passivation mechanism. According to the results of the passivation models, B passivation of Ga and Al vacancies is an effective method to completely remove the defect states from Ga and Al vacancy defects. Combining the III and V groups elements into the passivated process may be effective in achieving high-quality AlGaN/GaN heterojunction interface for the future GaN-based HEMTs fabrication.

Over 10W/mm High Power Density AlGaN/GaN HEMTs With Small Gate Length by the Stepper Lithography for Ka-Band Applications

This study reports AlGaN/GaN high-electron-mobility transistors (HEMTs) fabricated by the Stepper Lithography on a 4-inch wafer for Ka-Band applications. Small gate length (LG) of 100 nm was achieved through a 2-Step Photolithography Process and the gate region of the AlGaN/GaN HEMT was defined by using two lithography steps to form gamma-shaped gates. The 4-inch AlGaN/GaN HEMT wafer demonstrated high electrical performance uniformity with respect to the maximum drain-source current density (IDSS), the peak extrinsic output transconductance (Gm), and the threshold voltage (Vth). At <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${\mathrm{ V}}_{\mathrm{ DS}}\,\,=$ </tex-math></inline-formula> 20 V, the AlGaN/GaN HEMT exhibits an <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${\mathrm{ I}}_{\mathrm{ DSS}}$ </tex-math></inline-formula> of 1004.2 mA/mm, a Gm value of 363.6 mS/mm, a maximum output power density (POUT(MAX)) of over 10 W/mm, and a power gain of 8.8 dB with a maximum 51.1% Power-added efficiency (PAE) at 28 GHz in Continuous Wave (CW) mode. The results show the potential of AlGaN/GaN HEMT fabrication with high yield and outstanding RF performance using Stepper Lithography for 5G applications.

Challenges and Opportunities for High-Power and High-Frequency AlGaN/GaN High-Electron-Mobility Transistor (HEMT) Applications: A Review.

The emergence of gallium nitride high-electron-mobility transistor (GaN HEMT) devices has the potential to deliver high power and high frequency with performances surpassing mainstream silicon and other advanced semiconductor field-effect transistor (FET) technologies. Nevertheless, HEMT devices suffer from certain parasitic and reliability concerns that limit their performance. This paper aims to review the latest experimental evidence regarding HEMT technologies on the parasitic issues that affect aluminum gallium nitride (AlGaN)/GaN HEMTs. The first part of this review provides a brief introduction to AlGaN/GaN HEMT technologies, and the second part outlines the challenges often faced during HEMT fabrication, such as normally-on operation, self-heating effects, current collapse, peak electric field distribution, gate leakages, and high ohmic contact resistance. Finally, a number of effective approaches to enhancing the device's performance are addressed.

Single step electron-beam lithography archiving lift-off for T-gate in high electron mobility transistor fabrication

In this paper, a new method of electron-beam lithography was proposed to directly obtain a floating T-shaped gate. In the method, only one step of exposure and one step of development were operated on a three-layer photoresist of PMMA/P(MMA-MAA)/ P(MMA-MAA) to form an obvious undercut structure which is very benefit for subsequent lift-off process of gate metal. A high electron mobility transistor (HEMT) with an 80 nm floating T-shaped gate was fabricated on a SiC substrate which has a 10 nm InAlN barrier. Finally, the obtained device by above process has a fT/fmax of 90/200 GHz.

Fabrication and Performance of Ti/Al/Ni/TiN Au-Free Ohmic Contacts for Undoped AlGaN/GaN HEMT

We proposed a preparation method of a TiN capping layer compatible with the ohmic contacts process, and demonstrated the Au-free ohmic contacts of an undoped AlGaN/GaN high-electron-mobility transistor (HEMT) with a Ti/Al/Ni/TiN metal structure. TiN was prepared through depositing Ti thin film by a sputtering system and then annealing in N2 ambient by the rapid thermal annealing process. The thickness of Ti/Al, annealing temperature, and annealing time were investigated systematically. Using the Ti/Al/Ni/TiN structure, a low contact resistance ( $3.47 \times 10^{-5}\,\,\Omega $ cm2, $1.1~\Omega \cdot mm$ ) was obtained when annealed at 900 °C for 30 s in N2 ambient, which was comparable with conventional Au-based ohmic contacts ( $3.12 \times 10^{-5} \Omega \cdot cm^{2}$ , $1.05~\Omega \cdot mm$ ). In addition, the Ti/Al/Ni/TiN ohmic contacts showed smooth surface morphology with a surface roughness of 5.89 nm. AlGaN/GaN HEMT, based on Ti/Al/Ni/TiN Au-free ohmic contacts, was also fabricated and exhibited good dc characteristics. The reported Au-free AlGaN/GaN HEMT fabrication process can be used in standard Si fabs without the risk of contamination.

Impacts on access resistance of InP high electron mobility transistors from wafer processing

In this work, the authors evaluated the access resistance of InP high electron mobility transistors (HEMTs) and their degradation during wafer processing. The transfer resistance, which was rarely separated from other components of the total access resistance of InP HEMTs in the literature, was found to be the dominant component of the access resistance. It was also found that the transfer resistance degraded during wafer processing. The selection of the ohmic metal stack and its impact on both the metal-cap contact resistance and the transfer resistance was also investigated. The observations in their experiments and relevant discussions in the report are expected to be useful in the identification of improvement opportunities in both material growth and wafer fabrication of InP HEMTs.

Effects of Electrochemical Etching on InP HEMT Fabrication

Optimum device performance in terms of noise and gain of AlInAs/GaInAs/InP High Electron Mobility Transistors (HEMTs) requires minimizing the contact resistance ${R} _{C}$ . In several HEMT fabrication steps in device manufacturing it is common to expose highly doped semiconductors layers to heated solvents for prolonged periods of time. It is shown here that even a small amount of water or water vapor present during photoresist removals, metal lift-offs or related processes can dramatically affect the final device performance by promoting electrochemical etching of the semiconductor layers adjacent to metal stacks. In this paper, the impact of metal lift-off on erosion of HEMT epitaxial layers and Ohmic contact resistance is studied with respect to different layer doping levels, compositions and metal stacks forming the Ohmic contacts.

(Invited) Coupled Experimental and Numerical Investigation of High-Voltage GaN Hemts

The wide band gap compound semiconductor Gallium Nitride and its ternary alloys have found commercial acceptance in the fabrication of high electron-mobility transistor (HEMT) rf devices. In addition, high power applications have been very attractive due to their high breakdown voltage and thus high output power. Higher power limit improvements can be reached by several means, including the integration of field-plates above the conduction channel, which tend to improve the uniformity of the electric-field distribution and reduce its peaks. These field-plates can be connected to the source or to the gate. The reduction of electrical and thermal “hotspots,” where severe degradation is thought to initiate, increases the allowable power levels for HEMT devices by as many as five folds. In this study, GaN HEMT devices with source-connected field-plates are characterized thermally to quantify their performance. Deep submicron resolution thermoreflectance (TR) temperature imaging is used to measure the temperature profile of the exposed surface features of the device, which are mainly the source and drain metal contacts as well as the GaN channel region. The TR thermography method is based on detecting changes in surface reflectivity (ΔR) that result from changes in local surface temperature (ΔT). The relationship between the changes in reflectivity and temperature is linear to first-order effects, and is typically referred to as the coefficient of thermoreflectance (CTR). As expected, this coefficient depends on the material and the wavelength of light, but also on any transparent layers (e.g., passivation) in the optical path between the first reflective surface and the sensor where the light is collected. Therefore, the success of a TR measurement requires that the surface of interest exhibit both a high reflective index and be thermally-reflective, i.e., have a good value of CTR. By using a near ultra-violet source to illuminate the device under test (DUT), the GaN is rendered opaque, thus ensuring that the obtained temperature fields are those of the GaN surface and not an integrated average over multiple semi-transparent layers. However, the presence of the field-plate obstructs imaging access to the gate where the peak temperatures are expected. Therefore, this investigation couples the measurements to 3D computations in order to produce temperature fields that would otherwise be inaccessible to direct measurement. Both quasi-steady-state and transient temperature fields of the GaN HEMTs are obtained at different activation power levels and an experimental assessment is made with regard to the electrical activation limits and the thermal self-heating. In addition to the measurements, thermal computations are performed using a self-adaptive, multi-scale, numerical simulation engine. The 3D transient thermal model is then driven by the experimentally-obtained temperature maps to provide a more detailed and device-specific interpretation of the coupled electro-thermal effect of the field-plates on reducing the temperature and increasing the break-down voltage. Moreover, the full 3D thermal model also helps provide physically-accurate temperature fields of regions of critical channel regions, where the heat sources are located, and where localized hotspots that are hidden underneath field-plates are inaccessible to optical measurement approaches. The attached figure contains two temperature fields, numerical on the left and experimental on the right. These results are representative of the type of useful data that can be obtained from the computational and measurement techniques. The presentation will additionally include the results of the coupling of the two approaches and the insights that can be gained, especially for those features that are optically inaccessible. Figure 1

Evaluation of an InAs HEMT with source-connected field plate for high-speed and low-power logic applications

In this study, we have presented a source-connected field plate (SCFP) InAs high electron mobility transistor (HEMT) and evaluated its potential for using in high-speed and low-power logic applications. The fabricated device demonstrated good electrical characteristics including low subthreshold swing (SS) of 76 mV/decade, drain induced barrier lowering (DIBL) of 44 mV/V, ION/IOFF ratio of 2.4 × 104, an off-state gate leakage current of less than 5 × 10−6 A/mm and a Gm,max of 1100 mS/mm at VDS = 0.5 V. When increasing the drain-source bias (VDS) to 1.0 V, the Gm,max increased to 1750 mS/mm with a cut-off frequency of 113 GHz. These results revealed that the fabrication of source-connected field plate InAs HEMTs achieved excellent device performance for high-speed and low-power logic applications.

(Invited) GaN Buried Channel Normally Off MOSHEMT: Design Optimization and Experimental Integration on Silicon Substrate

AlGaN/GaN High Electron Mobility Transistors (HEMTs) find application in power electronics systems as high-frequency power switches. Low on-state resistance and high breakdown voltage in the off-state are the key features of AlGaN/GaN HEMTs. Achieving these qualities with a normally-off operation is a challenge. Gate recess etching is the most widely used technique to realize a normally off AlGaN/GaN HEMT. On-state current of gate recess etched devices are limited by Scattering of electrons at the oxide-GaN interface. Free carriers in the buffer layers and nonuniform electric field distribution between gate and drain electrode limits the breakdown voltage of these devices. We address these issues by implementing a buried channel device architecture in normally-off AlGaN/GaN MOS-HEMTs. Buried channel architecture has been reported in Si, SiC and InGaAs devices. With this architecture, the on-state characteristics improve significantly since the conduction channel is formed away from the oxide-semiconductor interface, thus avoiding interface scattering. The off-state characteristics improve due to the presence of depletion region associated with a p-n junction in GaN buffer. The p-n junction in the buffer also helps to achieve uniform electric field distribution between gate and drain. The schematic stack of the proposed buried channel normally-off AlGaN/GaN MOS HEMT is shown in fig. 1(a). Atlas silvaco simulator has been used to perform electrostatic simulation on the proposed buried channel device architechure. The thickness and doping concentrations of p-type and n-type regions in the GaN buffer are the important design parameters to be optimized. Fig. 1(b) and fig 1(c) show the electron concentration colour plot of the optimized device stack at VG = 0 V and at VG > VT respectively. The carriers bellow the gate electrode are depleted at VG = 0 V as shown in fig. 1(b) and the depletion region associated with p-n junction in the GaN buffer ensures low leakage current at off state. When VG > VT, a buried channel is formed below gate electrode as shown in the fig. 1(c), ensuring a buried conduction in the proposed device architecture. The device stack growth was carried out in a horizontal flow AIXTRON MOCVD reactor on a 2' silicon substrate. Standard HEMT fabrication procedure with Ti/Al/Ni/Au as source/drain contact and recessed Ni/Au gate contact with ALD Al2O3 dielectric was followed for the realization of the device. Performance of a buried channel device is compared with a reference device here. As shown in Fig. 2, VT of the device fabricated on buried channel stack and reference stack were 1.3 V and 1.7 V respectively, determined by extrapolating the linear region method. The lower VT of buried channel device compared to reference device is due to the presence of intentionally n-doped (1.5x1017 cm-3) region below UID GaN (1014 cm-3). This can be increased appropriately by increasing the p-type GaN doping, or reducing n-type doping. The field effect mobility of the buried channel device is 142 cm2/Vs compared to 25 cm2/Vs in case of reference device. More than five times increase in the field effect mobility is because of lesser interface scattering effect on electron transport in buried channel device. The off-state drain leakage current in devices on buried channel stack is four orders of magnitude lower than that on reference stack (4 nA/mm for buried channel device compared to 76 uA/mm for reference). The buried channel device has a breakdown voltage of 158V compared to 98V for reference device. The matching of calibrated device simulation and experimental results validate the advantages of buried channel architecture. Figure 1

Evaluation of a 100-nm Gate Length E-Mode InAs High Electron Mobility Transistor With Ti/Pt/Au Ohmic Contacts and Mesa Sidewall Channel Etch for High-Speed and Low-Power Logic Applications

In this paper, a 100-nm gate length InAs high electron mobility transistor (HEMT) with non-alloyed Ti/Pt/Au ohmic contacts and mesa sidewall channel etch was investigated for high-speed and low-power logic applications. The device exhibited a low subthreshold swing (SS) of 63.3 mV/decade, a drain induced barrier lowering value of 23.3 mV/V, an ION/IOFF ratio of 1.34 $\times$ 104, a Gm,max/SS ratio of 27.6, a current gain cut-off frequency of 439 GHz with a gate delay time of 0.36 ps, and an off-state gate leakage current of less than 1.6 $\times 10^{-5}$ A/mm at VDS = 0.5 V. These results demonstrated that the presence of non-annealed ohmic contacts with mesa sidewall etch process allowed the fabrication of InAs HEMTs with excellent electrical characteristics for high-speed and low-power logic applications.

The effects of tetramethylammonium hydroxide treatment on the performance of recessed-gate AlGaN/GaN high electron mobility transistors

AlGaN/GaN high electron mobility transistors (HEMTs) are fabricated using a gate recess process and a surface treatment with tetramethylammonium hydroxide (TMAH) prior to gate metal deposition. Electrical characterizations show improved extrinsic transconductance and saturation current, as well as more uniform off-state behavior with reduced off-current by a factor of 3.5 and gate leakage current by a factor of 4.2 in the devices with TMAH treatment. The analyses based on atomic force microscopy, transmission electron microscopy, and X-ray photoelectron spectroscopy show that the TMAH treatment effectively reduces the roughness of the recess-etched AlGaN surface and removes the native oxide layer on the AlGaN surface, suggesting a simple and viable route towards the fabrication of gate-recessed HEMTs based on AlGaN/GaN heterostructure with improved controllability and uniformity.

Scanning capacitance microscopy characterization of AIIIBV epitaxial layers

Abstract The applicability of scanning capacitance microscopy (SCM) technique for chosen electrical properties characterization of AIIIBV structures fabricated by Metalorganic Vapor Phase Epitaxy (MOVPE) was examined. The calibration curves for quantitative characterization of doping levels in GaAs layers were created. The AlGaN/GaN/Si heterostructures for high electron mobility transistor fabrication and InGaAs tunnel junction for tandem solar cell characterization were presented. The crucial factors of measurement conditions which could influence the obtained results were also discussed.

Effect of device geometry on static and dynamic performance of AlGaN/GaN-on-Si high electron mobility transistor

This paper discusses the effects of several geometric parameters in DC and RF performances of AlGaN/GaN high electron mobility transistors (HEMTs) grown on high-resistivity silicon substrates. Those parameters include the dependency of gate length (Lg), gate cap length (Lcap) and gate-to-source distance (Lgs). It is shown that decreasing Lg and Lgs can both improve maximum drain current and transconductance behaviors. The fabricated 50 μm wide GaN-HEMT exhibits the maximum drain current of 1 A mm−1 at Vg = 2 V and maximum extrinsic transconductance Gmmax of 240 mS mm−1. Besides, decreasing Lg and Lcap also provides the improvement on current gain frequency (fT) and maximum oscillation cut off frequency (fMAX). The fT of 40 GHz and fMAX of 55 GHz at Vds = 5 V are demonstrated by GaN-HEMT device featuring Lg of 200 nm, Lcap of 300 nm and Lgs of 1.2 μm, which can realize the compact solid-state power amplifier used in S and C band. However, gate-to-source distance has little effect on RF performance of AlGaN/GaN HEMTs. Those results compared in our study are not only very essential for accurate GaN-based HEMT device modeling and fabrication, but are also vital to better understanding of their device physics.

T‐Gate Fabrication of InP‐Based HEMTs Using PMGI/ZEP520A/PMGI/ZEP520A Stacked Resist

PMGI/ZEP520A/PMGI/ZEP520A fourlayer resist stack is firstly proposed for T-gates fabrication of InP-based High electron mobility transistors (HEMTs). Gate-head and gate-foot are exposed in single-step Electron beam lithography (EBL), which avoids alignment deviation by automatic self-alignment. The newly introduced PMGI at the bottom greatly improves the adhesiveness of ZEP520A resist with the substrate. The optimal gate-foot length reaches 101nm for a design of 50nm gate footprint pattern, and which can be improved to be 66.8nm for 30nm gate footprint pattern. Finally, Tgates in nanometer regime have been successfully incorporated into InP-based HEMTs fabrication. Benefiting from both the narrow gate-foot and the reduced parasitic gatecapacitance by single-step EBL technique with the fourlayer resist stack, the fabricated devices with gate-foot length of 101nm demonstrate excellent DC and RF performances: the maximum extrinsic transconductance, the current-gain cutoff frequency and maximum oscillation frequency are 1051mS/mm, 249GHz and 415GHz, respectively.

Comparison of Single‐Step and Two‐Step EBL T‐Gates Fabrication Techniques for InP‐Based HEMT

T-Gate fabrication processes for InP-based High electron mobility transistors (HEMTs) are described using PMMA/Al/UVIII. The single-step and two-step Electron beam lithography (EBL) methods are proposed contrastively without dielectric support layer. The opti- mal gate-foot length is 196nm for 50nm geometry path by single-step EBL technique. Since the gate-foot and gate-head are defined independently, the two-step EBL process minimizes forward scattering and enables smaller gate-foot length, which improves to be 141nm for 50nm geometry path and also 88nm for 30nm geometry path. Both EBL methods have been incorporated into InP- based HEMTs fabrication. With the gate-foot length de- creases from 196nm to 141nm, the current-gain cutoff fre- quency (fT) is improved from 125GHz to 164GHz, and also the maximum oscillation frequency (fmax )i ncreases from 305GHz to 375GHz.

Study of the Effects of GaN Buffer Layer Quality on the dc Characteristics of AlGaN/GaN High Electron Mobility Transistors

AlGaN/GaN high electron mobility transistors (HEMTs) are promising candidates for high power and high current applications with its high mobility and high breakdown field. Epitaxial films for device substrate are typically grown on sapphire or silicon carbide, SiC, with dislocation densities in the order of 108 - 1010cm-2 due to their thermal coefficient and lattice mismatches. The thinner GaN buffer layers on SiC have been reported to have higher threading dislocation density in the GaN, but lead to higher off-state breakdown voltages. However, thick GaN buffer layers on sapphire and their impact on dc performance have not been widely studied. In this study, the impact of GaN buffer layer quality on dc and gate-lag pulse performance of AlGaN/GaN HEMTs was studied. Transmission electron microscopy (TEM) was used to measure the dislocation density in the GaN buffer layer of the HEMT samples. Dc characteristics, including drain I-Vs, transfer characteristics, and gate pulsed drain I-V characteristics of the HEMTs, were measured to establish a correlation between the AlGaN/GaN HEMTs’ dc and gate-pulsed performance and GaN buffer layer quality. AlGaN/GaN HEMT structures grown by metal organic chemical vapor deposition (MOCVD) on sapphire substrates were acquired from two different vendors. Both types of wafers had 24% Al concentration in the AlGaN barrier layer. One type of wafer had a 5 µm GaN buffer and the other had a 2 µm GaN buffer layer. HEMT fabrication was started with mesa patterning by conventional optical lithography. The mesa-etching was achieved using a unaxis shuttle-lock reactive ion etcher with inductively coupled plasma module (ICP) for device isolation with a Cl2/Ar plasma. Ohmic metallization of electron-beam evaporated Ti/Al/Ni/Au (25 nm/125 nm/45 nm/100 nm) was patterned by lift-off and subsequently rapid thermally annealed at 850⁰C in a flowing N2 ambient for 45 seconds. Schottky gates of e-beam evaporated Ni/Au (20 nm/80 nm) with 100 μm width and 1 μm length were obtained by standard lift-off patterning. DC current–voltage (I-V) characteristics were measured using an HP4156 parameter analyzer, and gate-lag pulse measurements were measured using an Agilent 8114A pulse generator. Figure 1 shows the bright field cross-sectional transmission electron microscopy (BF-XTEM) pictures of AlGaN/GaN surface for the top layers of (a) HEMT structure with 2 µm GaN buffer layer, (b) HEMT structure with 5 μm GaN buffer layer as well as the GaN/sapphire interface for the (c) HEMT structure with 2 μm GaN buffer layer, and (d) HEMT structure with 5 μm GaN buffer layer. Dislocations are seen to originate near the GaN/sapphire interface and propagate up through the AlGaN/GaN interface to the surface of both HEMT wafers. However, it is clear that the HEMT structure with 2 μm GaN buffer layer exhibited a much higher defect density. The calculated defect density for 2 μm GaN buffer layer substrate had an order of magnitude higher defect density. However, 5μm GaN buffer layer wafer showed that it was under high strain with larger height difference across the 2 inch with lower radius of curvature. There was no major difference in HEMTs’ dc performance was observed. In the other hand, Figure 2 (a) and (b) shows that gate lag measurement on fabricated HEMTs on 5 μm GaN buffer layer wafer showed no degradation and on 2 μm GaN buffer layer wafer showed the otherwise. The effects of defect density on HEMT dc and radio frequency performance were studied. HEMTs were fabricated on 2 and 5 μm of GaN buffer layers with the same composition of active layers. Despite there was no significant difference was seen in dc characteristics, significant reduction in pulse measurements was observed on thinner GaN layer HEMTs. These results suggest that the defects created in GaN buffer layer do not largely influence device dc performance but are closely related to high frequency performance. Figure 1

Effect of Buffer Oxide Etchant (BOE) on Ti/Al/Ni/Au Ohmic Contacts for AlGaN/GaN Based HEMT

AlGaN/GaN high electron mobility transistors (HEMTs) have gained more attention recently because of the superior mobility (~1400 cm2/V-s) and high breakdown voltage. The quality of Ohmic contacts are key characteristics to guarantee the high mobility. During fabrication, Ohmic metals would be exposed to chemicals such as Buffer Oxide Etchant (BOE). BOE is a mixture of HF and NH4F, which is known to be reactive to metals. As a result, it is necessary to understand the effect of BOE treatment on Ohmic metals. The HEMT structures consisted of a 25 nm AlGaN barrier layer, a 0.8 µm C doped GaN buffer layer, a 1.4 µm AlGaN transition layer and a thin AlN nucleation layer on 300 µm Si substrate. HEMT fabrication began with Ti/Al/Ni/Au Ohmic metallization and rapid thermal annealing in N2 at 850ºC for 1 min. Ohmic metals were exposed to BOE for 3 mins. The resistance was monitored every 15 sec by transmission line method (TLM). Scanning electron microscopy (SEM) was used to observe the surface morphology change after BOE exposure. Energy dispersive X-ray spectrum (EDX) and Auger electron analysis was used to characterize the elemental change after BOE exposure. Figure 1 shows the effect of BOE exposure to contact resistance. As shown in Figure 1, the contact resistance increased from 1×10-4 Ω-cm2 to 2×10-4 Ω-cm2 after exposure to BOE for 2 minute. BOE solution is a solution which composed of NH4F and HF. Since the reaction of Ti, Al, and Ni to HF is spontaneous, the increase of contact resistance is expected. The sheet resistance doesn’t change much with BOE treatment time, indicating the GaN is more inert to BOE exposure. Table I shows the elemental change after BOE treatment analyzed by EDX. As shown in TABLE 1, Au decreased by 7% although it supposes to be not reactive to BOE. The content of Ti decreased by 0.1% and the contents for the rest of elements, Al, Ni and N, increased by 0.2, 1.3 and 0.6%, respectively. For EDX, the X-rays are generated in a region about 2 microns in depth of the sample. The thickness of the Ti/Al/Ni/Au Ohmic metallization was around 0.3 µm, and thus the EDX signals of Ga and N should be dominated by the bulk GaN even with some Ga or N out-diffusing through the alloyed Ohmic metallization. Thus, it is reasonable to assume that the Ga and N contents did not change significantly. The percent increases of Ga and N content after BOE treatment were due to the decrease of the Au content. By comparing the increases of percent content of Al, it was less than the percent increase of Ga or N. Therefore, besides Ti and Au, the content of Al also decreased after BOE treatment. However the increase of Ti/Al/Ni/Au Ohmic metallization contact resistance should be mainly caused by the decrease of Au content in the BOE treated sample. Although Au is inert to BOE, Au could be removed by the etching of Al underneath this layer. SEM is also used to observe the surface morphology change after BOE treatment. The Ohmic contacts can be further divided into three different regions, island, ring, and field area. Each island is around 3-5 µm and surrounded by a 1 µm-width Au ring. After BOE treatment, the width became thinner and the island became shorter. With the EDX analysis, Au/Al was found to mainly be distributed in ring area and Ni/Al in the island. Because Al is reactive to BOE, it might be etched and thus peeled off Au in the ring area. The etching of Au might be the reason of thinner width and the increase of contact resistance. In summary, the degradation of Ohmic metallization exposed in BOE was studied. The contact resistance of Ohmic metallization increased significantly after treatment in BOE for 2 minutes. Moreover, after annealing, there were island-like structures surrounded by Au-Al alloy rings and a field area between the islands. The BOE etching occurred mainly at the island and ring areas instead of the field area between the islands. The increase of sheet resistance was due to the etching of surface Al and Ti and the loss of Au in the island and ring areas. Figure 1