Abstract
In this paper, a 100-nm gate length InAs high electron mobility transistor (HEMT) with non-alloyed Ti/Pt/Au ohmic contacts and mesa sidewall channel etch was investigated for high-speed and low-power logic applications. The device exhibited a low subthreshold swing (SS) of 63.3 mV/decade, a drain induced barrier lowering value of 23.3 mV/V, an ION/IOFF ratio of 1.34 $\times$ 104, a Gm,max/SS ratio of 27.6, a current gain cut-off frequency of 439 GHz with a gate delay time of 0.36 ps, and an off-state gate leakage current of less than 1.6 $\times 10^{-5}$ A/mm at VDS = 0.5 V. These results demonstrated that the presence of non-annealed ohmic contacts with mesa sidewall etch process allowed the fabrication of InAs HEMTs with excellent electrical characteristics for high-speed and low-power logic applications.
Highlights
InXGa1−XAs high electron mobility transistor (HEMT) has been widely studied for replacing Si-based devices in future logic applications because of its excellent material properties such as high electron mobility, outstanding electron transport properties when used as a field effect transistor [1]–[3]
The E-mode In0.65Ga0.37As/InAs/In0.65Ga0.37As compositechannel HEMT fabricated with non-alloyed Ti/Pt/Au ohmic contacts, and mesa sidewall channel etch was explored for future high-speed and low-power logic applications
In this study, the InAs HEMTs were evaluated for high-speed logic applications
Summary
InXGa1−XAs high electron mobility transistor (HEMT) has been widely studied for replacing Si-based devices in future logic applications because of its excellent material properties such as high electron mobility, outstanding electron transport properties when used as a field effect transistor [1]–[3]. Using the mesa etching process for device isolation causes a high gate leakage current in conventional InAs HEMTs because of the contact between the gate metal contact and the lowenergy-bandgap (0.36 eV) InAs channel layer [10], which limits the logic applications of the device. YAO et al.: EVALUATION OF 100-nm GATE LENGTH E-MODE InAs HEMT the high selectivity between the InAlAs and InXGa1−XAs layers. This process considerably reduced the contact area between the gate metal and channel layer. The E-mode In0.65Ga0.37As/InAs/In0.65Ga0.37As compositechannel HEMT fabricated with non-alloyed Ti/Pt/Au ohmic contacts, and mesa sidewall channel etch was explored for future high-speed and low-power logic applications
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