Fabricated Schottky Barrier Diodes Research Articles

Pt/ZnGa₂O₄ Schottky Barrier Diodes Fabricated by Using Single Crystal n-ZnGa₂O₄ (111) Substrates

In this letter, we fabricated Schottky barrier diodes (SBDs) using n-type zinc gallium oxide (n-ZnGa2O4) single-crystal substrates, which were grown from the melt by the vertical gradient freeze (VGF) method. X-ray diffraction rocking curve and Laue diffraction results indicate the good crystal quality. The electrical properties of SBDs fabricated on substrates with two doping concentrations are systematically investigated. Heavily-doped (HD) SBDs exhibit lower differential specific on-resistance (~1.13 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{m}\Omega \cdot $ </tex-math></inline-formula> cm2) and lower turn-on voltage (~0.16 V) while the lightly-doped (LD) SBDs exhibit better ideality factor (1.17), rectification characteristics (on/off ratio ~1011) and lower reverse leakage. In addition, we separately tested the electrical properties of the two devices at different temperatures (298 K-473 K). The results of varying temperature show that LD-SBDs have better temperature stability in smaller variation of ideality factor and barrier height with temperature. Based on these experimental results, this work demonstrates the great promise of ZnGa2O4 materials to fabricate high-performance power devices.

Substrate orientation dependent current transport mechanisms in β-Ga2O3/Si based Schottky barrier diodes

Sapphire and gallium oxide have been used as substrates for most of the reported results on β-Ga2O3 devices. However, silicon (Si) is an abundant material on the Earth, leading to easier and low-cost availability of this substrate, along with higher thermal conductivity, which makes Si a promising and potential substrate candidate for rapid commercialization. Therefore, in order to strengthen the feasibility of Ga2O3 on Si integration technology, we have deposited β-Ga2O3 on (100) and (111) oriented p-Si substrates using a pulsed laser deposition technique. A single-phase (β) and polycrystalline nature of the β-Ga2O3 film is observed for both samples using x-ray diffraction. A low root mean square roughness of 3.62 nm has been measured for Ga2O3/Si(100), as compared to 5.43 nm of Ga2O3/Si(111) using atomic force microscope. Moreover, Ga2O3/Si(100) shows a smoother and uniform surface of the Ga2O3 film, whereas Ga2O3/Si(111) seems to have a rougher surface with pitlike defects. This might be due to the hexagonal projection of Si (111) that is not suitable for obtaining a good tilted cuboid or monoclinic Ga2O3 crystal unlike the rectangle projection of Si (100). The electrical parameters of the fabricated Schottky barrier diodes were extracted using current–voltage (I–V) and capacitance–voltage (C–V) characteristics. The polycrystalline Ga2O3 film on Si(100) leads to fewer defects emerging from the Ga2O3/Si heterointerface due to the close symmetry of Ga2O3 and the Si(100) crystal with rectangle projections unlike Ga2O3 on Si(111). These fewer defects eventually lead to a better diode performance of Ga2O3/Si(100) where we have observed typical thermionic dominating carrier transport, whereas defect-assisted thermionic field emission has been the primary carrier transport mechanism in Ga2O3/Si(111). Hence, the Si (100) substrate is demonstrated to be a better and potential platform for Ga2O3 devices than Si (111).

AlGaN/GaN on SiC Devices without a GaN Buffer Layer: Electrical and Noise Characteristics.

We report on the high-voltage, noise, and radio frequency (RF) performances of aluminium gallium nitride/gallium nitride (AlGaN/GaN) on silicon carbide (SiC) devices without any GaN buffer. Such a GaN–SiC hybrid material was developed in order to improve thermal management and to reduce trapping effects. Fabricated Schottky barrier diodes (SBDs) demonstrated an ideality factor n at approximately 1.7 and breakdown voltages (fields) up to 780 V (approximately 0.8 MV/cm). Hall measurements revealed a thermally stable electron density at N2DEG = 1 × 1013 cm−2 of two-dimensional electron gas in the range of 77–300 K, with mobilities μ = 1.7 × 103 cm2/V∙s and μ = 1.0 × 104 cm2/V∙s at 300 K and 77 K, respectively. The maximum drain current and the transconductance were demonstrated to be as high as 0.5 A/mm and 150 mS/mm, respectively, for the transistors with gate length LG = 5 μm. Low-frequency noise measurements demonstrated an effective trap density below 1019 cm−3 eV−1. RF analysis revealed fT and fmax values up to 1.3 GHz and 6.7 GHz, respectively, demonstrating figures of merit fT × LG up to 6.7 GHz × µm. These data further confirm the high potential of a GaN–SiC hybrid material for the development of thin high electron mobility transistors (HEMTs) and SBDs with improved thermal stability for high-frequency and high-power applications.

Classification of Killer and Non-Killer Silicon Carbide Epitaxial Defects and Accurate Prediction of Device Yield

Silicon Carbide continues to become more mainstream and enjoy adoption in various high voltage applications. With the growth of volume and variety of devices shipping to customers, it is important to understand the yield and reliability implications of all the defects that are present in the substrates and epitaxial layers. In our previous works [1,2] we published ways of detecting and screening reliability causing crystal defects. There are however a variety of visible defects present both in the bare substrates and after epitaxial growth. In this work we present the detection and classification of these defects into killer and non-killer defects as measured by electrical tests after device fabrication. This methodology enables the accurate prediction of yield before starting the wafers for device fabrication. We then extend this method to predict yield on various product dies sizes and validate those results experimentally. We have worked to detect all the visible defects present in our epitaxial layers. However due to the large variety of defects present and their varying effect on device performance, just detection is not enough. The defects have to be finely classified into various defect types to gauge their electrical impact. We have classified the defects into various types of triangular defects, fall-down particles, carrots, scratches, pits, step bunching, V-type defects [2,3], large and small topographic defects and defects related to manual handling. Through an iterative process involving electrical characterization of fabricated Schottky barrier diodes (SBD) we have determined which of these classes are killer defects. It is found that mainly fall-down particles, a subset of triangular defects, carrots and large topographic defects are the main causes of electrical failure at wafer sort. Other defects like fainter obtuse triangular defects [4], V-type defects, scratches, step-bunching and pits do not cause outright fails. Second degree effects are observed for many of these non-killer defect types. Other purely crystal defects having no visible defect signatures like basal plane dislocations, stacking faults, grain boundaries were also detected and classified. However these were also determined not to have any influence on SBD device yield at wafer sort. Once the killer defects are determined after epitaxial growth, we created a yield model based on the actual die grid of our actual physical device layout. The yield prediction of this model was tested experimentally and validated for different wafers across multiple lots. A very close agreement of ±2% was observed across all the wafers. This model enables us to predict wafer yield right after epitaxy and before starting the wafers in the fabrication line very accurately. As product lines involve multiple current ratings with different die sizes, a further enhancement of this model was done to predict the yield on a wide variety of die sizes corresponding to device current ratings ranging from 2 Amps to 20 Amps. The predicted yield was validated experimentally and was found to be accurate within ±0.5%. The accuracy of both these models enables very efficient binning of epitaxial wafers to the correct device die size to ensure optimum yield at electrical wafer sort. It is also important to gauge the impact of the non-killer defects on the electrical properties of various devices. Our analysis shows that some of these defects cause slightly increased leakage currents both in the forward conduction and reverse blocking conditions without causing the devices to fail. More extensive measurements and reliability testing is needed to understand some of the longer term impacts of the presence of these classes of defects in the SiC material. Both the above yield models along with the validation against experimental data will be presented. A detailed description of the various classified defect types will be presented. Second order effects of the non-killer defect types on electrical tests will also be discussed. [1] H. Das et al. ECS Transactions, 69 (11) 29-32 (2015) [2] H. Das et al. ECS Transactions, 75 (12) 233-237 (2016) [3] H. Wang et al. Materials Science Forum, Vols. 778-780, 332 (2014) [4] G. Chung et al. Materials Science Forum Vols. 679-680, 123 (2011)

Effect of Surface Morphology on Diode Performance in Vertical GaN Schottky Diodes

The properties of thick GaN layers grown by metal organic chemical vapor deposition on 2″ HVPE substrates were investigated. Although the epilayer is smooth on a microscopic scale with high quality layers as evidenced by X-ray diffraction and photoluminescence, macroscopic morphological variations are observed on the wafer surface. These variations correspond to disparities in leakage current in fabricated Schottky barrier diodes, with rougher macroscopic morphology resulting in increased leakage current.

Relationship between crystal defects and leakage current in β-Ga2O3 Schottky barrier diodes

We fabricated Schottky barrier diodes (SBDs) on the entire surface of a β-Ga2O3 single crystal, and investigated the leakage current in both forward and reverse directions. Subsequently, we investigated the distribution of dislocation and void etch pits on the entire surface. The dislocation etch pit density on the surface ranged from <1 × 103 to 6 × 104, and its average was 1.1 × 104 cm−2. The void etch pit density on the surface ranged from <5 × 102 to 7 × 103, and its average was 6 × 103 cm−2. From a comparison between the SBD leakage current and the dislocation and void etch pit densities, we found that dislocations are closely related to the SBD reverse leakage current, and that not all voids produce the leakage current.

(Invited) Probability of Low Off Angled 4H-SiC Epitaxial Wafers on Power Device Applications

Nowadays, the size of 4H-SiC bulk wafer in R & D stage have already reached at 8-inch. In this situation, wafer off angle is considered to be a big issues on reducing wafer cost due to existence of large material loss when slicing wafers from a SiC ingot. Epitaxial growth technique for low off angle 4H-SiC substrate lower than 4 degree is one of solutions for above issue. However, large step bunching is easily generated on low off angled epitaxial wafer surface and affects the device performance like long time reliability. So, it is very difficult to apply such wafers to power device applications. In this study, we investigated the probability of low off angled 4H-SiC epitaxial wafers on power device applications. To do this purpose, we focused on improvement of surface quality on low off angled epitaxial wafer. In addition, we fabricated Schottky barrier diodes, MOS capacitors, and Trench gate MOSFETs on grown epitaxial wafer and investigated theses characteristics. . In this study, we used horizontal hot wall type CVD with SiH4-C3H8-H2 gas system for epitaxial growth. On substrates, we used 2 degree and 0.8 degree off 4H-SiC Si-face 3 inch substrates that can be conventionally purchased. As the result, we found the balance of growth temperature and C/Si ratio is significantly important to control the generation of step bunching. In our case, when the growth temperature is low about 1500ºoC, the generation of large step bunching can be well suppressed. However, generation of in-grown stacking fault or triangular defects is enhanced. On the other hand, higher growth temperature close to 1700ºoC easily generates such step bunching nevertheless the generation of above defects is well suppressed. This tendency becomes strong with reducing wafer off angle. We could well take a balance between growth temperature and C/Si ratio and suppress the generation of large step bunching on 2 degree off 4H-SiC Si-face epitaxial wafer. By the AFM measurement, we could observe step terrace structure dependence on wafer off angle. The Ra and the step height were 0.48 nm and less than 1 nm at 10 mm square, respectively. It means surface quality of 2 degree off epitaxial wafer is almost the same as that of 4 degree one. We fabricated SBDs and MOS capacitors on as grown surface. For I-V characteristics of SBDs, except for 2 SBDs into 52 points shows good I-V characteristics. For forward characteristics, an average n value of all points is 1.03 and deviation is 1.4%. On the reverse ones, all points showed blocking voltage higher than 600V and an average leakage current density of all points at 600V was 1.70 x 10-7 A/cm2. Concerning MOS capacitors, we carried out the TDDB measurement in whole 3-inch wafer. The number of measurement MOS capacitors is 2099 in whole wafer. The charge-to-breakdown (Qbd) of MOS capacitors fabricated on 2 degree off epitaxial wafer shows the same value with that on 4 degree one. For the epitaxial layer grown on 0.8 degree off 4H-SiC Si-face, we have applied the same way with 2 degree off epitaxial wafer. This way is well effective to suppress the generation of the large step bunching. However, in the view point of triangular defect, this way is not enough to suppress the generation of such defects. To solve this issue, we applied long time hydrogen etching before epitaxial growth. As the results, we could well suppress the generation of triangular defects. On the other hand, step bunching is still remained on the surface of 0.8 degree off Si-face epitaxial layer. We also fabricated trench gate MOSFETs on this wafer. The measured device characteristics are the same as that fabricated on 4 degree off epitaxial wafer. These results mean low off angle epitaxial wafer is possible to use for power device applications. This work was supported by “Novel Semiconductor Power Electronics Project Realizing Low Carbon Emission Society” (2010-2015) organized by Ministry of Economy, Trade, and Industry (METI) and New Energy and Industrial Technology Development Organization (NEDO).

GaN Schottky diodes with single-crystal aluminum barriers grown by plasma-assisted molecular beam epitaxy

GaN-based Schottky barrier diodes (SBDs) with single-crystal Al barriers grown by plasma-assisted molecular beam epitaxy are fabricated. Examined using in-situ reflection high-energy electron diffractions, ex-situ high-resolution x-ray diffractions, and high-resolution transmission electron microscopy, it is determined that epitaxial Al grows with its [111] axis coincident with the [0001] axis of the GaN substrate without rotation. In fabricated SBDs, a 0.2 V barrier height enhancement and 2 orders of magnitude reduction in leakage current are observed in single crystal Al/GaN SBDs compared to conventional thermal deposited Al/GaN SBDs. The strain induced piezoelectric field is determined to be the major source of the observed device performance enhancements.

Capacitance–conductance spectroscopic investigation of interfacial oxide layer in Ni/4H–SiC (0 0 0 1) Schottky diode

In this reported work the interface properties of a process-induced thin interfacial oxide layer present between Ni and 4H–SiC substrate was examined systematically for fabricated Ni/4H–SiC (0001) Schottky barrier diodes. Moreover, their contribution in the form of interface traps level density was investigated employing capacitance–conductance (C–C) spectroscopy techniques. The distinctive parameters of interface at Ni and 4H–SiC substrate were determined from the C–C spectroscopy under forward bias condition. The increase in capacitance value towards lower frequencies results from the presence of interface traps at the Ni/4H–SiC interface however the observed maximums peaks in the normalized conductance curve of the diode indicates the presence of an interfacial layer in the fabricated Schottky barrier diode. It has been found that the density of interface traps level decreases (1.25×1013–1.16×1013cm−2eV−1) and time constant of interface traps (3.16×10−5–1.47×10−3s) increases with bias voltage at anode in the range of Ec-0.06 to Ec-1.06eV from the top of conduction band toward midgap of n-type 4H–SiC substrate. Furthermore, the capture cross section was found to vary from 9.31×10−10cm2 in (Ec-0.06) eV to 4.43×10–11cm2 in (Ec-1.06) eV.

극성/무극성 6H-SiC 쇼트키 베리어 다이오드 제조 및 전기적 특성 연구

We have fabricated schottky barrier diode (SBDs) using polar (c-plane) and non polar (a-, m-plane) n-type 6H-SiC wafers. Ni/SiC ohmic contact was accomplished on the backside of the SiC wafers by thermal evaporation and annealed for 20minutes at <TEX>$950^{\circ}C$</TEX> in mixture gas (<TEX>$N_2$</TEX> 90% + <TEX>$H_2$</TEX> balanced). The specific contact resistance was <TEX>$3.6{\times}10^{-4}{\Omega}cm^2$</TEX> after annealing at <TEX>$950^{\circ}C$</TEX>. The XRD results of the alloyed contact layer show that formation of <TEX>$NiSi_2$</TEX> layer might be responsible for the ohmic contact. The active rectifying electrode was formed by the same thermal evaporation of Ni thin film on topside of the SiC wafers and annealed for 5 minutes at <TEX>$500^{\circ}C$</TEX> in mixture gas (<TEX>$N_2$</TEX> 90% + <TEX>$H_2$</TEX> balanced). The electrical properties of SBDs have been characterized by means of I-V and C-V curves. The forward voltage drop is about 0.95 V, 0.8 V and 0.8 V for c-, a- and m-plane SiC SBDs respectively. The ideality factor (<TEX>${\eta}$</TEX>) of all SBDs have been calculated from log(I)-V plot. The values of ideality factor were 1.46, 1.46 and 1.61 for c-, a- and m-plane SiC SBDs, respectively. The schottky barrier height (SBH) of all SBDs have been calculated from C-V curve. The values of SBH were 1.37 eV, 1.09 eV and 1.02 eV for c-, a- and m-plane SiC SBDs, respectively.

Electrical properties of Au–Sb/p-GaSe:Gd Schottky barrier diode

Experimental results of the fabricated Schottky barrier diode on a GaSe:Gd substrate are presented. The electrical analysis of Au–Sb/p-GaSe:Gd structure has been investigated by means of current–voltage ( I–V) and capacitance–voltage ( C–V) measurements at 296 K temperature. The diode ideality factor and the barrier height have been obtained to be 1.07 and 0.85 eV, respectively, by applying a thermionic emission theory. At high currents in the forward direction, the series resistance effect has been observed. The series resistance has been determined from I– V measurements using Cheung's method.

Power Supply System Using Electromagnetic Induction for Three-Dimensionally Stacked Retinal Prosthesis Chip

We have proposed a new retinal prosthesis system consisting of a three-dimensionally (3-D) stacked retinal prosthesis chip, a flexible cable with an electrode array stimulus, and a power supply system for the retinal prosthesis chip. Electromagnetic induction with a primary coil and a secondary coil was employed as the power supply system. The power was transmitted to the retinal prosthesis chip through an RF/DC voltage conversion chip that converted AC voltage into DC voltage. The 3-D stacked retinal prosthesis chip operates with a DC supply voltage of 3.3 V, and the secondary coil requires a transmitted voltage that is 1 V higher than the DC supply voltage. In order to receive a sufficient supply voltage, several parameters such as external supply voltage and transmission frequency were optimized. A peak RF voltage of 4.5 V was obtained when we employed a primary coil with 50 turns, a secondary coil with 20 turns, an external supply voltage of 4.1 V, and a frequency of 3 MHz. We also successfully fabricated Schottky barrier diodes to rectify the RF voltage received by the secondary coil. The fabricated Schottky barrier diodes have a high breakdown voltage of 4.6 V, which is sufficient for our 3-D stacked retinal prosthesis chip.

ArF-excimer-laser annealing of 3C–SiC films—diode characteristics and numerical simulation

We fabricated Schottky barrier diodes using 3C–SiC films deposited on Si(1 1 1) by lamp-assisted thermal chemical vapor deposition and annealed with an ArF excimer laser. Improvement in both the reverse current and the ideality factor was obtained with 1–3 pulses with energy densities of 1.4– 1.6 J/cm 2 per pulse. We solved a heat equation numerically assuming a transient liquid phase of SiC. The calculated threshold energy density for melting the surface was 0.9 J/cm 2 . The thermal effects of Si substrate on SiC film were also discussed. The experimental optimum condition was consistent the numerical simulation.

MOCVD Growth of InAlAsSb Layer for High-Breakdown Voltage HEMT Applications

ABSTRACTThis paper studies the decomposition characteristic of group-III sources during InAlAsSb growth on InP substrates by metalorganic chemical vapor deposition (MOCVD) using trimethylindium (TMI), trimethylaluminum (TMA), trimethylantimony (TMSb) and arsine (AsH3). A composition analysis of InAlAsSb layers shows that the group-III compositions in the InAlAsSb layer change remarkably when the flow rate of the group-V source is varied. To clarify the reason for this phenomenon, the growth rates of InAsSb and AlAsSb component are examined. Their changes indicate that TMSb suppresses the decomposition of TMA while AsH3 enhances it. Moreover, the HEMT structure with InP/InAlAsSb Schottky barrier layer, whose InP layer acts as a recess-etch-stop layer, is fabricated for the first time. The I-V characteristics of a fabricated Schottky barrier diode indicate that the reverse leakage current of InP/InAlAsSb is about one order of magnitude smaller than that of commonly used InP/InAlAs.

Optical And Electrical Characterisation Study Of SICL4 Reactive Ion Etched Gaas

AbstractIn this study 1016cm−3 n-type epitaxial GaAs was reactive-ion-etched (RIE) in a parallel plate type reactor as a function of rf power and gas pressure using a SiCl4 plasma. The sample matrix followed a 3 level 3 factorial statistical experimental design. Photoreflectance (PR) was employed to characterise the etch induced modification to the electronic band structure at the fundamental band-edge transition. Variable angle spectroscopic ellipsometry (VASE) and photoluminescence (PL) optical diagnostic techniques are also employed to characterise the plasma processed GaAs. PR results detail a decrease in the surface electric field (Fs) with etch severity arising from an RIE induced electron trap that increases in concentration with energetic ion sputtering. For the highest rf power densities PR further distinguishes between reactant desorption and adsorption limited etching regimes. VASE and PL data reveal the extent and degree of surface modification of the etched substrates. Atomic-Force-Microscopy showed the etched surfaces to have an average roughness, Ra of 15nm. Optical characterisation data are correlated with electrical measurements using fabricated Schottky barrier diodes for deep-level-transient spectroscopy (DLTS) as well as current-voltage and capacitance-voltage (CV) analysis. CV results detail a reduced surface carrier concentration after RIE while DLTS revealed the emergence of six electron trap defect levels. One of the two prominent RIE induced trap levels exhibited similar DLTS behaviour as that produced after ion bombardment of n-type (Si) GaAs.

A characterization technique for the degradation characteristics of Ti/Si schottky-barrier diodes and ohmic contacts after thermal silicidation

The effects of thermal silicidation on both the nonideal current-voltage characteristics of the Schottky-barrier diodes and the degradation properties of the ohmic contacts have been self-consistently characterized by using a simple interfacial-layer theory. The abruptly changed nonideality of the measured I– V characteristics as TiSi 2 is formed can be interpreted as the variations of the interface properties, such as the thermal-equilibrium barrier height, the interfacial-layer capacitance, and the density distribution of the interface state. Moreover, different work functions for Ti and TiSi 2 and the change of the dominant type of the interface states and their density distributions are shown to be responsible for the fluctuations of the thermal-equilibrium barrier height after thermal silicidation. Furthermore, the interface parameters extracted from the fabricated Schottky-barrier diodes are used to calculate and compare the simultaneously-processed specific contact resistivities, and satisfactory agreement is obtained. Thus, the silicidation-related degradation characteristics of the ohmic contacts can be directly related to the variations of the interface properties at the Ti/Si interface.