Extreme Energy Efficiency Research Articles

Exploiting Inherent Error Resiliency of Deep Neural Networks to Achieve Extreme Energy Efficiency Through Mixed-Signal Neurons

Neuromorphic computing, inspired by the brain, promises extreme efficiency for certain classes of learning tasks, such as classification and pattern recognition. The performance and power consumption of neuromorphic computing depend heavily on the choice of the neuron architecture. Digital neurons (Dig-N) are conventionally known to be accurate and efficient at high speed while suffering from high leakage currents from a large number of transistors in a large design. On the other hand, analog/mixed-signal neurons (MS-Ns) are prone to noise, variability, and mismatch but can lead to extremely low-power designs. In this paper, we will analyze, compare, and contrast existing neuron architectures with a proposed MS-N in terms of performance, power, and noise, thereby demonstrating the applicability of the proposed MS-N for achieving extreme energy efficiency (femtojoule/multiply and accumulate or less). The proposed MS-N is implemented in 65-nm CMOS technology and exhibits $> 100\times $ better energy efficiency across all frequencies over two traditional Dig-Ns synthesized in the same technology node. We also demonstrate that the inherent error resiliency of a fully connected or even convolutional neural network can handle the noise as well as the manufacturing nonidealities of the MS-N up to certain degrees. Notably, a system-level implementation on CIFAR-10 data set exhibits a worst case increase in classification error by 2.1% when the integrated noise power in the bandwidth is $\sim 0.1 ~\mu $ V2, along with $\pm 3\sigma $ amount of variation and mismatch introduced in the transistor parameters for the proposed neuron with 8-bit precision.

Spatio-temporal dynamics of urban residential CO2 emissions and their driving forces in China using the integrated two nighttime light datasets

Increasing urban residential energy consumption and CO2 emissions pose a critical challenge for regional carbon reduction policy. This study integrated two nighttime light datasets: the Defense Meteorological Satellite Program’s Operational Linescan System (DMSP-OLS) nighttime light images and the Suomi National Polar-orbiting Partnership (NPP) Visible Infrared Imaging Radiometer Suite (VIIRS) composite data to improve on estimates of urban residential CO2 emissions from 2000 to 2015 at 1 km resolution. Then, the driving forces including socio-economic factors and climatic factors were discussed using spatial econometrics models based on panel data covering 288 prefecture-level cities. The results show that models built for the northern and southern regions separately performed better than those for the entire country in estimating urban residential CO2 emissions, which strongly suggests that climatic factors affect the behavior of urban residents and CO2 emissions. The spatio-temporal analysis revealed that rapid growth in emissions occurred in provincial capitals and was mainly concentrated in central China. Gross Domestic Product and energy utilization technology were associated with higher CO2 emission while GDP per capita and the number of employed workers had a negative effect. Measures based on daily mean temperatures had a substantial negative correlation with CO2 emissions. In contrast, the average of daily maximum air temperature in summer correlated with higher CO2 emissions. We conclude that extreme weather events and energy efficiency should be of particular concern for policy makers.

The Quest for Energy-Efficient I$ Design in Ultra-Low-Power Clustered Many-Cores

High performance and extreme energy efficiency are strong requirements for a fast-growing number of edge-node Internet of Things (IoT) applications. While traditional Ultra-Low-Power designs rely on single-core micro-controllers (MCU), a new generation of architectures leveraging fully programmable tightly-coupled clusters of near-threshold processors is emerging, joining the performance gain of parallel execution over multiple cores with the energy efficiency of low-voltage operation. In this work, we tackle one of the most critical energy-efficiency bottlenecks for these architectures: instruction memory hierarchy. Exploiting the instruction locality typical of data-parallel applications, we explore two different shared instruction cache architectures, based on energy-efficient latch-based memory banks: one leveraging a crossbar between processors and single-port banks (SP), and one leveraging banks with multiple read ports (MP). We evaluate the proposed architectures on a set of signal processing applications with different executable sizes and working-sets. The results show that the shared cache architectures are able to efficiently execute a much wider set of applications (including those featuring large memory footprint and irregular access patterns) with a much smaller area and with much better energy efficiency with respect to the private cache. The multi-port cache is suitable for sizes up to a few kB, improving performance by up to 40 percent, energy efficiency by up to 20 percent, and energy $\times$ area efficiency by up to 30 percent with respect to the private cache. The single-port solution is more suitable for larger cache sizes (up to 16 kB), providing up to 20 percent better energy $\times$ area efficiency than the multi-port, and up to 30 percent better energy efficiency than private cache.

3D multilevel spin transfer torque devices

Spin-transfer torque magnetic tunneling junction devices capable of a multilevel three-dimensional (3D) information processing are studied in the sub-20-nm size range. The devices are built using He+ and Ne+ focused ion beam etching. It has been demonstrated that due to their extreme scalability and energy efficiency, these devices can significantly reduce the device footprint compared to the modern CMOS approaches and add advanced features in a 3D stack with a sub-20-nm size using a spin polarized current.

ENERGY EFFICIENCY IN RESIDENTIAL BUILDINGS, LESS STRAIGHT FORWARD THEN PRESUMED

<jats:p>Since the 1990s, the successive EU directives and related national or regional legislations require new construction and retrofits to be as much as possible energy-efficient. Several measures that should stepwise minimize the primary energy use for heating and cooling have become mandated as requirement. However, in reality, related predicted savings are not seen in practice. Two effects are responsible for that. The first one refers to dweller habits, which are more energy-conserving than the calculation tools presume. In fact, while in non-energy-efficient ones, habits on average result in up to a 50% lower end energy use for heating than predicted. That percentage drops to zero or it even turns negative in extremely energy-efficient residences. The second effect refers to problems with low-voltage distribution grids not designed to transport the peaks in electricity whensunny in summer. Through that, a part of converters has to be uncoupled now and then, which means less renewable electricity. This is illustrated by examples that in theory should be net-zero buildings due to the measures applied and the presence of enough photovoltaic cells (PV) on each roof. We can conclude that mandating extreme energy efficiency far beyond the present total optimum value for residential buildings looks questionable as a policy. However, despite that, governments and administrations still seem to require even more extreme measurements regarding energy efficiency.</jats:p>

Chifley Passive House: A Case Study in Energy Efficiency and Comfort

Abstract: Numerous mandatory energy efficiency building standards and rating systems have been developed globally. The International Passive House Standard is a voluntary alternative, but there is little data on the performance of houses built to this standard in Australia. One house in suburban Canberra demonstrates that the Passive House Standard can be used to build high-performance houses with predictable outcomes. Extreme energy efficiency and occupant comfort were key performance objectives in building the three-bedroom house. Like most energy efficient housing projects in Australia, the building was designed to take advantage of solar gain, thermal mass and cross flow ventilation, but what set this project and all Passive House projects apart was the careful attention to airtightness, mechanical ventilation, avoidance of thermal bridging and the use of energy modelling tools at the design stage. The result was a house that required virtually no heating in winter despite frosty -2°C mornings; no artificial cooling in summer despite 37°C days and; overall consumed 64% less energy than similar households in the same city. Energy consumption, temperature and CO2 levels have been monitored and confirm exceptional levels of comfort and indoor air quality. The total energy consumed was within 12% of predicted values thus supporting the effectiveness of the Passive House Standard.

SCNN

Convolutional Neural Networks (CNNs) have emerged as a fundamental technology for machine learning. High performance and extreme energy efficiency are critical for deployments of CNNs, especially in mobile platforms such as autonomous vehicles, cameras, and electronic personal assistants. This paper introduces the Sparse CNN (SCNN) accelerator architecture, which improves performance and energy efficiency by exploiting the zero-valued weights that stem from network pruning during training and zero-valued activations that arise from the common ReLU operator. Specifically, SCNN employs a novel dataflow that enables maintaining the sparse weights and activations in a compressed encoding, which eliminates unnecessary data transfers and reduces storage requirements. Furthermore, the SCNN dataflow facilitates efficient delivery of those weights and activations to a multiplier array, where they are extensively reused; product accumulation is performed in a novel accumulator array. On contemporary neural networks, SCNN can improve both performance and energy by a factor of 2.7x and 2.3x, respectively, over a comparably provisioned dense CNN accelerator.

Flexible, Scalable and Energy Efficient Bio-Signals Processing on the PULP Platform: A Case Study on Seizure Detection

Ultra-low power operation and extreme energy efficiency are strong requirements for a number of high-growth application areas requiring near-sensor processing, including elaboration of biosignals. Parallel near-threshold computing is emerging as an approach to achieve significant improvements in energy efficiency while overcoming the performance degradation typical of low-voltage operations. In this paper, we demonstrate the capabilities of the PULP (Parallel Ultra-Low Power) platform on an algorithm for seizure detection, representative of a wide range of EEG signal processing applications. Starting from the 28-nm FD-SOI (Fully Depleted Silicon On Insulator) technology implementation of the third embodiment of the PULP architecture, we analyze the energy-efficient implementation of the seizure detection algorithm on PULP. The proposed parallel implementation exploits the dynamic voltage and frequency scaling capabilities, as well as the embedded power knobs of the PULP platform, reducing energy consumption for a seizure detection by up to 10× with respect to a sequential implementation at the nominal supply voltage and by 4.2× with respect to a sequential implementation with voltage scaling. Moreover, we analyze the trans-precision optimization of the algorithm on PULP, by means of a hybrid fixed- and floating-point implementation. This approach reduces the energy consumption by up to 43% with respect to the plain fixed-point and floating-point implementations, leveraging the requirements in terms of the precision of the kernels composing the processing chain to improve energy efficiency. Thanks to the proposed architecture and system-level approach for optimization, we demonstrate that PULP reduces energy consumption by up to 140× with respect to commercial low-power microcontrollers, being able to satisfy the real-time constraints typical of bio-medical applications, breaking the barrier of microwatts for a 50-ms complete seizure detection and a few milliwatts for a 5-ms detection latency on a fully-programmable architecture.

(Invited) Non-Volatile Redox Transistors for Low Power Computing and Brain-Machine Interfaces

The widely anticipated end to Moore’s law and the growing demand for low power computing systems capable of learning, image recognition and real-time analysis of large streams of unstructured data has spurred intense interest in neural algorithms for brain-inspired computing. The brain is capable of massively parallel information processing while consuming only ~1- 100 fJ per synaptic event. Inspired by the efficiency of the brain, CMOS-based neural architectures and tunable resistance elements (memristors) are being developed for low-power pattern recognition and machine learning. However, the volatility, design complexity and high supply voltages for CMOS architectures on one hand, and the stochastic and energy-costly switching of memristors on the other significantly complicate the path to achieve the extreme interconnectivity, information density, and energy efficiency of the brain using either approach. To overcome these limitations, we have recently demonstrated a Li-ion synaptic transistor for analog computation (LISTA).1 LISTA is an all solid-state, non-volatile redox transistor (NVRT) with a resistance switching mechanism based upon the intercalation of Li-ion dopants into a channel of Li1-xCoO2. An NVRT differs from previously described electrochemical transistors in that dopants cannot diffuse out of the channel (after relaxation of applied bias) without an external source of charge to facilitate oxidation and liberate them as ions in a surrounding electrolyte. This is identical to the charge storage mechanism in batteries, which require external current sources to drive charge/discharge redox reactions. A major advantage of the LISTA device is that resistance switching can occur without inducing large structural transformations that are common for memristive devices, such as filament formation or amorphous-to-crystalline phase transformation. In my talk I will show that the structurally stable, diffusion-driven switching mechanism of Li intercalation allows LISTA to operate with a low ‘write’ noise, a near linear response to ‘write’ operations, and orders of magnitude lower switching voltages and currents. Furthermore, our simulations of the device physics demonstrate that scaled LISTA devices will have orders of magnitude lower energy consumption than any resistive memory device to date, and could operate as part of a neural architecture with an energy efficiency matching the brain. Finally, I will introduce an NVRT device based entirely on organic polymers fabricated on flexible substrates. Such devices could in principle form direct interfaces with the brain opening up the opportunity to build advanced neural prostheses with integrated brain-machine interfaces. 1.Fuller, E. J.; Gabaly, F. E.; Léonard, F.; Agarwal, S.; Plimpton, S. J.; Jacobs-Gedrim, R. B.; James, C. D.; Marinella, M. J.; Talin, A. A., Li-Ion Synaptic Transistor for Low Power Analog Computing. Advanced Materials 2016, DOI: 10.1002/adma.201604310

Toward Massive Machine Type Cellular Communications

Cellular networks have been engineered and optimized to carrying ever-increasing amounts of mobile data, but over the last few years, a new class of applications based on machine-centric communications has begun to emerge. Automated devices such as sensors, tracking devices, and meters, often referred to as machine-to-machine (M2M) or machine-type communications (MTC), introduce an attractive revenue stream for mobile network operators, if a massive number of them can be efficiently supported. The novel technical challenges posed by MTC applications include increased overhead and control signaling as well as diverse application-specific constraints such as ultra-low complexity, extreme energy efficiency, critical timing, and continuous data intensive uploading. This article explains the new requirements and challenges that large-scale MTC applications introduce, and provides a survey of key techniques for overcoming them. We focus on the potential of 4.5G and 5G networks to serve both the high data rate needs of conventional human-type communication (HTC) subscribers and the forecasted billions of new MTC devices. We also opine on attractive economic models that will enable this new class of cellular subscribers to grow to its full potential.

A 60 GOPS/W, −1.8 V to 0.9 V body bias ULP cluster in 28 nm UTBB FD-SOI technology

Ultra-low power operation and extreme energy efficiency are strong requirements for a number of high-growth application areas, such as E-health, Internet of Things, and wearable Human–Computer Interfaces. A promising approach to achieve up to one order of magnitude of improvement in energy efficiency over current generation of integrated circuits is near-threshold computing. However, frequency degradation due to aggressive voltage scaling may not be acceptable across all performance-constrained applications. Thread-level parallelism over multiple cores can be used to overcome the performance degradation at low voltage. Moreover, enabling the processors to operate on-demand and over a wide supply voltage and body bias ranges allows to achieve the best possible energy efficiency while satisfying a large spectrum of computational demands. In this work we present the first ever implementation of a 4-core cluster fabricated using conventional-well 28nm UTBB FD-SOI technology. The multi-core architecture we present in this work is able to operate on a wide range of supply voltages starting from 0.44V to 1.2V. In addition, the architecture allows a wide range of body bias to be applied from −1.8V to 0.9V. The peak energy efficiency 60 GOPS/W is achieved at 0.5V supply voltage and 0.5V forward body bias. Thanks to the extended body bias range of conventional-well FD-SOI technology, high energy efficiency can be guaranteed for a wide range of process and environmental conditions. We demonstrate the ability to compensate for up to 99.7% of chips for process variation with only ±0.2V of body biasing, and compensate temperature variation in the range −40°C to 120°C exploiting −1.1V to 0.8V body biasing. When compared to leading-edge near-threshold RISC processors optimized for extremely low power applications, the multi-core architecture we propose has 144× more performance at comparable energy efficiency levels. Even when compared to other low-power processors with comparable performance, including those implemented in 28nm technology, our platform provides 1.4× to 3.7× better energy efficiency.

Hybrid Cache Designs for Reliable Hybrid High and Ultra-Low Voltage Operation

Geometry scaling of semiconductor devices enables the design of ultra-low-cost (e.g., below 1 USD) battery-powered resource-constrained ubiquitous devices for environment, urban life, and body monitoring. These sensor-based devices require high performance to react in front of infrequent particular events as well as extreme energy efficiency in order to extend battery lifetime during most of the time when low performance is required. In addition, they require real-time guarantees. The most suitable technological solution for these devices consists of using hybrid processors able to operate at: (i) high voltage to provide high performance and (ii) near-/subthreshold voltage to provide ultra-low energy consumption. However, the most efficient SRAM memories for each voltage level differ and trading off different SRAM designs is mandatory. This is particularly true for cache memories, which occupy most of the processor's area. In this article, we propose new, simple, single-Vcc-domain hybrid L1 cache architectures suitable for reliable hybrid high and ultra-low voltage operation. In particular, the cache is designed by combining heterogeneous SRAM cell types: some of the cache ways are optimized to satisfy high-performance requirements during high voltage operation, whereas the rest of the ways provide ultra-low energy consumption and reliability during near-/subthreshold voltage operation. We analyze the performance, energy, and power impact of the proposed cache designs when using them to implement L1 caches in a processor. Experimental results show that our hybrid caches can efficiently and reliably operate across a wide range of voltages, consuming little energy at near-/subthreshold voltage as well as providing high performance at high voltage without decreasing reliability levels to provide strong performance guarantees, as required for our target market.

Energy Efficient Programmable MIMO Decoder Accelerator Chip in 65-nm CMOS

This paper presents an energy efficient programmable hardware accelerator that targets multiple-input-multiple-output (MIMO) decoding tasks of orthogonal frequency-division multiplexing (OFDM) systems. The work is motivated by the adoption of MIMO and OFDM by almost all existing and emerging high-speed wireless data communication systems. The accelerator was fabricated in 65-nm CMOS technology and occupies a core area of 2.48 mm 2 . It delivers full programmability across different wireless standards (i.e., WiFi, 3G-long term evolution, and WiMax) as well as different MIMO decoding algorithms (i.e., minimum mean square error, singular value decomposition, and maximum likelihood) with extreme energy efficiency. The energy efficiency of our MIMO accelerator chip was compared against dedicated application specific integrated circuits for 4 × 4 QR decomposition, 4 × 4 singular value decomposition, and 2 × 2 minimum mean square error decoding. Despite the programmable nature of our design, it delivered energy efficiencies that were 18% to 28% better than the dedicated solutions reported in the literature. This paper presents the VLSI implementation of the architecture discussed in [14]-[16]. It discusses the implementation decisions and tradeoffs used to ensure minimum overall energy consumption of the resulting accelerator chip without sacrificing programmability. Given its programmability and extreme energy efficiency, the accelerator is an ideal solution for today's smart phones that implement multiple MIMO-OFDM waveforms on the same platform.

Extreme Energy Efficiency: In the city, in the country, and beyond

Extreme Energy Efficiency: In the city, in the country, and beyond

Challenges in body area networks for healthcare: the MAC

Body area wireless sensor networks (BANs) are a key component to the ubiquitous healthcare revolution and perhaps one of its most challenging elements from a communications standpoint. The unique characteristics of the wireless channel, coupled with the need for extreme energy efficiency in many healthcare applications, require novel solutions in medium access control protocols. We present the main characteristics and challenges associated with BANs from a healthcare perspective, and present some MAC techniques based on studies of the BAN channel that could be used to address these challenges.