Parasitic Capacitance Extraction Research Articles

Consistent and reliable MESFET parasitic capacitance extraction method

An improved model is proposed to evaluate the parasitic capacitances of GaAs MESFET transistors from the cold-FET S-parameter. Inherent in most conventional parasitic de-embedding methods, the extraction result for Cpd varies drastically with Vgs under cold-FET measurement, and this is in great contradiction with the normally adopted bias-independent Cpd assumption in active device modelling. An improved model is proposed to tackle this problem. Model parameters can thus be uniquely determined by using only two sets of cold-FET S-parameters under different Vgs biasing conditions. The resulting capacitance value, Cpd, is found to be independent of Vgs when Vgs<Vp.

Hierarchical Block Boundary-Element Method (HBBEM): A Fast Field Solver for 3-D Capacitance Extraction

As feature size decrease, fast and accurate parasitic capacitance extraction has become increasingly critical for verification and analysis in very large scale integration design. In this paper, a fast hierarchical-block boundary-element method based on the boundary-element method (BEM) is presented for three-dimensional (3-D) capacitance extraction, which can give out the global capacitance matrix directly. It assigns the global computation of 3-D domain into local computation in BEM blocks by hierarchical partition 3-D structure. The boundary capacitance matrix (BCM) is computed in the BEM block using all the known conditions. Reuse technology can decrease the running time. After merging the BCMs of all BEM blocks, the global capacitance matrix for a given set of conductors can be computed. Numerical results show that this global hierarchical approach can get very high speed in 3-D computation with equal accuracy as the 3-D field solver.

Measurements and extractions of parasitic capacitances in ulsi layouts

This paper deals with the extraction of parasitic capacitances of interconnects in submicron layouts. It is well known that, in integrated circuits, the signal delay due to interconnects is comparable to that of gates. This aspect becomes particularly important, for example, during the design of clock trees in high-speed applications. In general, capacitance extraction is carried out with software tools but they should be validated on a set of geometrical structures, which have been accurately characterized and that are representative of the circuit layouts. Experimental characterization of these structures and their set up in a golden set of measures is still a challenging task. In this paper, we first describe some experimental approaches to measure capacitances of structures from the golden set and in particular we identify a high accuracy transducer based on pass-gate transistors. We then propose a software implementation of the floating random walk algorithm that solves the drawbacks in the extraction of capacitances of interconnects in a nonhomogeneous medium as an industrial layout. Finally, experimental and simulation results are presented, validating the adopted approach.

Statistical method for the analysis of interconnects delay in submicrometer layouts

In deep-submicrometer layouts, the determination of the signal delay due to interconnects is a main aspect of the design. Usually, on-chip interconnects are modeled by a distributed resistance-capacitance (RC) line. Key aspects of the interconnect modeling are the extraction of parasitic capacitances and the determination of reduced lumped models suited for electrical simulation. This paper addresses both these aspects. The parasitic capacitance extraction problem of layouts is efficiently carried out by means of the floating random walk (FRW) algorithm. It is shown how the employment of the Monte Carlo integration jointly to an extended version of the FRW algorithm allows to directly synthesize an accurate reduced-order RC equivalent net. The new method can deal with very complex geometries in an efficient way and needs neither fracturing of the original layout into subregions nor discretization of interconnects.

A system for full-chip and critical net parasitic extraction for ULSI interconnects using a fast 3-D field solver

As integrated circuit (IC) manufacturing technology pushes toward the deep submicron (DSM) regime, the interconnect behavior begins to dominate the overall chip performance. Traditional interconnect characterization methods do not offer the required accuracy or the versatility to tackle challenges of DSM design. We present a system for interconnect parasitic capacitance extraction using an extremely fast three-dimensional (3-D) solver, capable of handling general geometry configurations and providing high accuracy. The contributions in this work make 3-D field solvers an attractive and, for the first time, computationally feasible approach to calculating interconnect parasitics. The system represents a significant performance leap in 3-D interconnect characterization, making it well suited for full-chip extraction and for high-accuracy characterization of critical nets, block IP, and standard and custom cell designs.

A statistical algorithm for 3D capacitance extraction

This letter deals with the problem of parasitic capacitance extraction in deep suhmicron layouts having general geometries. The presented extraction method is based on the statistical floating random walk algorithm. It employs a suitable spherical Green's function that, in a charge free region, relates the electrical field in the sphere center to the surface electrical potential.

A multilevel parasitic interconnect capacitance modeling and extraction for reliable VLSI on-chip clock delay evaluation

This paper describes fringing and coupling interconnect capacitance models which include the nonlinear second-order effects of field interactions among multilevel parasitic interconnects for accurate circuit simulations. They are fitted well with numerical solutions by using a Poisson equation solver. A reliable parasitic distributed resistance-inductance-capacitance (RLC) extraction method is identified by using the solver with the bounded local three-dimensional (3-D) numerical analysis to reduce excessive central processing unit (CPU) time compared to full 3-D numerical simulation. We investigate the impact of input slew variations on the traversal clock delay within the slow ramp region of the driver gate as well as in the extracted parasitic interconnect networks. Input slew is found to be a dominant factor affecting clock delay sensitivity. In addition, we use indirect on-chip electron beam probing to confirm that the simulated clock delays are in reasonable agreement with the measured delays.

A simple method for on-chip, sub-femto Farad interconnect capacitance measurement

In this letter, a sensitive and simple technique for parasitic interconnect capacitance measurement and extraction is presented. This on-chip technique is based upon an efficient test structure design that utilizes only two transistors in addition to the unknown interconnect capacitance to be characterized. No reference capacitor is needed. The measurement itself is also simple; only a dc current meter is required. Furthermore, the extraction methodology employs a self-checking algorithm to verify that the extracted capacitance value is consistent and accurate. The technique is demonstrated by extracting the capacitance of a single crossover between a Metal 1 line and a Metal 2 of 0.44 fF. The resolution limit is dominated by the matching of the minimum sized transistors used for the test structure. We estimate this resolution limit to be about 0.03 fF.