External Cache Research Articles

An efficient visual exploration approach of geospatial vector big data on the web map

The visual exploration of geospatial vector data has become an increasingly important part of the management and analysis of geospatial vector big data (GVBD). With the rapid growth of data scale, it is difficult to realize efficient visual exploration of GVBD by current visualization technologies even if parallel distributed computing technology is adopted. To fill the gap, this paper proposes a visual exploration approach of GVBD on the web map. In this approach, we propose the display-driven computing model and combine the traditional data-driven computing method to design an adaptive real-time visualization algorithm. At the same time, we design a pixel-quad-R tree spatial index structure. Finally, we realize the multilevel real-time interactive visual exploration of GVBD in a single machine by constructing the index offline to support the online computation for visualization, and all the visualization results can be calculated in real-time without the external cache occupation. The experimental results show that the approach outperforms current mainstream visualization methods and obtains the visualization results at any zoom level within 0.5 s, which can be well applied to multilevel real-time interactive visual exploration of the billion-scale GVBD.

CALM: QoS-Aware Vehicular Sensor-as-a-Service Provisioning in Cache-Enabled Multi-Sensor Cloud

This work addresses the problem of QoS-aware cache selection for provisioning vehicular sensors-as-a-service (Se-aaS) in the presence of multiple sensor-cloud service providers (SCSPs), vehicle owners, and roadside units. In cache-enabled sensor-cloud, each SCSP serves the applications from its internal and external caches, which may not be feasible in vehicular networks due to lack of resources. Moreover, in vehicular sensor-cloud, the SCSP may not have access to the required data; hence it loses revenue. To address these issues, we propose a game-theoretic cache orchestration scheme, named CALM, for multi-sensor-cloud. CALM is performed in two stages. In the first stage, after receiving the end-users’ service request, the requested SCSP identifies the optimal subset of internal caches using an expected utility theory. If the service is not executed in the first stage, the SCSP identifies the optimal subset of external caches at the RSUs in the second stage. In this stage, we use a single-leader-multiple-followers Stackelberg game, where the SCSP and the RSUs act as the leader and followers, respectively. We evaluate the performance of CALM theoretically and through simulation, while comparing it with the existing schemes. Simulation results depict that using CALM, the profit of SCSP and service delay improve by 33.91% and 20.79%, respectively.

Off-chip prefetching based on Hidden Markov Model for non-volatile memory architectures.

Non-volatile memory technology is now available in commodity hardware. This technology can be used as a backup memory for an external dram cache memory without needing to modify the software. However, the higher read and write latencies of non-volatile memory may exacerbate the memory wall problem. In this work we present a novel off-chip prefetch technique based on a Hidden Markov Model that specifically deals with the latency problem caused by complexity of off-chip memory access patterns. Firstly, we present a thorough analysis of off-chip memory access patterns to identify its complexity in multicore processors. Based on this study, we propose a prefetching module located in the llc which uses two small tables, and where the computational complexity of which is linear with the number of computing threads. Our Markov-based technique is able to keep track and make clustering of several simultaneous groups of memory accesses coming from multiple simultaneous threads in a multicore processor. It can quickly identify complex address groups and trigger prefetch with very high accuracy. Our simulations show an improvement of up to 76% in the hit ratio of an off-chip dram cache for multicore architecture over the conventional prefetch technique (g/dc). Also, the overhead of prefetch requests (failed prefetches) is reduced by 48% in single core simulations and by 83% in multicore simulations.

Platfora Method for High Data Delivery in Large Datasets

Platfora helps business users and data analyst to visually interact with large volume of data in seconds, letting them to work with even the easiest forms of transaction, user interaction, and machine data. In big data retrieval a cooperativebased database caching system for large datasets and the heart of the system catch submitted queries to database. In data caches, nodes that already request a cache in the queries are used as indices to retrieve the data. Based on the external database and caching systems are formed for requested data to retrieve from distributed file system in cloud. In the existing tool Hadoop having different limitations is a very low-level implementation to analyze the requirements like Map Reducing, extensive knowledge for developer to operate different PLATFORA. The user’s queries turn into Hadoop jobs automatically, and create an abstraction layer if anyone can exploit to reduce and manage datasets stored in the Hadoop that related to PLATFORA. To analyze the Hamlet framework allows the users to take caching decision system for content and then retrieve from the large datasets. In this paper we focus on sky tree to analyze a machine learning language and data analytics platform focused on handling the Big Data.

Optimal placement of on-load tap changers in distribution networks using SA-TLBO method

Abstract This paper presents a multi-objective optimal location of on-load tap changers (OLTCs) in distribution systems at spirit of distributed generators (DGs) based on Teaching–Learning-Based optimization coupled with Simulated annealing algorithm (SA-TLBO). In the suggested algorithm, teacher and learner phases are modified by SA. The proposed algorithm utilizes several teachers and considers the teachers as an external cache to store found Pareto optimal solutions during the search process. The proposed approach allows the decision maker to take one of the Pareto optimal solutions (by trade-off) for different applications. The performance of the SA-TLBO algorithm on a 70-bus distribution network in comparison with other methods such as GA, PSO, SA and TLBO is remarkable.

A hybrid storage technology for low power consumption and high I/O performance in an IPTV set-top box

A new method of prefetching data blocks from the NVCache to the page cache in main memory and cascading prefetching n-blocks from a hard disk to the NVCache together was proposed to reduce the spin-up frequency of a hybrid hard disk drive and thus enhance I/O performance. The proposed method consists of three steps: 1) Analyzing the pattern of read requests in block units; 2) Determining the number of blocks prefetched to the NVCache; 3) Replacing blocks in the NVCache according to the block replacement policy. The proposed method can reduce the latency time of a hybrid hard disk and optimize the power consumption of an IPTV set-top box. Experimental results show that the proposed method provides better average response time compared to an existing adaptive multistream prefetching (AMP) method by 25.17%. It also reduces by 20.83% the average power consumption over that of the existing external caching in energy saving storage system (EXCES) method.

基于FPGA的AMOLED驱动方案

This paper presents a driving scheme based on FPGA for the 17.8 cm(7 in) active matrix organic light emitting display(AMOLED) using μc-Si TFT technology.This scheme is easy to be implemented.It doesn't require external cache,and consequently the difficulty of PCB layout and system control is reduced.It presents a method connecting screen with IC to resolve the problem that it is not matching between AMOLED with LCD Driver IC.Architecture of the system and operating principle of each module within the FPGA are presented in detail.And the simulation results by computer and the results tested by oscillograph on the timing and controlling signals are provided.The results indicate this design can implement the dynamic video display on AMOLED with 64 gray scales.

Frequency, composition and variation in external food stores constructed by orb-web spiders: Nephila edulis and Nephila plumipes (Araneae : Araneoidea)

Few examples of food hoarding have been documented in spiders, yet two Australian species of orb-web spiders, Nephila edulis and N. plumipes, typically incorporate previously captured prey into the web. The effect of prey density and prey-encounter rate on the storage behaviour of adult female N. edulis was tested in the laboratory. Prey density had a significant effect on the propensity to construct external caches: when more food was available, food caches were larger than when the supply of prey was limited. Caching behaviour also differed with the rate of prey encounter, even though the total amount of food supplied was the same. When prey were encountered at constant rates, spiders allocated more food to external storage compared with random encounter rates. Finally, we tested the quality of different prey types for external or internal storage. N. edulis were fed with blow-flies or crickets, and these prey were stored in the web, discarded or totally consumed. Crickets were typically consumed or stored, while flies were more frequently discarded. Field observations of the storage behaviour in N. edulis and N. plumipes found surprising differences in the composition of the cache. While N. plumipes incorporated only animal material, N. edulis also utilised plant material, suggesting that the storage band in N. edulis has other, non-food-storing functions. Field experiments indicated that the presence or absence of external stores in the web of N. plumipes had no influence on mortality, weight gain, or the presence of Argyrodes kleptoparasites.

High-voltage-tolerant I/O buffers with low-voltage CMOS process

This paper presents high-voltage-tolerant I/O buffer designs for a 1.9-V external cache interface and a 3.3-V system interface using 1.9-V MOS transistors in a 0.21-/spl mu/m process with 40-/spl Aring/ gate-oxide thickness. Various circuit techniques are used for 1.9- and 3.3-V I/O buffers to ensure that the voltage across the gate oxide of every MOS element is below specified limits of 2.2 V for transient (short duty cycle) and 1.9 V for steady state. Only one PMOS pullup driver transistor between the bond pad and the power supply, and one NMOS pulldown driver transistor between the bond pad and ground, are used for the 1.9-V I/O buffer design, while cascoded MOS transistors between the bond pad and power supply or ground terminals are used for the 3.3-V I/O buffer design. The primary design goal is to ensure the reliability of MOS elements by avoiding excessive gate oxide stress due to high electric fields. However, due to differences in requirements for speed, power-supply voltage, and tristate leakage current, completely different circuit techniques have been used for the two designs. Both of the designs have been successfully implemented in a 400-MHz UltraSPARC microprocessor.

Design and implementation of dual processor block with shared external cache memory

The availability of low cost, high performance microprocessors has led to various designs of shared memory multiprocessor systems. As a result, commercial products which are based on shared memory have been proliferated. Such a multiprocessor system is heavily influenced by the structure of memory system and it is not difficult to find that most configurations include local cache memories. The more processors a system carries, the larger local cache memory is needed to maintain the traffic to and from the shared memory at reasonable level. The implementation of local cache memories, however, is not a simple task because of environmental limitations. In particular, the general lack of board space availability presents a formidable problem. A cache memory system usually needs space mostly to support its complex control logic circuits for the cache itself and network interfaces like snooping logic circuits for shared bus. Although packaging can be made denser to reduce system size, there are still multiple processors per board. It requires a more area-efficient cache memory architecture. This paper presents a design of shared cache for dual processor board of bus-based symmetric multiprocessors. The design and implementation issues are described first and then the evaluation and measurement results are discussed. The shared cache proposed in this paper has been determined to be quite area-efficient without the significant loss of throughput and scalability. It has been implemented as a plug-in unit for TICOM, a prevalent commercial multiprocessor system.

A trace-driven simulation methodology

This paper presents a simulation methodology for evaluating the performance of CISC computers. The method is called Message Flow Technique (MFT). MFT has several advantages over Instruction Flow Technique (IFT) we presented in [1]. The proposed methodology is applied to a single and two-level cache CISC system using 80486 SX as a case study. It was found that with a single-level on-chip cache of size 8K, the performance of the system is considerably limited by the service time of BIU(Bus Interface Unit). The average service time of BIU, per instruction, was found to be around 1.0135 microseconds for our Modified Gibson Mix (MGM). With a second-level external cache of sizes 16K, 32K, 64K, and 128K the average performance improvements were found to be 1.4%, 18.6%, 39% and 53% respectively. The methodology presented here is an efficient and easy to use tool that could help performance analysts in evaluating computer systems.

A methodology for evaluating the performance of CISC computer systems under single and two-level cache environments

This paper presents a simulation methodology for evaluating the performance of CISC computers. The method is called Message Flow Technique (MFT). MFT has several advantages over Instruction Flow Technique (IFT) we presented in [1]. The proposed methodology is applied to a single and two-level cache CISC system using 80486 SX as a case study. It was found that with a single-level on-chip cache of size 8KB, the performance of the system is considerably limited by the service time of BIU (Bus Interface Unit). The average service time of BIU, per instruction, was found to be around 1.0135 microseconds for our Modified Gibson Mix (MGM). With a second-level external cache of sizes 16KB, 32KB, 64KB, and 128KB the average performance improvements were found to be 1.4%, 18.6%, 39% and 53% respectively. The methodology presented here is an efficient and easy to use tool that could help performance analysts in evaluating computer systems.

A low-cost graphics and multimedia workstation chip set

With just three VLSI parts, Hewlett-Packard's latest workstation class lets designers optimize performance and cost at the system level. Its Hummingbird microprocessor features two-way superscalar execution incorporating two integer units, a floating-point unit, a 1-Kbyte internal instruction cache, an integrated external cache controller, an integrated memory and I/O controller, plus enhancements for little-endian and multimedia applications. Its Artist graphics controller integrates a graphical user interface accelerator, a frame buffer controller, and a video controller on a single chip.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Memory-fast computer memories

The search for new dynamic RAM (DRAM) technologies to reduce memory access time and so unleash computer performance is discussed. The typical memory hierarchy of internal registers, cache, main memory, and mass storage is described. DRAM technologies that aim at simplifying this hierarchy by speeding up main memory to the point where the need for a separate, external cache is moot are examined. >