External Bus Research Articles

Software waiting loop length control: Technique for reduction of radiated EMI from microprocessor-based PWM drive system

A novel technique, referred to as software waiting loop length control (SWLLC), for reducing the radiated EMI from microprocessor-based PWM drive systems is presented. By randomly changing the length of the software waiting loops, the energy concentrated into discrete bands by the action of periodic signals on the external and internal buses of the microprocessor system can be spread across a larger frequency range. Using this technique, significant reduction of radiated interference levels has been observed in a typical PWM drive system.

A 500-MHz 4-Mb CMOS pipeline-burst cache SRAM with point-to-point noise reduction coding I/O

A secondary cache SRAM is an indispensable CPU partner in a high-performance system. The main objectives are: 1) pipeline burst operation; 2) 32b 500MHz (2GB/s) I/Os, and 3) point-to-point communication with a CPU, as well as shortened latency and reduced noise and power caused by high-speed, high-bandwidth I/O operation. A pre-fetched pipeline scheme enables the cycle time for an internal memory core (I-cycle) to be extended by N times that of an external bus cycle (E-cycle). This is modified to an SRAM to achieve both 4b pipeline-burst cache operation and 500MHz I/O frequency. In this case, I-cycle time of 8ns is four times E-cycle time (2ns).

STiNG

"STiNG" is a Cache Coherent Non-Uniform Memory Access (CC-NUMA) Multiprocessor designed and built by Sequent Computer Systems, Inc. It combines four processor Symmetric Multi-processor (SMP) nodes (called Quads), using a Scalable Coherent Interface (SCI) based coherent interconnect. The Quads are based on the Intel P6 processor and the external bus it defines. In addition to 4 P6 processors, each Quad may contain up to 4 GBytes of system memory, 2 Peripheral Component Interface (PCI) busses for I/O, and a Lynx board. The Lynx board provides the datapath to the SCI-based interconnect and ensures system-wide cache coherency. STiNG is one of the first commercial CC-NUMA systems to be built. This paper describes the motivation for building STiNG as well as its architecture and implementation. In addition, performance analysis is provided for On-Line Transaction Processing (OLTP) and Decision Support System (DSS) workloads. Finally, the status of the current implementation is reviewed.

Experiences on using a workstation cluster to implement a real-time digital transient network analyzer

A feasibility study of a real-time digital simulator, capable of analyzing electrical transients in generation, transmission and distribution systems, led to the identification of a cluster of high-end workstations, interconnected by means of a high-performance communication and I/O system, as the most promising architectural solution. To evaluate teh possibility of matching the real-time requirements of such a simulator, a testbed has been set up, constituted by two workstations sharing an external VME bus through suitable bus adapters. The adequacy of the envisioned architecture for the considered problem was assessed and the main areas requiring the design of dedicated devices identified according to several experiments on processing power and communication times described in the paper. A working simulator for simple test cases has also been set up and benchmarked.

Comptage, téléreport, télérelevé et interface clientèle communicante

. Energy metering is progressing from the concept of remote reporting (i.e. data transfer from the meter outward) toward the concept of direct customer interfacing. . EDF studies on remote reporting concluded with development of the Euridis bus, which provides a magnetic link between meter and terminal. This system can be extended for use with other utility fluids, provided an external bus power source is available. . EDF's experience in automatic meter reading in the domestic sector is limited to its work on direct customer interfacing, though meters are read automatically for some special-tariff customers. To avoid monopolizing the telephone line, other communication methods (carrier currents, radio, etc.) could be used.

An asynchronous data acquisition ASIC with a data-push architecture

We report on a digital circuit for data acquisition that has been developed for high energy physics applications. Its function is to receive asynchronous voltage pulses, time-stamp them individually and transmit them sequentially on an external bus. A 16-channel design has been fabricated as an application specific integrated circuit (ASIC) using the HP 1.2 μm double-metal, single-polysilicon process. Test results made on prototype chips indicate that the circuit performs within specifications for an operating clock frequency of 25 MHz and a working environment temperature of 0°C to 40°C.

A unified architectural tradeoff methodology

We present a unified approach to assess the trade-off of architecture techniques that affect mean memory access time. The architectural features we consider include cache hit ratio, processor stalling features, line size, memory cycle time, the external data bus width of a processor, pipelined memory system, and read by-passing write buffers. We demonstrate how each of these features can be traded off to achieve the desired performance. The performance of an architecture feature is quantified in terms of cache hit ratio based on the equivalence of mean memory delay time. This paper investigates the implication of architectural tradeoffs on the pin count, memory system design, and on-chip cache area for microprocessor systems.

Organization of the Motorola 88110 superscalar RISC microprocessor

Motorola's second-generation RISC microprocessor, which uses advanced techniques for exploiting instruction-level parallelism, including superscalar instruction issue, our-of-order instruction completion, speculative execution, dynamic instruction rescheduling, and two parallel, high-bandwidth, on-chip caches, is discussed. The microprocessor was designed to serve as the central processor in low-cost personal computers and workstations, and support demanding graphics and digital signal processing applications. The 88110's instruction set architecture, instruction sequencer, register files, execution units, address translation facilities, caches, and external bus interface are described. >

Modeling digital circuits for troubleshooting

Existing methods for model-based troubleshooting have not previously scaled up to deal with complex digital circuits, in part because traditional circuit models do not represent aspects of the device that troubleshooters consider important. An instruction level simulation of a microprocessor explicitly represents the logic levels present on its external bus at every clock edge, but not the fact that during normal operation those bus signals should be very active. A schematic may represent the connectivity of field replaceable components, but does not show how their combined behavior implements the intentions of the designer. The specifications of a component rarely say how it is likely to fail. This suggests basing troubleshooting on a specialized circuit model that emphasizes such aspects. Although it is beyond current technology to derive such models from circuit schematics automatically, this work shows that these models can make the trouble-shooting of complex circuits feasible. This paper describes an implemented program for troubleshooting complex digital circuits, using a representation that makes explicit their behavior at a high level of temporal abstraction, their physical and functional organization, and the common ways that their components fail.

The latch bus driver system

A large and growing fraction of the power in modern VSLI chips is dissipated by the drivers of external bus lines. A novel bus system drastically reduces power and noise by using a central driver chip which periodically attempts to charge and to discharge the bus lines. The transmitters of the selected chip inhibit the charge process for the establishment of a 'low' signal. The central driver latches the signal state after the inhibit phase. The authors explain the inhibit driver principle in comparison with the usual push-pull system, present the timing characteristics, and report on the design and the measured results of an experimental central driver chip in full-custom CMOS.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Inertial-Dissipation Air-Sea Flux Measurements: A Prototype System Using Realtime Spectral Computations

A prototype system for the measurement and computation of air–sea fluxes in realtime was tested in the Humidity Exchange Over the Sea (HEXOS) main experiment, HEXMAX. The system used a sonic anemometer/thermometer for wind speed, surface stress and sensible heat flux measurements and a Lyman-α fast hygrometer for latent beat flux. A small desktop computer combining both fast analog to digital (A/D) capabilities, external bus (IEEE-488) operation of a slow voltmeter/scanner unit, and a plug-in board for computation of turbulence spectra by Fast Fourier Transform was used for acquisition of 17 channels of data. At the end of a ten-minute averaging period, air–sea fluxes were computed from the velocity, temperature, and humidity variance spectra using the inertial-dissipation method. A second computer and data acquisition system was used for simultaneous computations of covariance fluxes for comparison. The sonic anemometer/thermometer proved to be well suited for this application: the velocity data appear to be of good quality and the temperature data wore unaffected by salt contamination. We suggest an infrared hygrometer as a replacement for the Lyman-α. For the six week HEXMAX period the inertial-dissipation flux estimates agreed with covariances computed from the same instruments with a typical average root-mean-square difference of ± 10% for stress and ± 25% for sensible and latent heat.

The 68040 processor. 2. Memory design and chip

For pt.1 see ibid., February (1990). The memory subsystem, the external bus, chip and board testing, and design-verification methods for the 68040, a third-generation, full-32-bit microprocessor in the Motorola 68000 family, are discussed. The internal caches and memory management are examined at length. The external bus protocol, arbitration, snooping, and timing specifications are addressed. The MOVE16 instruction, which moves a cache line from one address (which may reside in the data cache) to another address outside the cache is described. User testing, based on dedicated test logic that is fully compliant with the IEEE 1149.1 standard, and factory testing, for which the processor employs structured design techniques for random logic and special test modes for embedded arrays, are examined. The use of top-down design and a hierarchical method of design verification is discussed.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A High Performance Single Chip LSI for Error Correction of Optical Disk Memory

A Single chip error correcting LSI of Reed-Solomon long minimum distance code (d=<17) has been developed for optical disk memory. High speed decoding of error correcting code has been realized by internal multi-processing architecture, in which interleaving, syndrome calculation, error correction, and data inter facing with the host computer are processed simultaneously. In addition to the adoption of a multiprocessor configuration, high speed hardware for error correction and detection is employed to realize “on the fly” decoding which decodes any decodable errors of a code of length n=20 distance d=<17 within 600 clocks. Euclidian algorithm is applied for correction of errors, and unknown error locations, besides, a newly developed recursive algorithm is applied to erasure correction if error locations are identified beforehand. This contributes to both high speed decoding and hardware reduction. Check words and other parameters are selectable and these are set up in registers via an external micro-controller bus. A Small Computer System Interface(SCSI-2) has been provided as the system interface.

Digital Effects Integration in a Video Switcher

Enhancements can be made to the control panel and the internal architecture of a video production switcher to simplify operation of a digital effects device from the switcher panel. Presently, inputs to digital effects devices are typically selected from auxiliary or external routing buses, and the output of the digital effects enters the switcher as an input. If a key channel is used and transformed with the digital effects, key-processing circuitry with additional key input routing is required. The output of the digital effects device still needs to be combined with other video sources into the final output. The ability to select and route sources, generate key signals, and mix output video are common to the video production switcher. With some additional hardware and control enhancements to the switcher, a digital effects device can easily be controlled with an efficiency of hardware.

4677586 Microcomputer device having test mode substituting external ram for internal RAM

A digital data processing system employs a single-chip microcomputer device having separate on-chip program and data memory, executing instructions in a single machine state. An external program address bus allows off-chip program fetch in a memory expansion mode, with the opcode returned by an external data bus, or all program storage can be off-chip in a system emulator mode. The ALU and accumulator have 32-bit data paths, while the busses are 16-bit. Various test modes are permitted; for example, the internal program ROM may be read out on the data bus, one opcode at a time, for test purposes without executing the opcodes. Alternatively, the internal data RAM may be disabled and an external RAM used, for which a three-state or four-state instruction execution sequence is established instead of one per state to allow an operand to be transferred in on the data bus and high and low words of the accumulator transferred out; this node is very useful for checking ALU operations not otherwise accessible off-chip.

A second-generation digital signal processor

The architecture, implementation, and applications of the TMS32020, a second-generation VLSI digital signal processor, are described. The processor has many special features which provide a significant advance over previous VLSI digital signal processors. Its multiprocessor capabilities further distinguish it, allowing for much more flexibility in overall system design. The architecture of the device allows a dual bus structure to be maintained on-chip, while external bus hardware requirements are minimized via the multiplexing of these buses externally. Some of the notable features incorporated onto the device include two large on-chip RAM blocks, large external program/data address spaces, single-cycle multiply/accumulate instructions, hardware and instructions for efficient memory management, and a versatile multiprocessor interface.

A second-generation digital signal processor

The architecture, implementation, and applications of the TMS32020, a second-generation VLSI digital signal processor, are described. It has many special features which provide a significant advance over previous VLSI digital signal processors. Its multiprocessor capabilities further distinguish it, allowing for much more flexibility in overall system design. The architecture of the device allows a dual bus structure to be maintained on-chip, while external bus hardware requirements are minimized via the multiplixing of these buses externally. Some of the notable features incorporated onto the device include two large on-chip RAM blocks, large external program/data address spaces, single-cycle multiply/ accumulate instructions, hardware and instructions for efficient memory management, and a versatile multiprocessor interface.

Improving the Extended Ward Equivalent for On-Line Static Security Analysis

Abstract This paper describes and analyses a new version of the Extended Ward Equivalent (EW). In this version, denominated One - Step Extended Ward (OSEW), a new algorithm for obtaining the equivalent parameters (shunts and lines) is utilized. The OSEW method calculates the equivalent parameters by means of one single triangular reduction (Gaussian elimination) of the external buses in the nodal admittance matrix Y bus of the boundary and external buses. The main contribution is the reduction of the computing effort to obtain the equivalent parameters. Aspects related to external shunt representation and accuracy of the equivalent model are also discussed. Numerical tests are presented and analysed.

4482953 Computer with console addressable PLA storing control microcode and microinstructions for self-test of internal registers and ALU

In a microprocessor having independent address and data paths and other pipeline architecture features, a control unit utilizes a PLA which stores microcoded instruction sequences. These sequences permit an operator at a console to read data from and write data to all the internal registers, any external memory location or the program counter. In addition, the PLA contains microcode which enables programs in external memory to be loaded from any location in memory and run by command from the console as well as to enable the operator to halt user program execution, read the pertinent internal registers, and then continue program execution such that single step execution for debug purposes is possible. The PLA also contains self-test microcode which permits the console operator to start a self-test sequence of instructions issued from the PLA which will test the functionality of the majority of the registers, multiplexers, and data paths in the machine as well as test the majority of the arithmetic and logical functions which can be carried out by arithmetic and logic unit of the microprocessor. The control unit also contains logic to support an external bus arbiter for use of the computer in a multiprocessor network with a common bus.

Evolution of television receivers from analog to digital

Digital circuits were introduced into TV receivers for control purposes, for example, remote control, and later for internal integrated circuit (IC) control via a data bus within the receiver. Recently, an external bus system was proposed that allows digital control of a variety of in-home consumer equipment. There are two reasons for extending the digitization of the receiver to the video signal processing in the receiver. Firstly, digitizing existing functions will reduce the cost and increase the reliability, and secondly, new functions will enable extra features and better picture quality to be obtained. The key components are complex, fast VLSI ICs and especially for the new features: the integrated digital field store. Examples of both approaches are given and the choice of sampling frequency, important for both approaches, is discussed. Teletext is a service already popular in many countries. Its viability is due to the early availability of complex digital ICs at economic prices. A review is given of the operation of teletext in the TV receiver and a description of the various system standards is attempted. The future use of time-multiplexed color-TV transmission systems, such as the C-MAC and D2-MAC/Packet systems (MAC = Multiplexed Analog Components), is considered. Decoders for these systems will probably use digital methods. Moreover, when digital field storage and processing are introduced in the TV receiver, interesting extensions to the MAC approach will become possible.