Extended Counting Research Articles

A 107.6 dB-DR Three-Step Incremental ADC for Motion-Tolerate Biopotential Signals Recording.

This article describes a power-efficient, high dynamic range (DR) incremental ADC (IADC) for wearable biopotential signals recording, where DC and low-frequency disturbances such as electrode offset, 50/60 Hz interference and motion artifact must be tolerated. To achieve a wide DR, the IADC performs a three-step conversion by combining zoom-SAR and extended counting (EC) on top of a second-order incremental delta-sigma modulator (ΔΣM). The hybrid architecture notably reduces the oversampling ratio (OSR) with respect to conventional incremental ΔΣMs, while using the EC further improves the Signal-to-Noise-and-Distortion Ratio (SNDR) by 7.4 to 25.6 dB. Fabricated in a 0.18-μm CMOS technology, the IADC achieves 107.6-dB DR, 104.9-dB peak SNR, and 99.3-dB peak SNDR at 2 kS/s while dissipating 130 μW from 1.8-V (analog) / 1.2-V (digital) supply. This translates to a highly competitive FoMDR of 176.5 dB. The high-DR IADC reduces the gain of the preceding instrumentation amplifier (IA) such that significant DC and low-frequency disturbances can be tolerated. The advantages of high DR have been demonstrated by wearable Electrocardiography (ECG) and Electroencephalography (EEG) recordings under motion artifact.

A multichannel readout integrated circuit with column-wise pseudo differential extended counting ADCs for an uncooled infrared focal plane array based on silicon diodes

This paper presents a multichannel readout integrated circuit (ROIC) with column-wise extended counting (EC) ADCs, which is targeted toward silicon diode uncooled infrared focal plane arrays (IRFPA). The column ADC features a direct connection with the detectors without extra pre-amplifiers. The ROIC incorporates 9-bit folding integration ADCs for coarse conversion and 5-bit single-slope ADCs for fine conversion. A pseudo-differential architecture combined with blind pixels is adopted to cancel even-order distortion. To improve linearity without increasing power consumption, a ping-pong integrator is adopted to reduce reset time by charging alternatively. A prototype consisting of 32 columns is fabricated in 180 nm 1P5M CMOS process for verification. The power consumption of one column is 50.5 μW. According to the measurement results, the input-referred noise is 1.21 LSB (2.36 μVrms), and the peak SNR is 82.5 dB. The INL and DNL are +2.43/-2.21 LSB and +0.33/-0.31 LSB, separately.

A Low Power ROIC with Extended Counting ADC Based on Circuit Noise Analysis for Sensor Arrays in IoT System

As the Internet of Things (IoT) is rapidly integrated into our daily life, the demand for high performance readout integrated circuit (ROIC) design for sensor arrays is boosting. This paper presents a low power, low noise ROIC with 14-bit column-parallel extended counting (EC) ADCs for sensor arrays targeting the IoT applications. The proposed EC-ADC adopts a pseudodifferential architecture to cancel even-order nonlinearity. The analog front-end is a G m stage, which employs a current-reuse topology to boost the transconductance and reduce noise without increasing current consumption. The upper 9-bit conversion is implemented during integration, and the residual voltage is converted by a 5-bit single-slope (SS) ADC, where the comparator is reused. A ping-pong integrator is proposed to reduce the reset time and improve linearity, eliminating the power-hungry CTIA structure. The ROIC is designed in 0.18 μm 1P5M CMOS process for a 640 × 480 sensor array. Power consumption of the ROIC is 33 mW, and each column ADC consumes 40.1 μW. Simulation results show an input-referred noise of 0.89 LSB (1.74 μVrms), an integral nonlinearity of +0.92/-0.70 LSB, an ENOB of 12.87 bits, and a FoM of 131.1 fJ/step.

Pipelined extended‐counting for 3D‐stacked CMOS image sensors

A novel multi-stage pipelined extended-counting (EC) for 3D-stacked CMOS image sensors is presented, which combines the benefits of a pipelined ADC, a first-order ADC and the EC principle in order to simultaneously achieve a high resolution and a high frame rate for 3D-stacked imagers. By assigning each stage of the pipeline to a sub-column of pixels while choosing another input stage of the pipeline when a sub-column has been read out, discontinuous rolling shutter artefacts like chopped images can be eliminated and frame rates up to 340 fps can be achieved for imagers with 8 K resolution.

A 102.2-dB, 181.1-dB FoM Extended Counting Analog-to-Digital Converter With Capacitor Scaling

Sensor interfaces demand ever-increasing energy efficiency from analog-to-digital converters (ADCs). For sensors requiring a wide dynamic range (DR) (>12 bit), the incremental ADC (IADC) is becoming a popular choice. In this article, the design of an energy-efficient IADC with a 16-bit signal-to-noise and distortion ratio (SNDR) and 17-bit DR is described. The IADC implements a novel capacitor scaling technique, which reduces power consumption in the critical first operational transconductance amplifier (OTA) by up to 37%. The new technique can be combined with the extended counting (EC) scheme utilizing an in-loop 4-bit asynchronous successive approximation register (SAR) (ASAR) ADC. Using a three-phase operation, this IADC architecture further reduces the power while enabling wider signal bandwidth with a much lower oversampling ratio (OSR). Silicon measurements in a 0.18- $\mu $ m CMOS process show the IADC achieved a DR of 102.2 dB, within a bandwidth of 2.04 kHz, with power consumption of about $25~\mu $ W, leading to a state-of-the-art Schreier figure-of-merit (FoM) of 181.1 dB.

A Triple-Mode Performance-Optimized Reconfigurable Incremental ADC for Smart Sensor Applications

This paper proposes a triple-mode discrete-time incremental analog-to-digital converter (IADC) employing successive approximation register (SAR)-based zooming and extended counting (EC) schemes to achieve programmable trade-off capability of resolution and power consumption in various smart sensor applications. It mainly consists of an incremental delta–sigma modulator and the proposed SAR-EC sub-ADC for alternate operation of the coarse SAR conversion and EC. They can be reconfigured to operate separately depending on the application requirements. The SAR-based zooming structure allows the IADC to have better linearity and resolution, and additional activation of the EC function gives the further resolution. During this reconfigurable conversion process, pipelined reusing operation of sub-blocks reduces the silicon area and the number of cycles for target resolutions. A prototype ADC is fabricated in a 180-nm CMOS process, and its triple-mode operation of high-resolution, medium-resolution, and low-power is experimentally verified to achieve 116.1-, 109.4-, and 73.3-dB dynamic ranges, consuming 1.60, 1.26, and 0.39 mW, respectively.