Architecture Exploration Research Articles

A framework to generate domain-specific manycore architectures from dataflow programs

In the last 15 years we have seen, as a response to power and thermal limits for current chip technologies, an explosion in the use of multiple and even many computer cores on a single chip. But now, to further improve performance and energy efficiency, when there are potentially hundreds of computing cores on a chip, we see a need for a specialization of individual cores and the development of heterogeneous manycore computer architectures.However, developing such heterogeneous architectures is a significant challenge. Therefore, we propose a design method to generate domain specific manycore architectures based on RISC-V instruction set architecture and automate the main steps of this method with software tools. The design method allows generation of manycore architectures with different configurations including core augmentation through instruction extensions and custom accelerators. The method starts from developing applications in a high-level dataflow language and ends by generating synthesizable Verilog code and cycle accurate emulator for the generated architecture.We evaluate the design method and the software tools by generating several architectures specialized for two different applications and measure their performance and hardware resource usages. Our results show that the design method can be used to generate specialized manycore architectures targeting applications from different domains. The specialized architectures show at least 3 to 4 times better performance than the general purpose counterparts. In certain cases, replacing general purpose components with specialized components saves hardware resources. Automating the method increases the speed of architecture development and facilitates the design space exploration of manycore architectures.

Design Space Exploration of Hardware Spiking Neurons for Embedded Artificial Intelligence

Machine learning is yielding unprecedented interest in research and industry, due to recent success in many applied contexts such as image classification and object recognition. However, the deployment of these systems requires huge computing capabilities, thus making them unsuitable for embedded systems. To deal with this limitation, many researchers are investigating brain-inspired computing, which would be a perfect alternative to the conventional Von Neumann architecture based computers (CPU/GPU) that meet the requirements for computing performance, but not for energy-efficiency. Therefore, neuromorphic hardware circuits that are adaptable for both parallel and distributed computations need to be designed. In this paper, we focus on Spiking Neural Networks (SNNs) with a comprehensive study of neural coding methods and hardware exploration. In this context, we propose a framework for neuromorphic hardware design space exploration, which allows to define a suitable architecture based on application-specific constraints and starting from a wide variety of possible architectural choices. For this framework, we have developed a behavioral level simulator for neuromorphic hardware architectural exploration named NAXT. Moreover, we propose modified versions of the standard Rate Coding technique to make trade-offs with the Time Coding paradigm, which is characterized by the low number of spikes propagating in the network. Thus, we are able to reduce the number of spikes while keeping the same neuron’s model, which results in an SNN with fewer events to process. By doing so, we seek to reduce the amount of power consumed by the hardware. Furthermore, we present three neuromorphic hardware architectures in order to quantitatively study the implementation of SNNs. One of these architectures integrates a novel hybrid structure: a highly-parallel computation core for most solicited layers, and time-multiplexed computation units for deeper layers. These architectures are derived from a novel funnel-like Design Space Exploration framework for neuromorphic hardware.

Ablate, Variate, and Contemplate: Visual Analytics for Discovering Neural Architectures.

The performance of deep learning models is dependent on the precise configuration of many layers and parameters. However, there are currently few systematic guidelines for how to configure a successful model. This means model builders often have to experiment with different configurations by manually programming different architectures (which is tedious and time consuming) or rely on purely automated approaches to generate and train the architectures (which is expensive). In this paper, we present Rapid Exploration of Model Architectures and Parameters, or REMAP, a visual analytics tool that allows a model builder to discover a deep learning model quickly via exploration and rapid experimentation of neural network architectures. In REMAP, the user explores the large and complex parameter space for neural network architectures using a combination of global inspection and local experimentation. Through a visual overview of a set of models, the user identifies interesting clusters of architectures. Based on their findings, the user can run ablation and variation experiments to identify the effects of adding, removing, or replacing layers in a given architecture and generate new models accordingly. They can also handcraft new models using a simple graphical interface. As a result, a model builder can build deep learning models quickly, efficiently, and without manual programming. We inform the design of REMAP through a design study with four deep learning model builders. Through a use case, we demonstrate that REMAP allows users to discover performant neural network architectures efficiently using visual exploration and user-defined semi-automated searches through the model space.

Electrochemical Interfacial Phenomena Under Microgravity

Electrochemical Processing under extreme conditions like reduced gravity, strong cosmic ray irradiation and magnetic fields should be well designed in the era of Gateway after ISS. JAXA’s “HAYABUSA” satellite project of Successful Sample Return from Asteroid “Itokawa” was achieved by newly developed Ion Engine and well controlled life-cycling of LIB. Now, HAYABUSA 2” is approaching to “Ryugu” asteroid by Pin-point Landing supported with Robotics & AI Image Learning (Self Controlled Driving). Moreover, Manned Rover operation plan toward Lunar Hydrogen Energy System in 2029 was announced by JAXA-TOYOTA last March. CO2 Reduction for Life Supporting System must be reasonably combined. HERACLES (Human Enhanced Robotic Architecture for Lunar Exploration and Science) and MMX (Martian Moons eXploration) shall be further planned. High Temp. Molten Oxide Electrolysis with Inert Anode are engaged as ISRU. One of the fundamental subjects common in designing the energy conversion and storage devices in space engineering is to well control the electrochemical interfacial phenomena among three Gas/Liquid(Aqueous or Molten Oxide)/Solid(Metal or Solid Oxide) phases under reduced gravity and magnetic field. Experimental studies in Drop Tower, a parabolic flight and University Laboratory(1-G) to focus the wettability effects on these phenomena were reported over last 30 years1-10). O2 bubble evolution behavior on Pt electrode modified by thiol SAM was monitored during alkaline water electrolysis under μ-G with a high speed video camera. Single bubble measurements on microwire electrode was additionally engaged. The latter revealed three-step processes involving (1) the nucleation and formation of supersaturated layer of dissolved O2 gas followed by (2) a rapid growth depending on the gas diffusion process and finally (3)a stable growth where its growth rate is dominated by bubble configuration depending on the contact angle. Moreover, the correlation of multiple gas bubble observation with electrochemical data and surface coverage on the plate electrode reinforces the importance of wettability in determining two phase flow motion and energy consumption during electrolysis. The degree of supersaturation of dissolved gas on hydrophilic/hydrophobic electrode surface in aqueous solution and molten salt are also studies. They are compared to 1-G experiments in order to newly enlighten the matured gas electrode concepts. “Electrochemical Laboratory in ISS & Gateway” should be constructed with Space Agencies.

Towards an authentic path: Structuralism and architecture in socialist Yugoslavia

The breakup between socialist Yugoslavia and the Soviet Union in 1948 paved the way for radical socio-political reforms as well as a new cultural model that would justify a newly invented Yugoslav socialist Sonderweg. In this context, Structuralism became a key vehicle for implementing the social and cultural values of the newly invented socialist self-management ideology. Structuralism helped shape the new culture via different fields and cultural approaches. This paper examines the origins and importance of Structuralism in architecture in the ideological and political context of Yugoslav socialism. As an avant-garde movement, Structuralism consequentially contributed to the critique of the then predominant functionalist paradigm of high modernism, resulting in a new direction that emphasised aestheticisation, a formal and semiotic approach, and the establishment of universal and archetypal values ostensibly derived from the exploration of vernacular architecture in Yugoslavia. Starting from the premise that all these values had a major impact on the construction of the mythology of authentic and autochthonous socialism, this paper shows how architectural Structuralism played a key role in shaping social and political authenticity and cultural mediation.

Research of green architecture—take Chinese traditional cave dwellings as an example

Most of people on the Loess Plateau live in cave dwellings. Cave dwelling, as a traditional residential building in China, demonstrates the wisdom of traditional Chinese residents. Cave dwelling, which is mainly made of earth, is gradually built by the people of the Loess Plateau by integrating natural environment and their unique natural resources. To a certain extent, cave dwelling also embodies the philosophy of sustainable development, coexisting harmoniously with nature, conforming to nature and cultivating nature. The research on the design of traditional Chinese cave dwellings has played a certain role in the exploration of green architecture in the future. In this paper studies the traditional Chinese dwellings - cave dwellings comprehensively, describes from many perspectives like the historical background, practical role and long-term impact, which is of great practical significance.

QUOTA: The Quantile Option Architecture for Reinforcement Learning

In this paper, we propose the Quantile Option Architecture (QUOTA) for exploration based on recent advances in distributional reinforcement learning (RL). In QUOTA, decision making is based on quantiles of a value distribution, not only the mean. QUOTA provides a new dimension for exploration via making use of both optimism and pessimism of a value distribution. We demonstrate the performance advantage of QUOTA in both challenging video games and physical robot simulators.

Chronic recording and electrochemical performance of amorphous silicon carbide-coated Utah electrode arrays implanted in rat motor cortex

Objective. Clinical applications of implantable microelectrode arrays are currently limited by device failure due to, in part, mechanical and electrochemical failure modes. To overcome this challenge, there is significant research interest in the exploration of novel array architectures and encapsulation materials. Amorphous silicon carbide (a-SiC) is biocompatible and corrosion resistant, and has recently been employed as a coating on biomedical devices including planar microelectrode arrays. However, to date, the three-dimensional Utah electrode array (UEA) is the only array architecture which has been approved by the food and drug administration (FDA) for long-term human trials. Approach. Here, we demonstrate, for the first time, that UEAs can be fabricated with a-SiC encapsulation and sputtered iridium oxide film (SIROF) electrode coatings, and that such arrays are capable of single-unit recordings over a 30 week implantation period in rat motor cortex. Over the same period, we carried out electrochemical measurements, including voltage transients, cyclic voltammetry, and electrochemical impedance spectroscopy (EIS), to evaluate potential failure modes. Furthermore, we evaluated chronic foreign body response via fluorescence immunohistochemistry following device explantation. Main results. During the indwelling period, we observed a reduction in active electrode yield percentage from 94.6 ± 5.4 (week 1) to 16.4 ± 11.5% (week 30). While the average active electrode yield showed a steady reduction, it is noteworthy that 3 out of 8 UEAs recorded greater than 60% active electrode yield at all times through 24 weeks and 1 out of 8 UEAs recorded greater than 60% active electrode yield at all times through the whole implantation period. Significance. In total, these findings further suggest that a-SiC may serve as a mechanically and electrochemically stable device encapsulation alternative to polymeric coatings such as Parylene-C.

Dynamic Power Management for Neuromorphic Many-Core Systems

This paper presents a dynamic power management architecture for neuromorphic many-core systems, such as SpiNNaker. A fast dynamic voltage and frequency scaling (DVFS) technique is presented which allows the processing elements (PEs) to change their supply voltage and clock frequency individually and autonomously within less than 100 ns. This is employed by the neuromorphic simulation software flow, which defines the performance level (PL) of the PE based on the actual workload within each simulation cycle. A test chip in 28-nm SLP CMOS technology has been implemented. It includes four PEs which can be scaled from 0.7 to 1.0 V with frequencies from 125 to 500 MHz at three distinct PLs. By measurement of three neuromorphic benchmarks, it is shown that the total PE power consumption can be reduced by 75%, with 80% baseline power reduction and a 50% reduction of energy per neuron and synapse computation, all while maintaining temporary peak system performance to achieve biological real-time operation of the system. A numerical model of this power management model is derived which allows DVFS architecture exploration for neuromorphics. The proposed technique is to be used for the second-generation SpiNNaker neuromorphic many-core system.

Comprehensive evaluation of deep learning architectures for prediction of DNA/RNA sequence binding specificities.

MotivationDeep learning architectures have recently demonstrated their power in predicting DNA- and RNA-binding specificity. Existing methods fall into three classes: Some are based on convolutional neural networks (CNNs), others use recurrent neural networks (RNNs) and others rely on hybrid architectures combining CNNs and RNNs. However, based on existing studies the relative merit of the various architectures remains unclear.ResultsIn this study we present a systematic exploration of deep learning architectures for predicting DNA- and RNA-binding specificity. For this purpose, we present deepRAM, an end-to-end deep learning tool that provides an implementation of a wide selection of architectures; its fully automatic model selection procedure allows us to perform a fair and unbiased comparison of deep learning architectures. We find that deeper more complex architectures provide a clear advantage with sufficient training data, and that hybrid CNN/RNN architectures outperform other methods in terms of accuracy. Our work provides guidelines that can assist the practitioner in choosing an appropriate network architecture, and provides insight on the difference between the models learned by convolutional and recurrent networks. In particular, we find that although recurrent networks improve model accuracy, this comes at the expense of a loss in the interpretability of the features learned by the model.Availability and implementationThe source code for deepRAM is available at https://github.com/MedChaabane/deepRAM.Supplementary information Supplementary data are available at Bioinformatics online.

Sequential exploration in the Iowa gambling task: Validation of a new computational model in a large dataset of young and old healthy participants.

The Iowa Gambling Task (IGT) is one of the most common paradigms used to assess decision-making and executive functioning in neurological and psychiatric disorders. Several reinforcement-learning (RL) models were recently proposed to refine the qualitative and quantitative inferences that can be made about these processes based on IGT data. Yet, these models do not account for the complex exploratory patterns which characterize participants’ behavior in the task. Using a dataset of more than 500 subjects, we demonstrate the existence of sequential exploration in the IGT and we describe a new computational architecture disentangling exploitation, random exploration and sequential exploration in this large population of participants. The new Value plus Sequential Exploration (VSE) architecture provided a better fit than previous models. Parameter recovery, model recovery and simulation analyses confirmed the superiority of the VSE scheme. Furthermore, using the VSE model, we confirmed the existence of a significant reduction in directed exploration across lifespan in the IGT, as previously reported with other paradigms. Finally, we provide a user-friendly toolbox enabling researchers to easily and flexibly fit computational models on the IGT data, hence promoting reanalysis of the numerous datasets acquired in various populations of patients and contributing to the development of computational psychiatry.

Synchronous Circuit Design With Beyond-CMOS Magnetoelectric Spin–Orbit Devices Toward 100-mV Logic

The supply voltage scaling has become increasingly challenging in the advanced CMOS technology due to the threshold voltage requirement for transistor OFF leakage, limiting the system energy efficiency. Spintronic logic utilizes the physical quantity of magnetization or spin as a computation variable, offering new design paradigms in terms of ultralow voltage operation and nonvolatility, but suffering from switching inefficiency of the charge-to-spin conversion. The magnetoelectric spin–orbit (MESO) device has been proposed as a new alternative logic device candidate to solve these issues by magnetoelectric transduction using a novel multiferroic oxide [both ferroelectric (FE) and antiferromagnetic], a ferromagnet and a spin injection layer. It enables a path toward 10–100 $\times $ switching energy reduction compared to CMOS inverter in 2018 node, due to the device and material innovations of a novel switching mechanism. In this paper, in order to build a MESO logic family for new circuit and architecture exploration, we propose for the first time the fundamental building blocks such as MESO sequential and combinatorial circuits for the synchronous logic operation. We employ a transistor sharing and a novel multiphase clocking scheme to address the circuit design issues such as clock control, directionality of state propagation, and power gating and enable the design exploration for MESO digital logic. Based on the proposed circuit techniques, we demonstrate these MESO logic functions operating at a supply voltage of 100 mV and a clock period of 1.2 ns with 320-ac FE polarization through the circuit simulations.

Accurate prediction of boundaries of high resolution topologically associated domains (TADs) in fruit flies using deep learning.

Genomes are organized into self-interacting chromatin regions called topologically associated domains (TADs). A significant number of TAD boundaries are shared across multiple cell types and conserved across species. Disruption of TAD boundaries may affect the expression of nearby genes and could lead to several diseases. Even though detection of TAD boundaries is important and useful, there are experimental challenges in obtaining high resolution TAD locations. Here, we present computational prediction of TAD boundaries from high resolution Hi-C data in fruit flies. By extensive exploration and testing of several deep learning model architectures with hyperparameter optimization, we show that a unique deep learning model consisting of three convolution layers followed by a long short-term-memory layer achieves an accuracy of 96%. This outperforms feature-based models’ accuracy of 91% and an existing method's accuracy of 73–78% based on motif TRAP scores. Our method also detects previously reported motifs such as Beaf-32 that are enriched in TAD boundaries in fruit flies and also several unreported motifs.

Network on Chip for Consumer Electronics Devices: An Architectural and Performance Exploration of Synchronous and Asynchronous Network-on-Chip-Based Systems

The ever-increasing demand for in-home products, automation, and sharing information over social networks has opened a gateway for consumer electronics (CE) devices. As a result, system on chip (SoC)-based multiprocessor systems are designed to meet the current demand. This article presents the architectural issues of multiprocessor SoCs (MPSoCs) used in CE devices and provides network on chip (NoC)-based multiprocessors as a solution that helps alleviate the performance of CE devices. Asynchronous NoC propounds more throughput and lower latency than synchronous NoC for a specific number of virtual channels (VCs) and cores.

Efficient architectural exploration of TAGE branch predictor for embedded processors

Embedded processors are usually limited by silicon budget and power consumption, and utilizing limited resources to design an accurate branch predictor becomes an urgent issue. In this paper, we conduct design space explorations of TAGE predictor with ultra-small RAM for embedded processors. We first define the design space exploration problem, and then we propose PSO-based exploration framework to explore parameters of TAGE predictor. To conduct explorations with different purposes, we propose a composite metric which integrates prediction accuracy, area, and power consumption.For explorations only considering prediction accuracy, results show that compared with Bi-mode and GShare predictor, parameters explored by our method achieves better performance-area efficiency. For explorations considering the area and power consumption, results show that compared to accuracy-first exploration, area-first exploration achieves better performance-area and performance-power efficiency. In addition, area-first exploration and power-first exploration have similar results. We also study how training traces impact overall performance. Results show that the performance gap between different training traces is small and our method is insensitive to traces selected for exploration.

Optimal Flow Control and Single Split Architecture Exploration for Fluid-Based Thermal Management

High-performance cooling is often necessary for thermal management of high power density systems. However, human intuition and experience may not be adequate to identify optimal thermal management designs as systems increase in size and complexity. This article presents an architecture exploration framework for a class of single-phase cooling systems. This class is specified as architectures with multiple cold plates in series or parallel and a single fluid split and junction. Candidate architectures are represented using labeled rooted tree graphs. Dynamic models are automatically generated from these trees using a graph-based thermal modeling framework. Optimal performance is determined by solving an appropriate fluid flow distribution problem, handling temperature constraints in the presence of exogenous heat loads. Rigorous case studies are performed in simulation, with components subject to heterogeneous heat loads and temperature constraints. Results include optimization of thermal endurance for an enumerated set of 4051 architectures. The framework is also applied to identify cooling system architectures capable of steady-state operation under a given loading.

An intelligent design method for actuation system architecture optimization for more electrical aircraft

The design of flight control actuation system is facing major challenge due to the development of more electrical aircraft. The task is to find the combinations of power sources, actuators and computers, which becomes more complex because of the new power sources and actuator types of more electrical aircraft. It is impossible to determine optimal architecture by traditional trial-and-error method within acceptable time. Therefore, the need for new methodology for actuation system architecture design emerges. This study proposes an intelligent design method which has steps of design space exploration of actuation system architectures by constraint satisfaction problem (CSP) method, safety assessment process to exclude unsafety solution, multi-objectives optimization to get Pareto optimal front and comprehensive decision for final architecture via analytic hierarchy process. And the design method is implemented in python and a software platform is developed. Furthermore, within the paper a case study for A350 flight control actuation system is presented to testify the application of this methodology. Compared to the traditional hydraulic architecture, the optimal architecture is more competitive in weight, power and cost. At the same time, the optimal architecture is found in less than 30 minutes among 1075 candidates, which greatly reduces the design cycle. This method deals with the problem in the design of flight control actuation system.

A gem5 trace-driven simulator for fast architecture exploration of OpenMP workloads

Architecture parameter exploration is one of the main analysis that needs to be performed in order to ensure that a multicore system has an optimal set of parameters. The main drawback of current simulation approaches is the long simulation times in order to extract performance metrics while varying a system parameter. Trace-driven simulation approaches allow to abstract selected components of the system under analysis by creating traces during the execution time of an application. This technique reduces the simulation time while keeping the accuracy levels. Even tough trace-driven techniques have proven to be useful, most of them are focused on mono-core systems, and some do not completely capture the behavior of multi-threaded programs. In this regard, we developed a trace-driven simulation approach based on the gem5 framework. This approach is based on a collection phase of the instructions and dependencies of a given application and two extra traces depending on the selected analysis. It allows weak and strong scaling analysis along with the possibility to perform extensive parameter exploration analysis. For weak scaling analysis simulations, we collect synchronization traces for OpenMP applications, and for strong scaling analysis, we collect task traces for OmpSs applications.

Architectural Optimization Framework for Earth-Observing Heterogeneous Constellations: Marine Weather Forecast Case

Earth observation satellite programs are currently facing, for some applications, the need to deliver hourly revisit times, subkilometric spatial resolutions, and near-real-time data access times. These stringent requirements, combined with the consolidation of small-satellite platforms and novel distributed architecture approaches, are stressing the need to study the design of new, heterogeneous, and heavily networked satellite systems that can potentially replace or complement traditional space assets. In this context, this paper presents partial results from ONION, a research project devoted to studying distributed satellite systems and their architecting characteristics. A design-oriented framework that allows selecting optimal architectures for the given user needs is presented in this paper. The framework has been used in the study of a strategic use-case and its results are hereby presented. From an initial design space of 5586 potential architectures, the framework has been able to preselect 28 candidate designs by an exhaustive analysis of their performance and by quantifying their quality attributes. This very exploration of architectures and the characteristics of the solution space are presented in this paper along with the selected solution and the results of a detailed performance analysis.

SoC implementation of a photovoltaic reconfiguration algorithm by exploiting a HLS-based architecture

The dynamic reconfiguration of photovoltaic arrays is a promising technique for reducing the power drops due to partial shadowing. Some approaches for determining the optimal electrical configuration of the photovoltaic array have been presented in literature. The most encouraging solution is based on the use of stochastic algorithms that can be fruitfully implemented in a system on chip. The computation time takes profit from the available field programmable gate array fabric, where multiple instances of the fitness function can be run in parallel. The use of Vivado High Level Synthesis, to create a Register Transfer Level implementation from C/C++ sources, allows achieving satisfactory results. Coding the algorithm by taking into account the synthesis process, thus resource allocation, scheduling and binding, helps in obtaining a further performance improvement. In this paper a High Level Synthesis approach is used for the systematic exploration of the possible architectures that can be used for implementing the reconfiguration algorithm. Some solutions that differ in terms of computation time and hardware resources used are compared. The target system on chip is a low cost one from Xilinx.