Existing SRAM Cell Research Articles

High performance radiation-hardened SRAM cell design for robust applications

This work proposes a high-performance 16-transistor radiation-hardened SRAM cell (HP16T), which recovers from all single event upsets and from the internal node pair multiple-node upset. The proposed HP16T cell uses a separate read path through its internal nodes and demonstrates high read stability. The HP16T cell has 6.36 times higher read stability than recently proposed RHD14T cell. The write stability of the HP16T is also high, and is 1.71 times higher than that of the recently proposed HP12T cell. The HP16T cell has the shortest write access time among existing SRAM cells, and is 1.72 times smaller than that of the RSP14T cell. Compared to the existing designs, HP16T can withstand a larger amount of the critical charge, contains fewer susceptible nodes, and has the least single event upset occurrence probability. The figure of merit (FOM) is used to assess the overall performance, and the proposed HP16T exhibits the best FOM among the referenced SRAM cells.

A novel PVT‐variation‐tolerant Schmitt‐trigger‐based 12T SRAM cell with improved write ability and high ION/IOFF ratio in sub‐threshold region

AbstractThis paper presents a process voltage temperature (PVT)‐variation‐tolerant Schmitt‐trigger‐based 12T SRAM cell at 32 nm. The cell uses a modified Schmitt‐trigger action in all operating modes for performance improvement, a characteristic that is not exhibited by existing SRAM cells. The action improves the stability of stored data in read and hold modes and assists the write process to enable a faster and low‐voltage write operation. Additionally, the cell uses negative bitline technique and fully‐gated grounded scheme for achieving further improvement in write ability and ION/IOFF ratio. The proposed cell shows 34.9% reduced deviation in switching threshold voltage in comparison to conventional structure. Further, improvement of up to 211% in write ability and 169% in ION/IOFF ratio is obtained over existing SRAM cells operating in sub‐threshold region. The cell takes up to 86% and 99% lesser read and write access time, respectively. The Monte‐Carlo simulations show the robust performance of proposed cell. The cell has reduced write, read, and hold failure probabilities resulting in overall Vmin of 425 mV, which is the least among the cells considered for comparison, thus making it an amenable design suitable for sub‐threshold operation under PVT‐variations.

Darlington Based 8T CNTFET SRAM Cells with Low Power and Enhanced Write Stability

In this paper, a novel low power and high write margin Darlington based NCNTFET Darlington 8T SRAM cell is proposed. The power consumption of the proposed Darlington SRAM cell is compared with that of conventional 6T CNTFET and conventional 8T CNTFET SRAM cells. The power consumption of the proposed Darlington SRAM cells is very less as compared to that of conventional 6T and 8T CNTFET SRAM cells for all write, hold, and read operations. The write static noise margin (WSNM) of the proposed NCNTFET Darlington 8T cell is found to increase by 70.83% than that of both conventional 6T and 8T CNTFET SRAM cell. Effect of CNTFET parameters such as chiral vectors (m,n), gate oxide thickness (Hox), dielectric constant of gate oxide material (Kox), temperature, pitch value, number of carbon nano tubes (CNTs) and supply voltage (VDD), on the power performance, drain current (ID) and drain to source voltage (VDS) of the novel proposed Darlington SRAM cell are investigated. The write, hold, and read power consumption of proposed NCNTFET Darlington 8T SRAM cell is compared with that of some of the existing SRAM cells. The simulation is carried out using Stanford University 32 nm CNTFET model.

A data‐independent 9T SRAM cell with enhanced ION/IOFF ratio and RBL voltage swing in near threshold and sub‐threshold region

SummaryThe conventional 8T SRAM cell with isolated read port is suggested as an alternative to overcome the read‐write conflicts associated with 6T SRAM cell. However, in near threshold and sub‐threshold regions, 8T cell performance is limited by reduced ION/IOFF ratio, deteriorated RBL voltage swing, data dependency, and higher read failures, although the existing SRAM cells address some of these issues but still suffer from degraded performance due to the trade‐off between leakage and read currents. In this paper, a 9T SRAM cell with novel read port is proposed that aims for low and data‐independent leakages, high ION/IOFF ratio, and large RBL voltage swing in near threshold and sub‐threshold regions. The performance of the proposed cell is compared with 7T, 8T, 9T, and 10T cells at 32 nm technology node by simulating a column of 128 cells to demonstrate its versatility over others. The proposed cell shows enhanced ION/IOFF ratio (71.2X), large RBL voltage swing and data‐independent leakages at VDD = 0.3 V in comparison to the conventional 8T SRAM cell. The results at different PVT corners are also captured to validate the impeccable performance of the proposed cell irrespective of operating conditions.

A Novel circuit of SRAM Cell Against Single-Event Multiple Effects for 45nm Technology

As CMOS technology down sized into double digit nanometer ranges, variations are a serious concern due to uncertainty in devices and interconnect characteristics. The single event upset (SEU) is changing the state of a memory cell due to the strike of an energetic particle. The single event multiple effects are likely to increase in nanometer CMOS technology due to reduced device size and scaling of power supply voltage.SRAM cells are sensitive to radiation induced hazards. Therefore, designing a reliable novel SRAM cell is an important challenge against SEU. In this paper, the proposed SRAM cell that provides a better features than their recent proposed SRAM cells. The simulation results and analysis represent that the proposed SRAM cell exhibits the high robustness against single event multiple effects (SEMEs). Moreover, the proposed SRAM cell successfully reduced the power consumption by 41% and write delay by 2% in comparison with the existing radiation-hardened SRAM cells at the cost of circuit complexity. The process corner analysis displays the comparison of power and delay of the proposed and existing SRAM cells. It shows that the proposed memory cell consumes less power than previous memory cells.

Characteristic analysis of a novel low power 10T SRAM cell during read and write operations

This paper focuses on characteristic analysis of a novel 10T SRAM cell. In the proposed cell two voltage sources VS1 and VS2 are used, one of which connected with the bit line and the other connected with the bitbar line, respectively, for reducing the voltage swing during the switching activity. This reduction in voltage swing causes less dynamic power dissipation during switching activity. Two stack transistors ST1 and ST2 are also connected in the pull-down paths. Due to the stack effect in the pull-down transistors in OFF condition sub-threshold leakage current is reduced and this causes reduction of static power dissipation. Simulation has been done in 45nm CMOS technology with 0.7 volt power supply with the help of Microwind 3.1 software. The simulation results of power dissipation, noise margin, power delay product and current leakage during read/write operation have been determined and compared to those of other existing SRAM cells.