Loop Execution Research Articles

The Analysis and Application Research on the Performance of Describing Based on an Abstract Grid Workflow Language

Grid Workflow Language Yu wan jun1,2, Liu Yunxiang1,2, Fang Hua1,21 Shanghai institute of technology, School of computer science and information engineering, Shanghai, 201418, China 2Shanghai institute of technology, research center of machine olfaction, Shanghai, 201418, China Key words:Intelligant System; Grid Workflow; Activity; Parallel Structure; Abstract:Grids specification is one of the imporant contents in grid workflow fields, it can shield details of underling grid, so users can concentrate on the description of Grid applications. AGWL(Abstract Grid Workflow Language) is an abstract language based on XML, it was always used to describe grid workflow. The basic activities are connected by the control flow and data link. AGWL uses advanced control flow to support the parallel execution of conditions and loops. As an example, we finally introduced a sales process to show the capacity of the grid workflow language AGWL.

Design Space Exploration of Distributed Loop Buffer Architectures with Incompatible Loop-Nest Organisations in Embedded Systems

The use of distributed loop buffer architectures with incompatible loop-nest organisations allows the execution of incompatible loops in parallel with minimal hardware overhead. Due to this fact, the utilisation of these distributed and scalable architectures in embedded systems is a promising option to improve the energy efficiency of the instruction memory organisations that exist in these systems. This paper proposes and analyses non-overlapping and complementary implementation options for distinct partitions of the design space that is related to distributed loop buffer architectures. The high-level trade-off analysis of the proposed implementations is crucial to present the correct process design that an embedded systems designer has to follow in order to have an efficient distributed loop buffer architecture for a certain application. Results show that, with an increase of about 6.5 % in the energy consumption of the control logic that exists in the instruction memory organisation, the overall energy consumption of the instruction memory organisation can be reduced by 6 % to 22 %, when distributed loop buffer architectures with incompatible loop-nest organisations are used instead of clustered loop buffer architectures with shared loop-nest organisations architectures.

SEED: A Statically Greedy and Dynamically Adaptive Approach for Speculative Loop Execution

Research on compiler techniques for thread-level loop speculation has so far remained on studying its performance limits: loop candidates that are worthy of parallelization are manually selected by the researchers or based on extensive profiling and preexecution. It is therefore difficult to include them in a production compiler for speculative multithreaded multicore processors. In a way, existing techniques are statically adaptive (realized; by the researchers for different inputs) yet dynamically greedy (since all iterations of all selected loop candidates are always parallelized at run time). This paper introduces a Statically GrEEdy and Dynamically Adaptive (SEED) approach for thread-level speculation on loops that is quite different from most other existing techniques. SEED relies on the compiler to select and optimize loop candidates greedily (possibly in an input-independent way) and provides a runtime scheduler to schedule loop iterations adaptively. To select loops for parallelization at runtime (subject to program inputs), loop iterations are prioritized in terms of their potential benefits rather than their degree of speculation as in many prior studies. In our current implementation, the benefits of speculative threads are estimated by a simple yet effective cost model. It comprises a mechanism for efficiently tracing the loop nesting structures of the program and a mechanism for predicting the outcome of speculative threads. We have evaluated SEED using a set of SPECint2000 and Olden benchmarks. Compared to existing techniques with a program's loop candidates being ideally selected a priori, SEED can achieve comparable or better performance while aututomating the entire loop candidate selection process.

국내 시판 경옥고 제품의 품질 특성 및 항염증 활성

시판 경옥고 제품의 품질 특성과 항염증 활성에 대한 특성을 비교 분석하였다. 총 10종에 대한 일반성분을 분석한 결과, 수분(18.62～49.78%), 탄수화물(47.95～77.08%), 단백질(0.89～3.58%), 지질(0.16～1.14%) 및 회분(0.20～1.21%)이었고, 진세노사이드는 홍삼특유 사포닌인 Rg3, Rh1, Rh2 및 F1 등의 사포닌이 검출되어 총사포닌 함량은 0.24～0.76mg/g이었으며, 생지황의 지표물질인 catalpol의 함량은 0.12～1.10 mg/g이었다. 유리당 조성 및 함량은 glucose가 11.00～22.38%로 가장 많이 함유되어 있으며, 이어서 fructose, sorbitol, maltose, 3당류 그리고 sucrose 순으로 검출되었고 총함량은 29.09～41.34%이었다. 색도는 백색도는 26.49～73.87, 적색도는 30±10, 황색도는 80～90의 범위에 있었다. 경옥고 제품의 물성은 점도특성으로 볼 때 일정한 온도에서 일정 회전속도로 반복적으로 작동시킬 경우 비례적으로 점도가 증가하는 특성을 가졌으며, 본 시험에 이용된 경옥고 제품의 물성은 크게 3가지 구분으로 grouping 되었는데 정적인 상태에서 고체상을 가지는 제품은 3, 5 및 10번이었고, 제품 2, 6 및 4번은 4회 반복 시까지는 일정값으로 비례적으로 상승하다가 그 이후부터는 일정한 값을 나타냈고, 7 및 8번은 한번 회전시킨 이후부터 거의 일정한 값을 보여주는 유동적인 특성을 보여주었으며, 탄수화물의 함량이 높은 것일수록 유동성이 큰 물성을 보여주었다. 시판 경옥고 제품의 열수추출물의 처리에 의한 RAW 264.7 대식세포에의 증식에 미치는 영향은 제품마다 약간씩 차이가 남을 볼 수 있었고, 제품 중 1, 2, 4, 5, 6, 7, 8번 제품이 세포독성이 낮은 것으로 나타났으며, 특히 8번 제품은 가장 안전한 것으로 관찰되었다. LPS를 대식세포에 처리하기 전에 각 경옥고 제품의 추출물을 전처리하여 항염증 활성을 조사한 결과를 종합해 보면, 세포독성이 낮으면서 대식세포로부터의 염증매개인자의 분비를 억제하는 항염증 활성은 1번과 7번 제품이 가장 우수하며, 2번 제품도 비교적 높은 안전성과 염증반응 억제효과를 가지는 것으로 판단되었다.

Foundations of distributed multiscale computing: Formalization, specification, and analysis

Inherently complex problems from many scientific disciplines require a multiscale modeling approach. Yet its practical contents remain unclear and inconsistent. Moreover, multiscale models can be very computationally expensive, and may have potential to be executed on distributed infrastructure. In this paper we propose firm foundations for multiscale modeling and distributed multiscale computing. Useful interaction patterns of multiscale models are made predictable with a submodel execution loop (SEL), four coupling templates, and coupling topology properties. We enhance a high-level and well-defined Multiscale Modeling Language (MML) that describes and specifies multiscale models and their computational architecture in a modular way. The architecture is analyzed using directed acyclic task graphs, facilitating validity checking, scheduling distributed computing resources, estimating computational costs, and predicting deadlocks. Distributed execution using the multiscale coupling library and environment (MUSCLE) is outlined. The methodology is applied to two selected applications in nanotechnology and biophysics, showing its capabilities.

A dynamic self-scheduling scheme for heterogeneous multiprocessor architectures

Today's heterogeneous architectures bring together multiple general-purpose CPUs and multiple domain-specific GPUs and FPGAs to provide dramatic speedup for many applications. However, the challenge lies in utilizing these heterogeneous processors to optimize overall application performance by minimizing workload completion time. Operating system and application development for these systems is in their infancy. In this article, we propose a new scheduling and workload balancing scheme, HDSS, for execution of loops having dependent or independent iterations on heterogeneous multiprocessor systems. The new algorithm dynamically learns the computational power of each processor during an adaptive phase and then schedules the remainder of the workload using a weighted self-scheduling scheme during the completion phase. Different from previous studies, our scheme uniquely considers the runtime effects of block sizes on the performance for heterogeneous multiprocessors. It finds the right trade-off between large and small block sizes to maintain balanced workload while keeping the accelerator utilization at maximum. Our algorithm does not require offline training or architecture-specific parameters. We have evaluated our scheme on two different heterogeneous architectures: AMD 64-core Bulldozer system with nVidia Fermi C2050 GPU and Intel Xeon 32-core SGI Altix 4700 supercomputer with Xilinx Virtex 4 FPGAs. The experimental results show that our new scheduling algorithm can achieve performance improvements up to over 200% when compared to the closest existing load balancing scheme. Our algorithm also achieves full processor utilization with all processors completing at nearly the same time which is significantly better than alternative current approaches.

Transparent Runtime Migration of Loop-Based Traces of Processor Instructions to Reconfigurable Processing Units

The ability to map instructions running in a microprocessor to a reconfigurable processing unit (RPU), acting as a coprocessor, enables the runtime acceleration of applications and ensures code and possibly performance portability. In this work, we focus on the mapping of loop-based instruction traces (called Megablocks) to RPUs. The proposed approach considers offline partitioning and mapping stages without ignoring their future runtime applicability. We present a toolchain that automatically extracts specific trace-based loops, called Megablocks, from MicroBlaze instruction traces and generates an RPU for executing those loops. Our hardware infrastructure is able to move loop execution from the microprocessor to the RPU transparently, at runtime, and without changing the executable binaries. The toolchain and the system are fully operational. Three FPGA implementations of the system, differing in the hardware interfaces used, were tested and evaluated with a set of 15 application kernels. Speedups ranging from 1.26 to 3.69 were achieved for the best alternative using a MicroBlaze processor with local memory.

From Hierarchy of the Levels of Theoretical Inquiry to Full Type 2 Fuzzy System Models

We first present a brief review of the essentials fuzzy system models: Namely (1) Zadeh’s rule base model, (2) Takagi and Surgeon’s model which is partly a rule base and partly a regression function and (3) Turksen fuzzy regression functions where fuzzy regression functions correspond to each fuzzy rule. Next we review the well-known FCM algorithm which lets one to extract Type 1 membership values from a given data set for the development of Type 1 fuzzy system models as a foundation for the development of Full Type 2 fuzzy system models. For this purpose, we provide an algorithm which lets one to generate Full Type 2 membership value distributions for a development of second order fuzzy system models with our proposed second order data analysis. If required one can generate Full Type 3. Full Type n fuzzy system models with an iterative execution of our algorithm. We present our application results graphically for TD_Stockprice data with respect to two validity indeces, namely: 1) Celikyilmaz-Turksen and 2) Bezdek indeces.

Memory-saving memetic computing for path-following mobile robots

In this paper, a recently proposed single-solution memetic computing optimization method, namely three stage optimization memetic exploration (3SOME), is used to implement a self-tuning PID controller on board of a mobile robot. More specifically, the optimal PID parameters minimizing a measure of the following error on a path-following operation are found, in real-time, during the execution of the control loop. The proposed approach separates the control and the optimization tasks, and uses simple operating system primitives to share data. The system is able to react to modifications of the trajectory, thus endowing the robot with intelligent learning and self-configuration capabilities. A popular commercial robotic tool, i.e. the Lego Mindstorms robot, has been used for testing and implementing this system. Tests have been performed both in simulations and in a real Lego robot. Experimental results show that, compared to other online optimization techniques and to empiric PID tuning procedures, 3SOME guarantees a robust and efficient control behaviour, thus representing a valid alternative for self-tuning control systems.

Branch Target Buffer Energy Reduction Through Efficient Multiway Branch Translation Techniques

Branch Target Buffer (BTB) plays an important role for pipelined processors in branch prediction during the execution of loops, if-then-else, call-return, and multiway branch statements. It has been observed that 20% of instructions in a program are related to branch. Access to BTB consumes 10% of total energy consumption of a program in execution. The present work introduces the use of K–d tree and pattern matcher to generate efficient code, i.e., lesser execution time, for multiway branch. However, instead of enhancing performance, Voltage Frequency Scaling (VFS) can be applied to achieve energy efficiency without degradation in performance. The present work is evaluated on a wide range benchmark programs. The BTB energy saving in the present work lies in the range 20% to 80% with small improvement performance as well. The total energy reduction is in the range 3–12%.

Free Recall Behaviour in Children with and without Spelling Impairment: The Impact of Working Memory Subcapacities

This study examined supraspan free recall in children with and without spelling impairment. A repeated free recall task involving overt rehearsal and three computer-based adaptive working memory tasks were administered to 54 eight-year-old children. Children without spelling impairments tended to recall more items than did those children with spelling deficits. Video analyses revealed that recall behaviour was similar in impaired and unimpaired children, indicating that both groups applied similar learning activities. Group differences in number of recalled items were attributed to differences in working memory subcapacities between children with and without spelling impairment, especially with regard to central executive and phonological loop functioning.

Optimization-based iterative learning for precise quadrocopter trajectory tracking

Current control systems regulate the behavior of dynamic systems by reacting to noise and unexpected disturbances as they occur. To improve the performance of such control systems, experience from iterative executions can be used to anticipate recurring disturbances and proactively compensate for them. This paper presents an algorithm that exploits data from previous repetitions in order to learn to precisely follow a predefined trajectory. We adapt the feed-forward input signal to the system with the goal of achieving high tracking performance--even under the presence of model errors and other recurring disturbances. The approach is based on a dynamics model that captures the essential features of the system and that explicitly takes system input and state constraints into account. We combine traditional optimal filtering methods with state-of-the-art optimization techniques in order to obtain an effective and computationally efficient learning strategy that updates the feed-forward input signal according to a customizable learning objective. It is possible to define a termination condition that stops an execution early if the deviation from the nominal trajectory exceeds a given bound. This allows for a safe learning that gradually extends the time horizon of the trajectory. We developed a framework for generating arbitrary flight trajectories and for applying the algorithm to highly maneuverable autonomous quadrotor vehicles in the ETH Flying Machine Arena testbed. Experimental results are discussed for selected trajectories and different learning algorithm parameters.

Frontostriatal Connectivity in Children during Working Memory and the Effects of Prenatal Methamphetamine, Alcohol, and Polydrug Exposure

Various abnormalities in frontal and striatal regions have been reported in children with prenatal alcohol and/or methamphetamine exposure. In a recent fMRI study, we observed a correlation between accuracy on a working-memory task and functional activation in the putamen in children with prenatal methamphetamine and polydrug exposure. Because the putamen is part of the corticostriatal motor loop whereas the caudate is involved in the executive loop, we hypothesized that a loss of segregation between distinct corticostriatal networks may occur in these participants. The current study was designed to test this hypothesis using functional connectivity MRI. We examined 50 children ranging in age from 7 to 15, including 19 with prenatal methamphetamine exposure (15 of whom had concomitant prenatal alcohol exposure), 13 with prenatal exposure to alcohol but not methamphetamine, and 18 unexposed controls. We measured the coupling between blood oxygenation level dependent (BOLD) fluctuations during a working-memory task in four striatal seed regions and those in the rest of the brain. We found that the putamen seeds showed increased connectivity with frontal brain regions involved in executive functions while the caudate seeds showed decreased connectivity with some of these regions in both groups of exposed subjects compared to controls. These findings suggest that localized brain abnormalities resulting from prenatal exposure to alcohol and/or methamphetamine lead to a partial rewiring of corticostriatal networks. These results represent important progress in the field, and could have substantial clinical significance in helping devise more targeted treatments and remediation strategies designed to better serve the needs of this population.

Obstacles to decision making in Agile software development teams

The obstacles facing decision making in Agile development are critical yet poorly understood. This research examines decisions made across four stages of the iteration cycle: Iteration Planning, Iteration Execution, Iteration Review and Iteration Retrospective. A mixed method approach was employed, whereby a focus group was initially conducted with 43 Agile developers and managers to determine decisions made at different points of the iteration cycle. Subsequently, six illustrative mini cases were purposefully conducted as examples of the six obstacles identified in these focus groups. This included interviews with 18 individuals in Agile projects from five different organizations: a global consulting organization, a multinational communications company, two multinational software development companies, and a large museum organization. This research contributes to Agile software development literature by analyzing decisions made during the iteration cycle and identifying six key obstacles to these decisions. Results indicate the six decision obstacles are unwillingness to commit to decisions; conflicting priorities; unstable resource availability; and lack of: implementation; ownership; empowerment. These six decision obstacles are mapped to descriptive decision making principles to demonstrate where the obstacles affect the decision process. The effects of these obstacles include a lack of longer-term, strategic focus for decisions, an ever-growing backlog of delayed work from previous iterations, and a lack of team engagement.

Interactions within and between Corticostriatal Loops during Component Processes of Category Learning

We examined dynamic interactions between cortex and BG during stimulus-response and feedback processing phases of categorization. First, we dissociated stimulus-response processing from feedback processing using "jittered" intervals of time between response and feedback to examine how each recruits the four primary corticostriatal loops (motor, executive, visual, and motivational). Second, we examined dynamic interactions within and between corticostriatal loops using Granger causality mapping. On each trial, subjects viewed one of six abstract visual stimuli, pressed a button indicating category membership, and then received feedback as to whether the decision was right or wrong. Stimulus-response processing was associated with greater activity in the visual loop, whereas feedback processing resulted in activity in the executive loop that was sensitive to feedback valence. Granger causality mapping showed patterns of directed influence within corticostriatal loops and between loops from the motor to the executive, to the visual, and finally to the motivational loop. These patterns of interaction are consistent with functional integration of motor processing in the motor loop with feedback processing in the executive loop and maintenance of stimulus-response history for future responses in the motivational loop.

S15 * ESBRA/ISBRA JOINT SYMPOSIUM: IMAGING IN ALCOHOL RESEARCH * S15.1 * THE ROLE OF FUNCTIONAL NEUROIMAGING IN THE CHOICE OF TREATMENT FOR ALCOHOLICS

S15 * ESBRA/ISBRA JOINT SYMPOSIUM: IMAGING IN ALCOHOL RESEARCH * S15.1 * THE ROLE OF FUNCTIONAL NEUROIMAGING IN THE CHOICE OF TREATMENT FOR ALCOHOLICS

An integrated development framework for rapid development of platform-independent and reusable satellite on-board software

Even in the field of small satellites, the on-board data handling subsystem has become complex and powerful. With the introduction of powerful CPUs and the availability of considerable amounts of memory on-board a small satellite it has become possible to utilize the flexibility and power of contemporary platform-independent real-time operating systems. Especially the non-commercial sector such like university institutes and community projects such as AMSAT or SSETI are characterized by the inherent lack of financial as well as manpower resources. The opportunity to utilize such real-time operating systems will contribute significantly to achieve a successful mission. Nevertheless the on-board software of a satellite is much more than just an operating system. It has to fulfill a multitude of functional requirements such as: Telecommand interpretation and execution, execution of control loops, generation of telemetry data and frames, failure detection isolation and recovery, the communication with peripherals and so on. Most of the aforementioned tasks are of generic nature and have to be conducted on any satellite with only minor modifications. A general set of functional requirements as well as a protocol for communication is defined in the SA ECSS-E-70-41A standard “Telemetry and telecommand packet utilization”. This standard not only defines the communication protocol of the satellite–ground link but also defines a set of so called services which have to be available on-board of every compliant satellite and which are of generic nature. In this paper, a platform-independent and reusable framework is described which is implementing not only the ECSS-E-70-41A standard but also functionalities for interprocess communication, scheduling and a multitude of tasks commonly performed on-board of a satellite. By making use of the capabilities of the high-level programming language C/C++, the powerful open source library BOOST, the real-time operating system RTEMS and finally by providing generic functionalities compliant to the ECSS-E-70-41A standard the proposed framework can provide a great boost in productivity. Together with open source tools such like the GNU tool-chain, Eclipse SDK, the simulation framework OpenSimKit, the emulator QEMU, the proposed on-board software framework forms an integrated development framework. It is possible to design, code and build the on-board software together with the operating system and then run it on a simulated satellite for performance analysis and debugging purposes. This makes it possible to rapidly develop and deploy a full-fledged satellite on-board software with minimal cost and in a limited time frame.

Efficient hardware-based nonintrusive dynamic application profiling

Application profiling—the process of monitoring an application to determine the frequency of execution within specific regions—is an essential step within the design process for many software and hardware systems. Profiling is often a critical step within hardware/software partitioning utilized to determine the critical kernels of an application. In this article, we present an innovative, nonintrusive dynamic application profiler (DAProf) capable of profiling an executing application by monitoring the application's short backward branches, function calls, and function returns. The resulting profile information provides an accurate characterization of the frequently executed loops within the application providing a breakdown of loop executions versus loop iterations per execution. DAProf achieves excellent profiling accuracy with an average accuracy of 98% for loop executions, 97% for average iterations per execution, and 95% for percentage of execution time. In addition, the presented dynamic application profiler incurs as little as 11% area overhead compared to an ARM9 microprocessor. DAProf is ideally suited for rapidly profiling software applications and dynamic optimization approaches such as dynamic hardware/software partitioning in which detailed loop execution information is needed to provide accurate performance estimates.

A performance evaluation on monte carlo simulation for radiation dosimetry using cell processor

This study investigated the performance of Cell processor in Monte Carlo simulation using the EGSnrc code. The execution speeds of two processor-intensive functions namely, HOWNEAR and RANMAR_GET in the EGSnrc code based on the informal 20-80 rule were measured, using the profiler gprof, which specified the number of executions and total time spent in the function. The functions were re-implemented in a testing architecture designed for Cell processor using a Playstation3 (PS3) system. This specific framework was designed to divide the program functionality in two-isolating branching code for execution on the powerPC processing element (PPE) and synergistic processing elements (SPEs) in the system. Depth dose profiles in heterogeneous phantoms using photon and electron beams calculated by a CPU and Cell processor were compared and there was no difference in the results. It was found that our examined algorithms could be parallelizable on the Cell processor, provided that an architectural change of the EGSnrc was made so that the code was initialized on the PPE, and execution of the simulation loop within the program be split between the PPE and SPE. Since it was found that the EGSnrc performance was currently limited by the PPE using the Cell processor, a computing platform of PC coupled with a general purpose programming on graphics processing units or GPGPU may provide a more viable avenue for acceleration.

Accurate Determination of Loop Iterations for Worst-Case Execution Time Analysis

Determination of accurate estimates for the Worst-Case Execution Time of a program is essential for guaranteeing the correct temporal behavior of any Real-Time System. Of particular importance is tightly bounding the number of iterations of loops in the program or excessive undue pessimism can result. This paper presents a novel approach to determining the number of iterations of a loop for such analysis. Program traces are collected and analyzed allowing the number of loop executions to be parametrically determined safely and precisely under certain conditions. The approach is mathematically proved to be safe and its practicality is demonstrated on a series of benchmarks.