Execute Stage Research Articles

FPGA-based LoongArch Five-stage Pipeline CPU

We designed and implemented a five-stage pipeline CPU based on the FPGA platform, programmed in Verilog hardware description language to implement LoongArch architecture. The design and implementation of the Instruction Fetch (IF) stage, Instruction Decode (ID) stage, Instruction Execute (EX) stage, Memory Access (MEM) stage, and Write Back (WB) stage. The design and implementation of the important modules in the pipeline are given. The use of the Bubble method and Bypass technique solves most of the parameter passing problems and branch judgment problems in the pipeline. The access memory problem is solved using design tricks. Finally, the design is verified on an FPGA platform. The CPU design can be well used in learning and research related to pipeline CPUs. It can also support experimental platforms and provide an example for further research in pipelines and SOCs.

Design and Assertion Based Verification of RISC-V Processor Subsystems

RISC-V is an open, free standard architecture. As its open-source architecture, it can be used in multiple applications like embedded processors, IoT, artificial intelligence, machine learning, military and defense applications. The parameters like throughput, performance, high speed etc., become essential in designing processor architecture. Pipelining is one such unique feature supported by RISC-V ISA, which basically involves the execution of multiple instructions in single cycle. This feature helps in improving the performance of the processor architecture. RISC-V ISA supports five stages of pipelining they are instruction fetch, instruction decode, execute, memory and write-back stage. The work covered in this paper involves the design and implementation of the subsystems of the RISC-V ISA which are present in different stages of pipeline architecture. The subsystems included in this work are Floating Point Unit (FPU) of Execute stage, Branch Prediction Unit (BPU) of instruction fetch stage, Forwarding Unit of execution stage, Operand Logic of decode stage and Floating-Point register file of Write-back stage. These subsystems are designed using Verilog Hardware Description Language in Xilinx ISE. Followed by the implementation the verification of the floating-point unit and the forwarding unit is performed using System Verilog Assertions in QuestaSim. The Assertion coverage report for the same is extracted.

Практическая абстрактная интерпретация бинарного кода

The mathematical foundations of abstract interpretation provide a unified method of formalization and research of program analysis algorithms for a broad spectrum of practical problems. However, its practical usage for binary code analysis faces several challenges, of both scientific and engineering nature. In this paper we address some of those challenges. We describe an intermediate representation that is tailored to binary code analysis; unlike some other IRs it is still useable in system code analysis. To achieve this, we take into account the low-level specifics of how CPUs work; on the IR level this mostly pertains to modeling main memory in that accesses can fail, and addresses can alias. Further, we propose an infrastructure for carrying out abstract interpretation on top of the IR. The user needs to implement the abstract state and the transfer functions, and the infrastructure handles the rest: two executors are currently implemented, one for analysis of a single path, and one for fixed point analysis. Both executors handle interprocedural analysis internally, via inlining or using summaries, so the interpretations only consider only procedure at a time, which greatly simplifies implementation. The IR and the abstract interpretation framework are used together to define a model pipeline for a target instruction set architecture, consisting of a fetch stage, a decode stage, and an execute stage. A distinct fetch stage allows to model delay slots, hardware loops, etc. We currently have limited implementations for RISC-V and x86. The x86 implementation is evaluated in two experiments where concolic execution is used to automatically analyze a «crackme» program, both in dynamic (execution trace) and static (executable image) setting. In conclusion, we outline the future directions of our project.

Multi-channel biomimetic visual transformation for object feature extraction and recognition of complex scenes

Object recognition occurs accurately with human visual neural mechanism despite in different complex background interference. For computer system, it is still a challenging work of object recognition and classification. Recently, many methods for object recognition based on human visual perception mechanism are presented. However, most methods cannot achieve a better recognition accuracy when object images are corrupted by some background interferences. Therefore, it is necessary to propose a method for object recognition of complex scene. Inspired by biomimetic visual mechanism and visual memory, a multi-channel biomimetic visual transformation (MCBVT) is proposed in this paper. MCBVT involves three channels. Firstly, some algorithms including orientation edge detection (OED), local spatial frequency detection (LSFD) and weighted centroid coordinate calculation are adopted for two stage’s visual memory maps creations during the first channel, where some visual memory points are stored in memory map. Secondly, an object hitting map (OHM) is built in the second channel and the OHM is an edge image without background interference. After that, the first stage’s visual memory hitting map is obtained through execute back-tracking second stage’s visual memory map. Furthermore, an OHM is constructed through back-tracking with common memory points in first stage’s visual memory map and first stage’s visual memory hitting map. Thirdly, the OED and LSFD algorithms are conducted to extract a feature map of OHM in the third channel. Consequently, the final feature map is reshaped into a feature vector, which is used for object recognition. Additionally, several image database experiments are implemented, the recognition accuracy for alphanumeric, MPEG-7 and GTSRB database are 93.33%, 91.33 and 90% respectively. Moreover, same object images in different backgrounds share with highly similar feature maps. On the contrary, different object images with complex backgrounds through MCBVT show different feature maps. The experiments reveal a better selectivity and invariance of MCBVT features. In summary, the proposed MCBVT provides a new framework of feature extraction. Background interference of object image is eliminated through the first and second channel, which is a new method for background noise reduction. Meanwhile, the results show that the proposed MCBVT method is better than other feature extraction methods. The contributions of this paper is significant in computational intelligence for the further work.

Power and Area Efficient Clock Stretching and Critical Path Reshaping for Error Resilience

Energy efficient semiconductor chips are in high demand to cater the needs of today’s smart products. Advanced technology nodes insert high design margins to deal with rising variations at the cost of power, area and performance. Existing run time resilience techniques are not cost effective due to the additional circuits involved. In this paper, we propose a design time resilience technique using a clock stretched flip-flop to redistribute the available slack in the processor pipeline to the critical paths. We use the opportunistic slack to redesign the critical fan in logic using logic reshaping, better than worst case sigma corner libraries and multi-bit flip-flops to achieve power and area savings. Experimental results prove that we can tune the logic and the library to get significant power and area savings of 69% and 15% in the execute pipeline stage of the processor compared to the traditional worst-case design. Whereas, existing run time resilience hardware results in 36% and 2% power and area overhead respectively.

STRATEGI KOMUNIKASI WISATA TAMAN AIR MANCUR SRI BADUGA SITU BULEUD KABUPATEN PURWAKARTA

This research was motivated by Situ Buleud is not so well known to the public then was built and developed into a Sri Baduga Fountain Park requires communication to the target audience to come to Purwakarta District. This research uses qualitative research methodology with qualitative descriptive approach. The purpose of this research is to describe and analyze the communication strategy of Sri Baduga Situ Buleud Fountain Park. The object of this research is communication strategy of DISPORAPARBUD and DISKOMINFO Purwakarta District. This session will discuss about five stage of communication plans are research, plan, execute, measure, and report. The result found that research which has been done by DISPORAPARBUD are observation and the evaluation result of the number of tourists and DISKOMINFO take the data from the monitoring media report. DISPORAPARBUD and DISKOMINFO Purwakata District has been planned to determine the source or communicator, message, media, target, and effects. The execute stage will be performed after getting approval from Purwakarta Regent by implementing the plan that has been designed. In this Measure stage, DISPORAPARBUD will count the total of tourist, while tourism media will be monitored by DISKOMINFO Purwakarta district. Report undertaken by DISPORAPARBUD Purwakarta District, conduct an evaluation by counting the number of tourists in each week and will be made a report at the end of each year. Therefor DISKOMINFO Reporting as a book report on the results of analysis from third parties

Cost-effective speculative scheduling in high performance processors

To maximize performance, out-of-order execution processors sometimes issue instructions without having the guarantee that operands will be available in time; e.g. loads are typically assumed to hit in the L1 cache and dependent instructions are issued accordingly. This form of speculation -- that we refer to as speculative scheduling -- has been used for two decades in real processors, but has received little attention from the research community. In particular, as pipeline depth grows, and the distance between the Issue and the Execute stages increases, it becomes critical to issue instructions dependent on variable-latency instructions as soon as possible rather than wait for the actual cycle at which the result becomes available. Unfortunately, due to the uncertain nature of speculative scheduling, the scheduler may wrongly issue an instruction that will not have its source(s) available on the bypass network when it reaches the Execute stage. In that event, the instruction is canceled and replayed, potentially impairing performance and increasing energy consumption. In this work, we do not present a new replay mechanism. Rather, we focus on ways to reduce the number of replays that are agnostic of the replay scheme. First, we propose an easily implementable, low-cost solution to reduce the number of replays caused by L1 bank conflicts. Schedule shifting always assumes that, given a dual-load issue capacity, the second load issued in a given cycle will be delayed because of a bank conflict. Its dependents are thus always issued with the corresponding delay. Second, we also improve on existing L1 hit/miss prediction schemes by taking into account instruction criticality. That is, for some criterion of criticality and for loads whose hit/miss behavior is hard to predict, we show that it is more cost-effective to stall dependents if the load is not predicted critical. In total, in our experiments assuming a 4-cycle issue-to-execute delay, we found that the majority of instruction replays caused by L1 data cache banks conflicts -- 78.0% -- and L1 hit mispredictions -- 96.5% -- can be avoided, thus leading to a 3.4% performance gain and a 13.4% decrease in the number of issued instructions, over a baseline pipeline with speculative scheduling.

A Framework for Power-Gating Functional Units in Embedded Microprocessors

Power gating is a technique commonly used for leakage reduction in integrated circuits. In microprocessors, power gating is implemented by using sleep transistors to selectively deactivate circuit modules that remain idle for sustained periods of time during program execution. In this work, we develop a new framework for power gating the functional units in embedded system microprocessors without degradation in performance. The proposed framework includes an efficient algorithm for idle time estimation, appropriate insertion of sleep instructions within the code, and a method for reactivating the sleeping units only when needed without the use of wakeup instructions. We introduce the notion of loop hierarchy trees (LHTs) to represent the partial ordering of the nested loops within the program. From the control flow graph (CFG) representation of the source program, a forest of LHTs is constructed and is used to identify the maximal subgraphs representing the long idle periods for the functional units. For each subgraph thus identified, a sleep instruction is introduced in the program with a list of corresponding functional units to be deactivated. When an instruction is decoded, the functional units needed for that instruction are automatically activated by the control unit such that the units are ready before the instruction reaches the execute stage. This eliminates the need for wakeup instructions to be inserted into the object code reducing the overheads. In our implementation, the ARM processor architecture was modified and resynthesized to include power gating by developing a CMOS cell library of functional units with the above capabilities. Experimental results are reported for a set of 12 benchmarks chosen from the MiBench suite, which indicate that, on average, our technique reduces the leakage energy in functional units by 31.1% for integer benchmarks and 26.8% for floating-point benchmarks.

Operand Registers and Explicit Operand Forwarding

Operand register files are small, inexpensive register files that are integrated with function units in the execute stage of the pipeline, effectively extending the pipeline operand registers into register files. Explicit operand forwarding lets software opportunistically orchestrate the routing of operands through the forwarding network to avoid writing ephemeral values to registers. Both mechanisms let software capture short-term reuse and locality close to the function units, improving energy efficiency by allowing a significant fraction of operands to be delivered from inexpensive registers that are integrated with the function units. An evaluation shows that capturing operand bandwidth close to the function units allows operand registers to reduce the energy consumed in the register files and forwarding network of an embedded processor by 61%, and allows explicit forwarding to reduce the energy consumed by 26%.