exclusive-OR Logic Research Articles

Digital single-sideband mixer

A single-sideband (SSB) frequency converter using only exclusive-or logic gates and no reactive or frequency-selective analog circuit elements takes square-wave inputs at two arbitrary frequencies f <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1</inf> and f <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> and generates an output waveform whose principal spectral component is at either f <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1</inf> +f <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> or f <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1</inf> -f <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> , selectably. A pair of outputs is generated in phase quadrature.

Easily Testable Realizations ror Logic Functions

Desirable properties of "easily testable networks" are given. A realization for arbitrary logic function, using AND and EXCLUSIVE-OR gates, based on Reed-Muller canonic expansion is given that has many of these desirable properties. If only permanent stuck-at-0 (s-a-0) or stuck-at-1 (s-a-1) faults occur in a single AND gate or only a single EXCLUSIVE-OR gate is faulty, the following results are derived on fault detecting test sets for the proposed networks: 1) only (n/4) tests, independent of the function being realized, are required if the primary inputs are fault-free; 2) only 2n, additional inputs (which depend on the function realized) are required if the primary inputs can be faulty, where n, is the number of variables appearing in even number of product terms in the Reed-Muller canonical expansion of the function; and 3) the additional 2ne inputs are not required if the network is provided with an observable point at the output of an extra AND gate.

The Logical Design of a Digital Pseudorandom Noise Generator

A digital pseudorandom noise generator is described and analyzed. The generator output is predictable and deterministic in nature allowing precise calibration of the signal bandwidth occupancy. It is designed by use of a linear feedback shift register and exclusive-or (modulo-two) logic elements to produce maximum cycle sequences of 2N-1 where N is switch selectable. Modulo-two arithmetic and delay operators describe the generator by use of characteristic polynomials. Many independent noise sources are derived since there is a complete lack of correlation between outputs delayed a shift command apart. The auto-correlation function of the binary signal determines the time functions suitability as a random noise source. By use of this function the corresponding spectral density function is shown to approximate (sin x/x)2. By use of this function the bandwidth of the generator is shown to be directly proportional to the shift oscillator frequency. Two examples are given illustrating the use of the generator.