Excessive Power Dissipation Research Articles

ENNA: An Efficient Neural Network Accelerator Design Based on ADC-Free Compute-In-Memory Subarrays

Compute-in-memory (CIM) is an attractive solution for machine learning hardware acceleration since it merges computation directly into memory arrays, performing parallel multiply-and-accumulate (MAC) operations. The primary challenge in the reported CIM designs is the analog-to-digital converters (ADCs) that digitize analog MAC values for further processing, causing accuracy loss, excessive power dissipation, latency penalty, and area overhead. In this work, we propose ENNA, a novel CIM architecture based on an ADC-free sub-array design, implementing inter-array data processing in an analog manner. A lightweight input encoding scheme based on pulse-width modulation (PWM) is proposed to improve the throughput. We taped-out a prototype macro and validated the proposed ADC-free RRAM array design in TSMC 40nm process. Based on the measured silicon data, we explore the system-level performance with a partition between analog and digital processing at a level higher than the sub-array. The evaluation results show that the proposed accelerator can achieve 73.6~86.4 TOPS/W energy efficiency and 2.3~7 TOPS throughput (normalized to binary operation) tested on various DNN models. Furthermore, we project the proposed design using a heterogeneous 3D integration (H3D) scheme, showing a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$3\times \sim 37\times $ </tex-math></inline-formula> throughput improvement depending on different tasks and ~50% reduced area overhead compared to 2D design.

(Invited) Achieving Lower Power Logic Using P-Type Metal Oxide Thin Film Transistors

The excellent performance of n-channel thin film transistors (TFTs) based on amorphous oxide semiconductors has allowed integrated circuits based on NMOS logic to be successfully realized. However, future development will require CMOS logic to avoid excessive power dissipation and therefore p-channel TFTs are needed. Thin film p-type oxide semiconductors are rarely amorphous, and their microstructure has a significant impact upon both hole mobility and off-state current. In silicon MOSFETs, it is possible to scale device geometry to compensate for the lower hole mobility relative to electron mobility, but in TFTs this results in an excessive off-state current in the p-channel TFT as the off-state current also scales with geometry, which is not true to the same degree in silicon MOSFETs. Using new scaling rules that account for the off-state current, it is possible to optimize p-channel TFTs to operate alongside n-channel TFTs to achieve low power CMOS logic.

Fabrication of surface ion traps with integrated current carrying wires enabling high magnetic field gradients

A major challenge for quantum computers is the scalable simultaneous execution of quantum gates. One approach to address this in trapped ion quantum computers is the implementation of quantum gates based on static magnetic field gradients and global microwave fields. In this paper, we present the fabrication of surface ion traps with integrated copper current carrying wires embedded inside the substrate below the ion trap electrodes, capable of generating high magnetic field gradients. The copper layer’s measured sheet resistance of 1.12 mΩ/sq at room temperature is sufficiently low to incorporate complex designs, without excessive power dissipation at high currents causing a thermal runaway. At a temperature of 40 K the sheet resistance drops to 20.9 μΩ/sq giving a lower limit for the residual resistance ratio of 100. Continuous currents of 13 A can be applied, resulting in a simulated magnetic field gradient of 144 T m−1 at the ion position, which is 125 μm from the trap surface for the particular anti-parallel wire pair in our design.

IMPACT OF SENSOR DATA SAMPLING RATE IN GNSS/INS INTEGRATED NAVIGATION WITH VARIOUS SENSOR GRADES

Abstract. The fast-growing small-size equipment requires robust navigation with low power consumption and high positioning accuracy. However, as the mainstream robust navigation method against different environments, GNSS/INS causes excessive power dissipation. Considering downsampling is confirmed as a simple but efficient way to reduce energy usage, this paper focuses on the impact of sensor data sampling rate in GNSS/INS integrated navigation to give guidance for selecting proper GNSS/INS rates. Specifically, we first simulated data sequences with various sensor grades and then downsampled them into multiple sampling rates, followed by positioning accuracy evaluation. Experiment results have shown that GNSS interval caused more significant degradation of the navigation accuracy than the IMU rate. Meanwhile, the 5 sec GNSS interval with the 20 Hz IMU rate may be the most suitable for a power-accuracy trade-off solution in our experiments, which has a 16% reduction in positioning accuracy compared to the standard sampling rate combination (i.e, 1 sec GNSS interval and 200 Hz IMU sampling rate).

Hardware-Efficient Approximate Dividers for Image Processing in WSN Edge Devices

This paper proposes a hardware-efficient implementation of division, which is useful for image processing in WSN edge devices. For error-resilient applications such as image processing, accurate calculations can be unnecessary overhead, and approximate computing that obtains circuit benefits from inaccurate calculations is effective. Since there are studies showing sufficient performance with few bit operations, this paper proposes a combinational arithmetic circuit design of 16 bits or less. The proposed design is an approximate restoring division circuit implemented with a 2-dimensional array of 1-bit subtractor cells. The main drawback of such a design is the long “borrow-chain” that traverses all of the rows of the 2-dimensional subtractor array before a final stable quotient result can be produced, thereby resulting in a long delay and excessive power dissipation. This paper proposes two approximate subtractor cell designs, named ABSC and ADSC, that break this borrow chain: the first in the vertical direction and the second in the horizontal direction, respectively. The proposed approximate divider designs are compared with an accurate design and previous state-of-the-art designs based on accuracy and hardware overhead. The proposed designs have accuracy levels that are close to the best accuracy levels achieved by previous state-of-the-art approximate divider designs. In addition, the proposed ADSC design had the lowest delay, area, and power characteristics. Finally, the implementation of both proposed designs for two practical applications showed that both designs provide sufficient division accuracy.

Comprehensive investigation of various bypass diode associations for killer-SuDoKu PV array under several shading conditions

This paper investigates the electrical behavior of total cross tied (TCT), SuDoKu (SDK) and killer-SDK (KSDK) configurations under several shading conditions. Three different types of bypass diode (BD) arrangements for these PV arrays (PVAs) have been reported and the considered different BD arrangements are without BD (WBD), non-overlapped BD (NBD) and overlapped BD (OBD). Due to the occurrence of shading situations, the investigation of excess current for various BD based PVA configurations has been carried out. In the present work, maximum prospecting values of excess current for PV modules and arrays are also reported. Moreover, comparative analysis between WBD, NBD and OBD based PVA configurations has been presented using P–V and I–V characteristics. Also, investigation has been extended in terms of reduction of excess current, power dissipation, power improvement, energy savings and earnings. The presented results may be used as a suggestion for appropriate BD interconnection for the chosen PVA configurations. Overall, it is reported in this article that the NBD based KSDK PVA configuration is superior to WBD, OBD and NBD based TCT and SDK PVA configurations.

Sensitivity of heavy-ion-induced single event burnout in SiC MOSFET

The energy deposition and electrothermal behavior of SiC metal–oxide–semiconductor field-effect transistor (MOSFET) under heavy ion radiation are investigated based on Monte Carlo method and TCAD numerical simulation. The Monte Carlo simulation results show that the density of heavy ion-induced energy deposition is the largest in the center of the heavy ion track. The time for energy deposition in SiC is on the order of picoseconds. The TCAD is used to simulate the single event burnout (SEB) sensitivity of SiC MOSFET at four representative incident positions and four incident depths. When heavy ions strike vertically from SiC MOSFET source electrode, the SiC MOSFET has the shortest SEB time and the lowest SEB voltage with respect to direct strike from the epitaxial layer, strike from the channel, and strike from the body diode region. High current and strong electric field simultaneously appear in the local area of SiC MOSFET, resulting in excessive power dissipation, further leading to excessive high lattice temperature. The gate–source junction area and the substrate–epitaxial layer junction area are both the regions where the SiC lattice temperature first reaches the SEB critical temperature. In the SEB simulation of SiC MOSFET at different incident depths, when the incident depth does not exceed the device’s epitaxial layer, the heavy-ion-induced charge deposition is not enough to make lattice temperature reach the SEB critical temperature.

The Impact of CPU Voltage Margins on Power-Constrained Execution

CPUs typically operate at a voltage which is higher than what is strictly required, using voltage margins to account for process variability and anticipate any combination of adverse operating conditions. However, these worst-case scenarios occur rarely, if ever, thus the operating voltage is overly pessimistic resulting in excessive power dissipation which leads to decreased performance under power capping. In this paper, we investigate the impact of reducing voltage margins beyond the nominal level on the efficiency of CPU power capping mechanisms, for three commercial systems, two Applied Micro ARMv8 micro-servers (X-Gene2 and X-Gene3) and an Intel x86-64 (Xeon E3). We show that CPU power capping at reduced voltage margins compared with Intel’s RAPL and Dynamic Frequency Scaling (DFS) mechanisms results in performance improvement by up to 64 and 24 percent on average, respectively. In combination with state-of-the-art thread packing, the reduction of CPU voltage margins results in 36, 33 and 27 percent performance improvement compared with RAPL and DFS for the Xeon E3 and the X-Gene processors, respectively. Also, we validate the robustness of our approach with a set of long-running experiments and show that significant energy gains can be achieved even when considering the cost of checkpointing and recovery in large-scale systems.

Dynamic Reliability Management for FPGA-Based Systems

Radiation tolerance in FPGAs is an important field of research particularly for reliable computation in electronics used in aerospace and satellite missions. The motivation behind this research is the degradation of reliability in FPGA hardware due to single-event effects caused by radiation particles. Redundancy is a commonly used technique to enhance the fault-tolerance capability of radiation-sensitive applications. However, redundancy comes with an overhead in terms of excessive area consumption, latency, and power dissipation. Moreover, the redundant circuit implementations vary in structure and resource usage with the redundancy insertion algorithms as well as number of used redundant stages. The radiation environment varies during the operation time span of the mission depending on the orbit and space weather conditions. Therefore, the overheads due to redundancy should also be optimized at run-time with respect to the current radiation level. In this paper, we propose a technique called Dynamic Reliability Management (DRM) that utilizes the radiation data, interprets it, selects a suitable redundancy level, and performs the run-time reconfiguration, thus varying the reliability levels of the target computation modules. DRM is composed of two parts. The design-time tool flow of DRM generates a library of various redundant implementations of the circuit with different magnitudes of performance factors. The run-time tool flow, while utilizing the radiation/error-rate data, selects a required redundancy level and reconfigures the computation module with the corresponding redundant implementation. Both parts of DRM have been verified by experimentation on various benchmarks. The most significant finding we have from this experimentation is that the performance can be scaled multiple times by using partial reconfiguration feature of DRM, e.g., 7.7 and 3.7 times better performance results obtained for our data sorter and matrix multiplier case studies compared with static reliability management techniques. Therefore, DRM allows for maintaining a suitable trade-off between computation reliability and performance overhead during run-time of an application.

Magneto-electric antiferromagnetic spin–orbit logic devices

As electronic integrated circuits are scaled to ever smaller sizes, they run into the obstacle of excessive power dissipation. Spintronic devices hold the promise of alleviating this problem via improved energy efficiency. Research effort around a promising class of such devices based on antiferromagnetic materials and magnetoelectric switching is reviewed.

Eightdirectional Smart Reconfigurable Router Design for Network on Chip (Noc)

Designing N.O.C routers are based on performance parameters like power dissipation , energy , latency[2] .These performance are usually defined during design time.Taking under consideration all parameters as buffer size while designing lead to higher side of power dissipation and higher latency . Large size buffers lead to good performance but at the same time cause excess power dissipation. In this paper our aim is to design a router which supports heterogeneous data .

Enhanced Scan Segmentation for Low Power DFT

Excessive test power dissipation during scan testing of an SOC may cause reliability and yield concerns for the circuit under test (CUT). We propose an enhanced scan segmentation method using logic cluster controllability (LoCCo) technique for scan chain stitching to reduce test power efficiently. After LoCCo based scan stitching, since the trailing edge of scan chains contain very less switching transitions, we optimize the number of segments needed. This enables segmentation hardware reduction and still achieve lower power scan test compared to conventional method. Test cases prepared from ITC’99 standard circuits and industrial designs in 40nm CMOS and 28FDSOI technology were used for comparison. LoCCo based scan segmentation gave a shift power reduction of up-to 21.7% over conventional scan segmentation. Up-to 8.6%, shift power gain was observed even with 25% reduced segmentation when enhanced scan segmentation technique is used.

Power dissipation in the mixed metal-insulator state of self-heated VO2 single crystals and the effect of sliding domains

The mixed metal-insulator state in VO2 sets on within the current-controlled negative differential resistivity regime of I-V loops traced at ambient temperature. In this state, the stability of I(V) and/or spontaneous switching between initial and final steady states are governed by the load resistance RL in series with the sample. With increasing current (decreasing voltage), the power P = IV reaches a maximum (Pmax) and drops to a minimum (Pmin) along a path that depends on RL. For low enough RL, the ratio Pmax/Pmin may exceed by far the contrast in thermal emissivity from films of VO2 over the metal-insulator transition as reported in Kats et al. [Phys. Rev. X 3, 041004 (2013)]. The minimum is followed by a range of currents where the power increases with current. The return path overlaps the original path and continues towards backward switching. For a few samples, there is evidence from optical microscopy that the portion of the P(I) loop between Pmin and backward switching coincides with the range of currents where semiconducting domains slide within a metallic background. Damage induced in crystals by repeated I-V cycling suppresses domain sliding and flattens P(I) in the respective range of currents. This is consistent with the current dependent excess power dissipation being induced by the sliding domains.

Design of solar powered charging backpack.

This paper demonstrated a step by step process in designing a solar powered charging backpack that is capable of charging a mobile phone efficiently. A selection of existing products available on the market were reviewed and compared to ascertain the cost, size, and output capabilities. Next, the solar cell types and regulators were compared and their respective merits were also investigated. The charging system was then designed and tested before being integrated with the backpack. The results clearly showed that the system managed to charge the mobile phone. However, it was found that the excessive power dissipation has caused the linear regulator to generate significant heat.

Design of Solar Powered Charging Backpack

&lt;span&gt;This paper demonstrated a step by step process in designing a solar powered charging backpack that is capable of charging a mobile phone efficiently. A selection of existing products available on the market were reviewed and compared to ascertain the cost, size, and output capabilities. Next, the solar cell types and regulators were compared and their respective merits were also investigated. The charging system was then designed and tested before being integrated with the backpack. &lt;/span&gt;&lt;span lang="IN"&gt;The &lt;/span&gt;&lt;span&gt;results &lt;/span&gt;&lt;span lang="IN"&gt;clearly showed that the system managed to charge the mobile phone. However, it was found that the excessive power dissipation has caused the &lt;/span&gt;&lt;span&gt;linear regulator&lt;/span&gt;&lt;span lang="IN"&gt; to generate significant heat&lt;/span&gt;&lt;span&gt;.&lt;/span&gt;

Mitigation of Hot-Spots in Photovoltaic Systems Using Distributed Power Electronics

In the presence of partial shading and other mismatch factors, bypass diodes may not offer complete elimination of excessive power dissipation due to cell reverse biasing, commonly referred to as hot-spotting in photovoltaic (PV) systems. As a result, PV systems may experience higher failure rates and accelerated ageing. In this paper, a cell-level simulation model is used to assess occurrence of hot-spotting events in a representative residential rooftop system scenario featuring a moderate shading environment. The approach is further used to examine how well distributed power electronics converters mitigate the effects of partial shading and other sources of mismatch by preventing activation of bypass diodes and thereby reducing the chances of heavy power dissipation and hot-spotting in mismatched cells. The simulation results confirm that the occurrence of heavy power dissipation is reduced in all distributed power electronics architectures, and that submodule-level converters offer nearly 100% mitigation of hot-spotting. In addition, the paper further elaborates on the possibility of hot-spot-induced permanent damage, predicting a lifetime energy loss above 15%. This energy loss is fully recoverable with submodule-level power converters that mitigate hot-spotting and prevent the damage.

Timing Attack and Countermeasure on NEMS Relay Based Design of Block Ciphers

Scaling down CMOS technology results in excessive power dissipation issues. Nanoelectromechanical System (NEMS) relay technology is an alternative emerging solution that overcomes the power dissipation limitation of CMOS technology. However, despite its zero static leakage, NEMS relay technology suffers from large delay compared to CMOS technology. Binary Decision Diagram (BDD) based implementations of NEMS relay design targets minimizing the total delay. However, this implementation renders the timing delay of the output of a BDD input-dependent, which is a threat to security-critical applications, such as ciphers. In this paper, we analyze the impact of the input-dependent timing variation on the security of NEMS relay based cipher implementations. We present a generalized timing attack methodology, which is applicable to both Substitution Permutation Network (SPN) as well as Feistel block ciphers. We provide case studies on state-of-the-art SPN cipher candidate Advanced Encryption Standard (AES) and Feistel cipher candidates Camellia and DES. Our attack analysis shows that compact designs with single S-box implementation can be compromised, while parallel S-box implementations possess an inherent resistance against timing attacks. We also propose a cost-effective countermeasure which eliminates the input-dependent timing variation and thwarts all such timing attacks on BDD based implementations of NEMS relay design.

Free power dissipation from functional line integration

Power functional theory provides an exact generalisation of equilibrium density functional theory to non-equilibrium systems undergoing Brownian many-body dynamics. Practical implementation of this variational approach demands knowledge of an excess (over ideal gas) dissipation functional. Using functional line integration (i.e. the operation inverse to functional differentiation), we obtain an exact expression for the excess free power dissipation, which involves the pair interaction potential and the two-body, equal-time density correlator. This provides a basis for the development of approximation schemes.

Runtime buffer management to improve the performance in irregular Network-on-Chip architecture

This paper presents a heterogeneous adaptable router to reduce latency in irregular mesh Network-on-Chip (NoC) architectures. Regular mesh-based NoC architecture may become irregular due to variable sized IPs and needs new routing algorithms to ensure throughput. Therefore, an irregular NoC mesh is considered and an adaptive algorithm is used for routing. The performance measures such as throughput, latency, and bandwidth are defined at design time to guarantee the performance of NoC. However, if the application has to change its communication pattern, parameters set at design time (say buffer size) may result in large area and power consumption or increased latency. Routers with large input buffers improve the efficiency of NoC communication, but they incur excessive power dissipation and hardware overheads. Routers with small buffers reduce power consumption, but result in high latency. In the proposed NoC router, input buffers can be dynamically allocated, thereby, latency can be reduced. In a 4 × 4 irregular mesh NoC with a buffer depth of 4 slots, 20% reduction in latency and 9% increase in throughput are attained using dynamic buffer allocation. An 8 × 8 irregular mesh NoC with the proposed router is exposed to the synthetic traffics like uniform, bit complement, tornado and hotspot traffics and it offered a 30.42% reduction in overall average latency and 18.33% increase in overall saturation throughput. The proposed router outperformed the static router by 22.63% less average latency for E3S benchmark applications. For the same performance, maximum of 55% reduction in buffer requirement and 53% less power consumption is achieved.

Analog Domain Signal Processing-Based Low-Power 100-Gb/s DP-QPSK Receiver

Coherent techniques are expected to be used to meet the demand for higher data rates in short-reach optical links in the near future. Digital coherent receivers used for long haul applications are not suitable for short-reach links because of excessive power dissipation, size, and cost. The power consumption, size, and cost of the receiver can be drastically reduced by processing signals in the analog domain itself. A 100 Gb/s dual-polarization quadrature phase-shift keying receiver that uses analog domain signal processing is presented. The receiver, designed in 130-nm BiCMOS technology, consumes 3.5 W of power. Simulations show bit error rates of less than $10^{-3}$ in the presence of dispersion up to 160 ps/nm, laser linewidths of up to 200 kHz, and a frequency offset of 100 MHz between the transmitter and the receiver lasers.