Excess Loop Delay Research Articles

On the design of high-performance wide-band continuous-time sigma-delta converters using numerical optimization

Continuous-time (CT) sigma-delta (/spl Sigma//spl Delta/) modulators are growing increasingly popular in wide-band analog-digital conversion. High orders of quantization noise shaping, and multibit quantizers, are used to compensate for the low oversampling ratios in wide-band applications. These, however, add circuit complexities and excess loop delay that are detrimental to the /spl Sigma//spl Delta/ control loop. This paper presents an exact mathematical analysis technique, based on the CT-discrete time equivalence, that can take these effects into account. A design-by-optimization approach based on that analysis is used to compensate for these effects, avoid intractability issues and to gain flexibility in the design. It is also shown that it is advantageous not to fix the position of the quantization noise-shaping zeros in the signal band.

High-Speed Continuous-Time Subsampling Bandpass AD Modulator Architecture Employing Radio Frequency DAC

This paper proposes a continuous-time bandpass ΔΣAD modulator architecture which performs high-accuracy AD conversion of high frequency analog signals and can be used for next-generation radio systems. We use an RF DAC inside the modulator to enable subsampling and also to make the SNDR of the continuous-time modulator insensitive to DAC sampling clock jitter. We have confirmed that this is the case by MATLAB simulation. We have also extended our modulator to multi-bit structures and show that this alleviates excess loop delay problems.

Return to-zero feedback insertion in a continuous time Delta-Sigma modulator for excess loop delay compensation

Excess loop delay in continuous time (CT) Delta-Sigma modulators (DSM), as a result of the limited DAC response time, leads to SNR degradation so that the optimal tuning of the system will be impossible. In order to solve this problem, this paper proposes a novel return to-zero feedback insertion method. To verify the analytical results extracted in this paper, a second order CT DSM is simulated.

Sixth-order programmable bandwidth bandpass sigma–delta modulator implemented with transmission lines

An implementation of a sixth-order bandpass continuous time sigma–delta modulator using transmission lines is presented. A single tuning coefficient allows the exchange of resolution and bandwidth in this modulator, owing to the use of a two path transformation that exploits the similarity between transmission line modulators and discrete time modulators. The modulator tolerates two clock cycles of excess loop delay and a high clock jitter.

A Continuous-Time>tex<$Sigma Delta $>/tex<Modulator With 88-dB Dynamic Range and 1.1-MHz Signal Bandwidth

This paper presents the design and experimental results of a continuous-time /spl Sigma//spl Delta/ modulator for ADSL applications. Multibit nonreturn-to-zero (NRZ) DAC pulse shaping is used to reduce clock jitter sensitivity. The nonzero excess loop delay problem in conventional continuous-time /spl Sigma//spl Delta/ modulators is solved by our proposed architecture. A prototype third-order continuous-time /spl Sigma//spl Delta/ modulator with 5-bit internal quantization was realized in a 0.5-/spl mu/m double-poly triple-metal CMOS technology, with a chip area of 2.4 /spl times/ 2.4 mm/sup 2/. Experimental results show that the modulator achieves 88-dB dynamic range, 84-dB SNR, and 83-dB SNDR over a 1.1-MHz signal bandwidth with an oversampling ratio of 16, while dissipating 62 mW from a 3.3-V supply.

Continuous-time sigma-delta modulators with reduced timing jitter sensitivity based on time delays

A novel continuous time sigma-delta modulator architecture is presented. This architecture employs a noise shaping filter based on time delays, which allows a high speed hardware implementation with transmission lines. This architecture is less sensitive to clock jitter and excess loop delay than the equivalent continuous time modulators based on integrators.

A Reduced Delay Method for Improving the Performance of Sigma-Delta Analog-to-Digital Converters (ADC)

Excess loop delay in a continuous-time switched-current ΣΔ modulator causes a stability problem and degrades the modulator's dynamic range. This paper presents a simple and effective way to reduce the loop delay and improve the modulator's performance. The loop delay of the ADC is reduced by feeding the “predicted next state” to the comparator. With reduced loop delay, a larger loop gain is allowed without a stability problem, and hence, the dynamic range of the ADC is improved. A new circuit architecture to realize a second-order modulator with this method is also presented. From the simulation result, the new architecture shows a 6–10 dB improvement in dynamic range for a second-order ΣΔ modulator.

Excess loop delay in continuous-time delta-sigma modulators

Continuous-time (CT) delta-sigma modulators (/spl Delta//spl Sigma/M's) suffer from a problem not seen in discrete-time (DT) designs, that of excess loop delay: nonzero delay between the quantizer clock edge and the time when a change in output bit is seen at the feedback point in the modulator. This paper analytically shows how such delay affects the equivalence between the CT modulator loop filter and its DT counterpart. The effect of this delay on modulator dynamic range is studied through simulation for the standard double-integration (low pass) CT modulator and its equivalent fourth-order f/sub s//4 band pass circuit. For the first time, the results are extended to higher order low-pass and bandpass designs, as well as multibit designs. Methods for alleviating the performance loss caused by excess loop delay are also discussed.