Excellent Threshold Voltage Research Articles

Design optimization of wide-gate swing E-mode GaN HEMTs with junction barrier Schottky gate

To increase the gate swing, a GaN-based high-electron-mobility transistor with a junction barrier Schottky gate (JBS-HEMT) was proposed. Compared to conventional p-GaN Schottky gate HEMTs (Conv-HEMT), the high electric field at the surface is transferred to the pn junction inside the body, and the extended depletion region of the pn junction shields the surface Schottky contact interface for the JBS-HEMT. After fitting the model to the reported device, the proposed JBS-HEMT was simulated and optimized using the Sentaurus TCAD tool. The simulation results of the optimized JBS-HEMT demonstrate a high gate breakdown voltage (17.6 V), which is 158.5% higher than the gate breakdown voltage of the Conv-HEMT (11.1 V) and a lower gate leakage current of six orders of magnitude than the Conv-HEMT at the gate-to-source voltage of 10 V. The proposed JBS-HEMT exhibits a positive threshold voltage (1.68 V) and excellent threshold voltage stability, and the maximum threshold voltage drift of the JBS-HEMT (+0.237 V) is smaller than that of the Conv-HEMT (−0.714 V) under gate stress conditions. The peak transconductance of the JBS-HEMT (186 mS mm−1) at athe drain-to-source voltage of 10 V showed almost no reduction compared to the Conv-HEMT (189 mS mm−1), which solves the problem of decreased transconductance capability of the reported GaN HEMT with a p-n junction gate (PNJ-HEMT). It was confirmed that the JBS-HEMT has excellent gate stability and potential for power electronics applications.

Simulation based analysis of HK-Ge-Step-FinFET and its usage as inverter & SRAM

This paper deals with comparative simulation of High-k dielectrics -Germanium Step FinFET (HK-Ge-Step-FinFET) device with reference Step FinFET. For the first time we have investigated the impact of various dimensional parameters like oxide thickness tox, gate length Lg, drain bias voltage Vds on the performance of Proposed and Reference FinFET devices. These FinFET structures have been designed and simulated in Sentaurus TCAD and Cadence Virtuoso. The electrical parameters such as current ratio ION/IOFF, Sub-threshold Swing SS , Drain Induced Barrier Lowering (DIBL), threshold voltage Vth, gate capacitance, intrinsic delay and transconductance are extracted at 10 nm gate length. It is noticed that there is a significant improvement of 28 times and 23 times in ION for proposed device over reference FINFET at Vds = 1 V and Vds = 0.5 V respectively, improvement in ION/IOFF ratio from 8.05 × 108 to 6.65 × 1010, SS of 63.21 mV/decade to 61.5 mV/decade and excellent threshold voltage of 0.18 V in proposed FinFET. The characteristics of the proposed SRAM cell including, static noise margin (SNM), read/write delay, and subthreshold leakage power, are compared with the conventional 6 T SRAM cells. It is reported that the FinFET SRAM cell has RSNM, HSNM, and WNM of 285 mV, 360 mV, and 302 mV, respectively, at Vds = 1 V. Furthermore, the suggested device-based SRAM cell outperforms traditional SRAM cells at 1.0 V in terms of read noise margin, hold noise margin, and write noise margin, as well as leakage power. Thus, it may prove to be a viable option for lowering leakage components, making it effective for low-power and high-performance inverter and SRAM cell design in the nanoscale regime.

(Invited) Highly Stable Self-Aligned Top-Gate Indium Gallium Zinc Oxide Thin-Film Transistors for High-Resolution OLED TV and Mobile Displays

Highly stable self-aligned coplanar top-gate InGaZnO (IGZO) thin-film transistors (TFTs) with excellent threshold voltage (Vth) uniformity are developed by optimizing gate insulator film properties and controlling oxygen/hydrogen diffusion into IGZO channel. The TFTs do not show notable negative Vth shift and Vth non-uniformity from channel length 10 µm down to 3 µm. The TFTs also show no notable Vth shift during a humidity test in a chamber at 85°C/85% after deposition of passivation layers or even after 1-µm-thick thin-film encapsulation (TFE) SiNx layer on the top of the passivation layer due to the high quality/low hydrogen 2nd SiNx passivation layer deposited on the top of 1st SiOx passivation layer.

Excellent Uniformity and Reliability Top‐Gate Self‐Aligned IGZO TFTs with Cu Electrode

A top‐gate self‐aligned oxide amorphous indium‐gallium‐zinc‐oxide (a‐IGZO) thin‐film transistor (TFT) was examind for active matrix organic light‐emitting diode (AMOLED) display. The device exhibited robust device performance, such as excellent threshold voltage uniformity, high mobility, and good gate bias stress stabilities. Furthermore, remarkable short channel characteristics were achieved

62‐1: Invited Paper: Highly Stable Self‐Aligned Coplanar InGaZnO Thin‐Film Transistors and Investigation on Effective Channel Length†

Highly stable top‐gate InGaZnO (IGZO) thin‐film transistors (TFTs) with excellent threshold voltage (Vth) uniformity are developed by optimizing gate insulator film properties and controlling oxygen/hydrogen diffusion into IGZO channel. The TFTs do not show notable negative Vth shift and Vth non‐uniformity from channel length 10 µm down to 3 µm.

Fabrication of High-Uniformity and High-Reliability Si3N4/AlGaN/GaN MIS-HEMTs With Self-Terminating Dielectric Etching Process in a 150-mm Si Foundry

A novel early gate dielectric AlGaN/GaN metal–insulator–semiconductor high-electron-mobility transistors (MIS-HEMTs) process is reported. With the high-quality Si3N4 dielectric by low-pressure chemical vapor deposition and damage free, self-terminating passivation layer etching at the gate area, the MIS-HEMTs on 150-mm Si substrate demonstrate excellent output performance and good uniformity. The interface trap density between the gate insulator and the barrier layer is as low as $2 \times 10^{{12}}{\mathrm {cm}}^{- {2}}\,\,\cdot \,\,{\mathrm {eV}}^{- {1}}$ extracted by the conductance method. The MIS-HEMT fabricated on the wafer delivers an extremely small gate leakage current of 10−9 mA/mm and a high ${I}_{\mathrm{\scriptscriptstyle {ON}}}/{I}_{{\mathrm{\scriptscriptstyle {OFF}}}}$ ratio of 1011. The subthreshold swing (SS) is around 80 mV/dec, and the saturated output current density is 750 mA/mm. The dynamic on-resistance increases about 42% at a quiescent drain bias of 600 V. The ${V}_{ {th}}$ shift is −0.63 and −0.89 V at a high temperature of 200 °C and negative gate-bias stress of −25 V, respectively, indicating a comparable stability with the state-of-the-art MIS-HEMTs. An excellent threshold voltage and SS uniformity ( $ {1} - \sigma /\mu)$ with the value of 94.5% and 95.2% are achieved on the 150-mm wafer.

4H-SiC V-Groove Trench MOSFETs with Low Specific On-State Resistance and High Reliability

1. Introduction Silicon Carbide (SiC) MOSFETs have attracted attention as high performance power devices due to their unique material properties such as wide bandgap, high electric field strength, high saturation velocity, and high thermal conductivity. However, the obtained channel mobility (field effect mobility) of 5-30 cm2V-1s-1 is substantially lower than the bulk mobility (1000 cm2V-1s-1) because of the high SiO2/SiC interface state density (D it). Thus, the reduction of the interface states is the key issue in the development of SiC MOS devices. In order to improve the channel mobility, we proposed MOSFETs fabricated on the 4H-SiC(0-33-8) face which has the lower interface state density than the 4H-SiC(0001) face. In fact, a high channel mobility of 80 cm2V-1s-1was attained by using the superior MOS properties. 2. Device structure of the V-groove Trench MOSFETs We have proposed the V-groove trench MOSFETs (VMOSFETs) with the 4H-SiC{0-33-8} face as the trench sidewalls for the channel region. Furthermore, the buried p+regions below the trench bottom corner and the thick oxide layer at the trench bottom were employed. Both of these contribute to alleviate the electric field in the trench bottom oxide layer in order to realize high breakdown voltage over 1200V without gate oxide breakdown. The schematic cross-sectional view of the VMOSFET is shown in Fig.1 3. Device Fabrication Process The SiC epitaxial layer was grown on 4o off-axis n-type 4H-SiC(000-1) substrate by chemical vapor deposition (CVD). The n+, p+ and p-body regions were formed by P and Al ion implantation. The channel length is 0.6 mm along the trench sidewall. Thereafter, the V-groove structures with the 4H-SiC{0-33-8} sidewalls were fabricated through the thermochemical etching process in Cl2 ambient using a SiO2 mask. Gate oxide was thermally grown, followed by nitridation and post oxidation annealing (POA), resulting in an oxide thickness of about 50 nm. The source and drain contact metal were fabricated and alloyed at the temperature of 1000oC. The Al electrode was deposited on the alloyed contact metal. 4. Results and Discussion Figure 2 shows the static device characteristics. Figure 2 (a) shows the on-state forward I D-V DS characteristics of the VMOSFETs. The measured specific on-resistance in accordance with the active area size is 2.0 mΩ cm2 (V GS = 20 V, V DS = 1 V) at room temperature. As shown in fig. 2 (b), the breakdown voltage of above 1200 V is obtained. Figure 3 shows the on-state forward I D-V DScharacteristics of the VMOSFETs of 6.0-mm-square chip. A large current of 150 A is obtained with a single chip.Figure 4 shows the temperature dependence of the specific on-resistance of the V MOSFET and a planar DMOSFET on 4o off 4H-SiC(0001). The specific on-resistance of the DMOSFET decreases from -50oC to 0oC as expected due to the thermal emission of trapped electrons near oxide interfaces. In contrast, the specific on-resistance of the VMOSFET monotonically increases from -50oC to 175oC. This result shows that a drift resistance in the epitaxial layer of the VMOSFETs is more dominant than a channel resistance because of the low interface state density (D it) of SiO2/4H- SiC(0-33-8).We evaluated the stability of the threshold voltage of the VMOSFETs. Figure 5 shows the High Temperature Gate Bias (HTGB) test results of the VMOSFETs under a gate bias of +20V or -10V at 175oC. The threshold voltage of the VMOSFETs was 3 V (V DS = 10 V, I D = 5 mA cm-2). After the 1000 hour test, the threshold voltage shifts were only less than ±0.2 V of both positive and negative gate bias tests. These results show the excellent threshold voltage stability of the VMOSFETs for long term operation. This is considered due to the low interface trap density of SiO2/4H-SiC(0-33-8). 5. Summary The originally structured 4H-SiC V-groove trench MOSFET with the {0-33-8} face for the trench sidewalls has been proposed. The inclined trench structure can be fabricated by the thermochemical chlorine etching, resulting in the smooth low damage surface. Consequently, the low specific on-state resistance of the VMOSFET is attained. Thus a large current of 150A was obtained with a single 6-mm-square chip. Also High Temperature Gate Bias (HTGB) test was performed under a gate bias of +20V or -10V at 175oC. After the 1000 hour test, the threshold voltage kept stable with only less than ±0.2 V voltage shifts. Due to these advantages, the VMOSFETs are suitable for use in automotive electronic devices and the regenerative energy generation system applications. Figure 1

Investigation of asymmetric effects due to gate misalignment, gate bias and underlap length in III–V heterostructure underlap DG MOSFET

In the present work, we investigate the influence of asymmetry in III–V heterostructure underlap DG MOSFET caused by back gate movement, back gate voltages and drain side underlap length. The device has narrowband In0.53Ga0.47As and wideband InP layers in the channel, along with high-K Al2O3 as the gate dielectric. The 2D Sentaurus TCAD simulations are done using drift diffusion model and interface traps are considered. The simulation model is calibrated with the previous reported experimental results. For the same gate misalignment value, back gate shift toward drain (BG_D) resulted in a lower DIBL, Ioff and Delay, than back gate shift towards source (BG_S). Conversely, BG_S results in lower SS, higher Ion and Ion/Ioff ratio. Excellent threshold voltage controllability, reduced delay, reduced energy delay product, higher Ion/Ioff ratio are achieved by varying back gate voltage. Varying drain underlap reduces DIBL, SS, Delay, Ioff and increases Vt and Ion/Ioff ratio. Thus, application specific optimized device parameters can be achieved with asymmetrical device structure, asymmetrical gate bias or its combination.

Organic Thin-Film Transistors with Low Threshold Voltage Variation on Low-Temperature Substrates

We demonstrate a systematic approach to optimize pentacene-based thin-film transistors using a photolithographic-based process to integrate basic circuit components such as organic-based diodes, transistors, and capacitors to fabricate circuits such as inverters, ring oscillators, current mirrors, and rectifiers for radio-frequency identification and flexible display applications. Excellent threshold voltage control among transistors is demonstrated with a 2× reduction in threshold voltage (V T ) standard deviation. Our integration methodology includes a seven-mask photolithography process that incorporates several discrete devices built with pentacene as the semiconductor and parylene as the gate dielectric and interlevel dielectric. In addition, the maximum temperature for all processes is 120°C.

0.2-μm fully-self-aligned Y-shaped gate HJFET's with reduced gate-fringing capacitance fabricated using collimated sputtering and electroless Au-plating

This paper reports on new fully-self-aligned gate technology for 0.2-/spl mu/m, high-aspect-ratio, Y-shaped-gate heterojunction-FET's (HJFET's) with about half the external gate-fringing capacitance (C/sub f//sup rext/) of conventional Y-shaped gate HJFET's. The 0.2-/spl mu/m Y-shaped gate openings are realized by anisotropic dry-etching with stepper lithography and SiO/sub 2/ sidewall techniques instead of electron beam lithography. By introducing WSi-collimated sputtering and electroless gold-plating techniques for the first time, we have developed a high-aspect-ratio, voidless and refractory Y-shaped gate-electrode without the need for mask alignments. A fabricated 0.2-/spl mu/m gate n-Al/sub 0.2/Ga/sub 0.8/As/In/sub 0.2/Ga/sub 0.8/As HJFET shows very small current saturation voltage of 0.25 V, marked gm/sub max/ of 631 mS/mm with 6-V gate-reverse breakdown voltage, and excellent threshold voltage uniformity of 9 mV. Also, the improved rf-performance such as f/sub T/=71 GHz and f/sub max/=120 GHz is realized even with the passivation for the high-aspect-ratio gate-structure with reduced C/sub f//sup rext/. The developed technology based upon a fully-self-aligned and an all-dry-etching process provides higher performance and uniformity, thus it is very promising for high-speed and low-power-consumption digital and/or analog IC's/LSI's.

0.3-μm gate-length enhancement mode InAlAs/InGaAs/InP high-electron mobility transistor

The fabrication and performance of ultra-high-speed 0.3-/spl mu/m gate-length enhancement-mode high-electron-mobility transistors (E-HEMT's) are reported. By using a buried platinum-gate technology and incorporating an etch-stop layer in the heterostructure design, submicron E-HEMT devices exhibiting both high-threshold voltages and excellent threshold voltage uniformity have been achieved. The devices demonstrate a threshold voltage of +171 mV with a standard deviation of only 9 mV. In addition, a maximum DC extrinsic transconductance of 697 mS/mm is measured at room temperature. The output conductance is 22 mS/mm, which results in a maximum voltage gain (g/sub m//g/sub 0/) of 32. The devices show excellent RF performance, with a unity current-gain cutoff frequency (f/sub t/) of 116 GHz and a maximum frequency of oscillation (f/sub max/) of 229 GHz. To the best of the authors' knowledge, these are the highest reported frequencies for lattice-matched E-HEMT's on InP.

Tantalum-gate thin-film SOI nMOS and pMOS for low-power applications

The threshold voltages of thin-film fully-depleted silicon-on-insulator (FDSOI) nMOS and pMOS have been controlled by employing tantalum (Ta) as the gate materials. Ta-gate FDSOI MOSFET's have excellent threshold voltage control for 1.0 V application on low impurity concentration SOI layers in both nMOS and pMOS. The low-temperature processing after the gate oxidation step leads to good on/off characteristics in Ta-gate SOI MOSFET's because of no reaction between Ta gate electrode and SiO/sub 2/ gate insulator. This technology makes it possible to drastically decrease the number of the process steps for CMOS fabrication, because the same gate material is available for both nMOS and pMOS.

Fully self-aligned AlGaAs/GaAs heterojunction bipolar transistors for high-speed integrated-circuits application

Structure optimization, uniformity consideration, and high-speed circuit performance for an AlGaAs/GaAs heterojunction bipolar transistor (HBT) are described. The HBT is fabricated in a fully self-alignment manner using only a single photoresist mask for achieving submicrometer-dimension devices, and, thus reducing parasitic elements. The fabricated HBT's exhibit excellent threshold voltage deviation sigma V/sub BE/=2 mV on a 2-in wafer, a CML gate propagation delay time tau /sub pd/=9.5 ps, and a toggle frequency f/sub tog/=13.3 GHz for a CML divide-by-two frequency divider. >

Prospects for GaAs-on-Si LSI Circuits

ABSTRACTThis paper will review some of the recent progress in GaAs-on-Si devices and circuits, and discuss the issues involved in realizing large scale ICs in GaAs-on-Si wafers. With a recent success in fabricating 1 Kbit static RAMs in GaAs-on-Si wafers, it has become apparent that this material is indeed acceptable for LSI complexity circuits. GaAs MESFETs fabricated using a standard process show an excellent threshold voltage uniformity which is comparable to that for bulk GaAs devices. GaAs bipolar devices on GaAs-on-Si have realized a gain of 25 which is the highest reported for bipolar devices in GaAs-on-Si material. Bipolar ring oscillators and 256-bit ROMs consisting of more than 100 gates have also been realized. In spite of these successes, however, there are numerous issues that need to be solved before this material becomes practical.

Application of a solution proximity annealing technique for fabrication of ion-implanted GaAs integrated circuits

A technique for capless annealing of ion-implanted GaAs, using an arsenic-saturated solution of Sn and Ga in close proximity to the wafer, has been applied to the fabrication of GaAs integrated circuits. The IC processing technology utilizes a self-aligned T-shaped refractory gate approach for the fabrication of both enhancement- and depletion-mode MESFET's. Using the solution proximity annealing technique, excellent threshold voltage uniformities (standard deviation = 26 mV) have been obtained for enhancement-mode devices using commercial substrates. This process technology has resulted in the fabrication of divide-by-16 circuits in both SDFL and DCFL logic implementations, as well as enhancement/depletion (E/D) ring oscillators (L <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">g</inf> = 2 µm) with propagation delays as low as 45 ps/gate and concomitant power consumptions of 2 mW/gate. This technique can also be applied, by suitable choice of the solution constituents, to capless annealing of other III-V semiconductors such as InP and GaInAs.