Ethernet Transceiver Research Articles

100-Gb/s and beyond transceiver technologies

First generation 100-Gb/s Ethernet transceiver architecture, standards and components are presented. Second generation 100-Gb/s architecture, standards and enabling photonic integration component technology are then described. Extension of this technology is shown to support cost effective 400-Gb/s Ethernet interfaces. The next OTN data rate then also becomes 400-Gb/s to efficiently carry a 400-Gb/s Ethernet payload. Further data rate increase to ⩾1-Tb/s is not possible with existing technology, and will require completely new technology R&D effort.

SIGNAL CONSTELLATION DISTORTION AND BER DEGRADATION DUE TO HARDWARE IMPAIRMENTS IN SIX-PORT RECEIVERS WITH ANALOG I/Q GENERATION

Since its introduction in 1994 direct conversion sixport receivers have attracted a considerable attention at microwave frequencies, with most recent work focusing on the so called sixport receivers with analog I/Q generation. Besides its applications at microwave frequencies, six-port receivers with I/Q regeneration play a crucial role in the optical communications field, as they are the most promising candidates for optical coherent receivers that are being developed for 100 Gigabit Ethernet transceivers. In this paper we analytically model the influence of six-port junction hardware impairments on receiver performance. New analytical expressions are developed which give geometrical interpretation of signal constellation distortion due to hardware impairments and allow for the definition of several interesting figures of merit. Closed formulas are also proposed to analytically calculate BER degradation, under AWGN conditions, from these figures of merit. Finally, the proposed formulas are validated by means of simulation, and it is shown that they can be of practical interest to set the specifications of the six-port junction components.

A Low-Complexity Hybrid LDPC Code Encoder for IEEE 802.3an (10GBase-T) Ethernet

This paper presents a novel hybrid encoding method for encoding of low-density parity-check (LDPC) codes. The design approach is applied to design 10-Gigabit Ethernet transceivers over copper cables. For a specified encoding speed, the proposed method requires substantially lower complexity in terms of area and storage. Furthermore, this method is generic and can be adapted easily for other LDPC codes. One major advantage of this design is that it does not require column swapping and it maintains compatibility with optimized LDPC decoders. For a 10-Gigabit Ethernet transceiver which is compliant with the IEEE 802.3 an standard, the proposed sequential (5-Parallel) hybrid architecture has the following implementation properties: critical path: (log2(324) + 1)Txor + Tand, number of XOR gates: 11 056, number of and gates: 1620, and ROM storage: 104 976 bits (which can be minimized to 52 488 bits using additional hardware). This method achieves comparable critical path, and requires 74% gate area, 10% ROM storage as compared with a similar 10-Gigabit sequential (5-parallel) LDPC encoder design using only the G matrix multiplication method. Additionally the proposed method accesses fewer bits per cycle than the G matrix method which reduces power consumption by about 82%.

Low-Complexity Echo and NEXT Cancellers for High-Speed Ethernet Transceivers

Gigabit and multigigabit transceivers require very long adaptive filters for echo and near-end crosstalk (NEXT) cancellation. Implementation of these filters not only occupies large silicon area but also consumes significant power. These problems become even worse when the Tomlinson-Harashima precoding (THP) technique is used in applications such as 10-Gigabit Ethernet over Copper (10 GBASE-T) as the input to the echo and NEXT cancellers is no longer a simple PAM-M signal. To reduce the complexity of these cancellers, in this paper, a novel method based on word-length reduction technique is proposed. The proposed design is derived by replacing the original input to the echo and NEXT cancellers with a finite-level signal, which is the sum of the input to the TH precoder and a finite-level compensation signal. Then, this modified input signal is recoded to have shorter word-length compared with the original input. Hence, the overall complexity can be reduced by using the proposed method. To further reduce the complexity of these cancellers, an improved design is proposed by exploiting the property of the compensation signal. Compared with the traditional design, the proposed echo and NEXT cancellers have exact input and do not suffer from the quantization problem, and thus they are more suitable for VLSI implementation. The proposed method can also be applied to design adaptive echo and NEXT cancellers with little modification. The performance evaluation is performed by simulations to verify the proposed design. It is shown that, by applying the proposed method to a 10 GBASE-T Ethernet system, the hardware complexity of echo and NEXT cancellers can be reduced by about 10.82% without performance loss, compared with the traditional design.

Timing Recovery for Backplane Ethernet

The dominant solutions for single-chip multi-port backplane Ethernet transceivers utilize a dual-loop design - a combination of a single master phase-locked loop (PLL) and multiple slave delay-locked loops (DLL). Each transmitter or receiver port has its own DLL, which delays or advances a copy of the master clock from the master PLL to generate its own clock signal for synchronization. The DLLs are typically implemented using current-mode logic phase interpolators. This paper presents an alternative solution to this synchronization problem. Instead of moving the sampling phase, timing recovery is done by changing the group delay of the receiver-side forward equalizer by rotating its tap coefficients. The standard least-mean-square algorithm is used for coefficient rotation. This solution is equivalent to a first-order PLL/DLL, which suffers from steady-state timing offset when there is a frequency offset between the transmitter and the receiver. However, the degradation in performance caused by a frequency offset is significantly reduced by using a coefficient-rotation digital-signal processor capable of detecting and reducing the offset. With a practical frequency accuracy specification of plusmn100 ppm, the improved performance can approach that of the PLL/DLL dual-loop solution.

High-performance, low-cost joint equalizer and trellis decoder for 1000BASE-T gigabit Ethernet transceiver

This article presents an M-algorithm (MA) decoder with 4 survival paths (MA4) for Institute of Electrical and Electronics Engineers (IEEE) 802.3ab 1000BASE-T gigabit Ethernet (GbE) transceiver. To fulfill the entire requirements, various methods were introduced to accelerate the MA4 decoder while retaining the desired high performance and low complexity. Optimized look-ahead architecture was employed to solve the critical path problem with minimal gate consumption. Symbol compression methods saved registers during pipeline stages. A sorting network accelerated the kernel sorting operation at low hardware cost by utilizing the special characteristics of MA4. Simulations and synthesis results show that the proposed decoder achieves 125 MHz clock frequency and 1 Gb/s throughput in 1.8 V 0.18 μm standard cell complementary metal-oxide-semiconductor (CMOS) process. It achieves additional 0.4 dB coding gain over 14tap parallel decision feedback decoder (PDFD) with 39% area reduction.

Joint AGC-Equalization Algorithm and VLSI Architecture for Wirelined Transceiver Designs

Traditional approaches of automatic gain control (AGC) involve estimating the average power or the peak amplitude over an extended time period, which results in high hardware complexity and a long processing time. Moreover, the accuracy of traditional approaches is seriously degraded by noise and intersymbol interference. In this paper, we propose a joint AGC and equalization (Joint AGC-EQ) scheme, in which the AGC circuitry comprises only one-tenth of the area of a traditional AGC. In addition, the total convergence time of the proposed Joint AGC-EQ is only half that of traditional blind equalization. The scheme is already silicon proven for the application of a Fast Ethernet transceiver using Faraday/UMC 0.18-mum cell libraries

Ethernet transmissions over large core polymer optical fibres: demonstration of an extended reach (425 m) LAN system

Optical community has expressed a wide consensus over the idea that 1 mm poly-methil-meta-acrilate step-index fibres (PMMA SI-POF) can be a good candidate in future domotic networks and in edge networks, that is in the last part of access networks, due to their better mechanical behaviour and lower installation and handling costs with respect to conventional 50/125 or 62.5/125 multi-mode glass fibres. Current applications are anyway limited by relatively low transmission performances: up to now, the best performing commercial Ethernet transceivers using PMMA SI-POF are able to reach at the most 200 m at 10 Mb/s or 70 m at 100 Mb/s, thereby keeping these fibres in the niche of very-short reach applications, such as in the automotive market. A Prototype of a media converter for fully compliant 10 Mb/s Ethernet transmissions over PMMA SI-POF experimentally demonstrated the feasibility of >400 m long link, this length may open new applications to PMMA SI-POF. The 425-m record distance presented here has been achieved by both introducing a proprietary protocol implemented over a field programmable gate array platform and by a careful selection of (commercial) optoelectronic components. The prototype is to be considered as a proof-of-concept that PMMA SI-POF can be introduced in new areas such as the last part of access/edge networks or datacom applications in industrial automation or aircrafts/ships cabling. The 400-m distance is, for instance, the specification of an Italian fibre to the home operator for the last part of its access network architecture

Co-design for an SoC embedded network controller

With the development of Ethernet systems and the growing capacity of modern silicon technology, embedded communication networks are playing an increasingly important role in embedded and safety critical systems. Hardware/software co-design is a methodology for solving design problems in processor based embedded systems. In this work, we implemented a new 1-cycle pipeline microprocessor and a fast Ethernet transceiver and established a low cost, high performance embedded network controller, and designed a TCP/IP stack to access the Internet. We discussed the hardware/software architecture in the forepart, and then the whole system-on-a-chip on Altera Stratix EP1S25F780C6 device. Using the FPGA environment and SmartBit tester, we tested the system's throughput. Our simulation results showed that the maximum throughput of Ethernet packets is up to 7 Mbps, that of UDP packets is up to 5.8 Mbps, and that of TCP packets is up to 3.4 Mbps, which showed that this embedded system can easily transmit basic voice and video signals through Ethernet, and that using only one chip can realize that many electronic devices access to the Internet directly and get high performance.

A 1.2-V-only 900-mW 10 gb ethernet transceiver and XAUI interface with robust VCO tuning technique

This paper describes the design and the implementation of a fully integrated 10 Gb Ethernet transceiver in a 0.13-/spl mu/m CMOS process using only a 1.2 V supply. A coarse control algorithm that combines a voltage range monitoring circuit with a frequency lock detector provides a robust operation against process, voltage, and temperature (PVT) variations for a VCO with a ring oscillator. With the use of a blind oversampling DPLL architecture, four channels of XAUI transceivers can share a single PLL, eliminating the clock synchronization problem between channels. Also, the total number of clock domains for the entire chip is reduced to three, making the integration of the XAUI with the 10G transceiver much simpler. The test chip consumes 898 mW from a 1.2 V supply.

Emcore acquires Molex for 10G market

Emcore has acquired Molex Inc’s 10 Gigabit (10G) Ethernet transceiver business, including assets, products, technology and IP related to Molex’s 10G Ethernet transceiver business, primarily focused on Xenpak and X2 form factor products, and located in Downers Grove, Illinois. Some 17 Molex employees will join Emcore. The business will become a part of Emcore’s Fiber Optics division and will initially continue to operate in a portion of Molex’s Downers Grove facility to be leased by Emcore Visit www.three-fives.com for the latest advanced semiconductor industry news

JDS Uniphase transceivers

JDS Uniphase today announced a new family of XFP MSA-compliant transceivers and extended its line of SFP MSA-compliant Fibre Channel and Ethernet transceivers for optical communications equipment manufacturers in the datacom market. The products are important for high speed LAN and SAN applications. “Of the various 10 Gb/s datacom designs, our customers are currently showing the greatest interest in the XFP standard, and we are the first of the major suppliers to offer an MSA-compliant product at 850 nm, which we believe is ideal for short reach, very high speed LAN and SAN applications,” said Don Bossi, president of JDS This is a short news story only. Visit www.three-fives.com for the latest advanced semiconductor industry news.

Multichannel bit error rate tester for fiber optic transceiver testing

I describe an inexpensive and portable method used to conduct bit error rate test measurements in an aircraft at altitude to measure susceptibility of gigabit fiber optic transceivers to ionizing radiation. This method uses a built-in test feature of Texas Instruments GigaBit Ethernet transceiver chips. During a 20 min flight at 39 000 ft altitude, none of the eight test channels using Finisar FTRJ-8519-1 fiber optic transceivers indicated any bit errors.

Demonstration of a small-form-factor WWDM transceiver module for 10-Gb/s local area networks

We demonstrate for the first time all key components for a small-form-factor (SFF) wide-wavelength-division-multiplexed (WWDM) transceiver module with four channels operating at a data rate of 3.125 GBd/channel giving an aggregate rate of 12.5 GBd. The key components that enable a SFF package include a compact injection-molded plastic demultiplexer and a compact transmitter optical subassembly. We report link results showing successful operation of these key components with transmission over 300 m of 62.5-μm core multimode fiber (MMF) and 10.5 km of single-mode fiber (SMF). These technologies enable highly-integrated WWDM 10-Gb Ethernet transceiver modules that support both MMF and SMF.

Preventing a "noisequake" [substrate noise analysis

Substrate noise analysis can identify potential problems in mixed-signal and RF designs. In this paper substrate noise analysis was described and the methodology used in Cadence's SeismIC tool, a 3D solver, was discussed in detail. Several results were presented to demonstrate the accuracy of substrate extraction. Good correlation was shown between SeismIC and the 2D solver, Medici, for two structures in a TSMC 0.18 μm process. The overall average error in magnitude of the impedance for the two structures was 1.4 dB. Excellent correlation was demonstrated between SeismIC and measured impedances. The average magnitude of error between simulations and measurements was 6.4%. Another example of comparison of SeismIC with silicon was shown for a mixer fabricated in 0.6 μm technology. Measured gain showed excellent correlation to that simulated using a circuit simulator, with a substrate annotated netlist computed using SeismIC extraction. The SeismIC simulation flow was demonstrated for an Ethernet transceiver chip containing one million devices. This example shows the utility of using substrate analysis in the debug phase of a design, the value of identifying the worst noise contributors for a given design, and using analysis in the design phase to optimize the noise immunity of a design.

Low-power equalizer architectures for high speed modems

In many DSP-based high-speed modem applications, such as broadband modems for high-speed Internet access to the home or gigabit Ethernet transceivers, channel equalization requires processing power so high that power consumption and clock speed become major design challenges. This article describes techniques to implement low-cost adaptive equalizers for ASIC implementations of broadband modems. Power consumption can be reduced using a careful selection of architectural, algorithmic, and VLSI circuit techniques. The derivation of a hybrid FIR filter structure is given that enables the designer to adjust both the speed and power consumption to suit an application. Furthermore, the architecture can be made programmable to target multiple applications in one piece of silicon while maintaining or even improving the efficiency of the architecture. Run-time techniques are shown that can minimize the power consumption for a given application or operating environment. In all cases, the power reduction techniques are supported by simulations and measurements made on a test integrated circuit.