Ethernet Frames Research Articles

Research on the Implement Mechanism of EPON VoD QoS Multicast Based on Utility

Non-guaranteed QoS and low benefit are essential problems when VoD runs in IP network.Based on network priority,mass SLA priority,as well as economic priority of multicast service of VoD in EPON,a QoS priority utility algorithm(utility priority)is introduced for multicast.When congestion is occurring,the network resources are re-allocated among multicast group according to their utility priority.This measure can not only reduce bandwidth requirement and packet loss,but also can increase bandwidths benefit by converging them on the higher value services.By turning disorderly and variable-length Ethernet frame into orderly and constant-length one,the delay jitter of VoD packet is reduced.The result of simulation well verifies its merits.

Flush Optimizations to Guarantee Less Transient Traffic in Ethernet Ring Protection

Ethernet ring protection (ERP) technology, which is defined in ITU-T Recommendation G.8032, has been developed to provide carrier grade recovery for Ethernet ring networks. However, the filtering database (FDB) flush method adopted in the current ERP standard has the drawback of introducing a large amount of transient traffic overshoot caused by flooded Ethernet frames right after protection switching. This traffic overshooting is especially critical when a ring provides services to a large number of clients. According to our experimental results, the traditional FDB flush requires a link capacity about sixteen times greater than the steady state traffic bandwidth. This paper introduces four flush optimization schemes to resolve this issue and investigates how the proposed schemes deal with the transient traffic overshoot on a multi-ring network under failure conditions. With a network simulator, we evaluate the performance of the proposed schemes and compare them to the conventional FDB flush scheme. Among the proposed methods, the extended FDB advertisement method shows the fastest and most stable protection switching performance.

Performance of 10 Gigabit Ethernet Using Commodity Hardware

In the prospect of employing 10 Gigabit Ethernet as networking technology for online systems and offline data analysis centers of High Energy Physics experiments, we performed a series of measurements on the performance of 10 Gigabit Ethernet, using the network interface cards mounted on the PCI-Express bus of commodity PCs both as transmitters and receivers. In real operating conditions, the achievable maximum transfer rate through a network link is not only limited by the capacity of the link itself, but also by that of the memory and peripheral buses and by the ability of the CPUs and of the Operating System to handle packet processing and interrupts raised by the network interface cards in due time. Besides the TCP and UDP maximum data transfer throughputs, we also measured the CPU loads of the sender/receiver processes and of the interrupt and soft-interrupt handlers as a function of the packet size, either using standard or ?jumbo? Ethernet frames. In addition, we also performed the same measurements by simultaneously reading data from Fibre Channel links and forwarding them through a 10 Gigabit Ethernet link, hence emulating the behavior of a disk server in a Storage Area Network exporting data to client machines via 10 Gigabit Ethernet.

Bridging the Digital Divide by Building and Developing Wireless Community Networks in Rural Areas of Sri Lanka

This paper discusses how new and emerging wireless technologies could be deployed together with Open Source product lines in expediting the propagation of the ICT know-how in the rural as well as the suburban areas of Sri Lanka. The intention of the authors is to showcase a blueprint for using newer and emerging viable communication technologies in the rural context. Current internet distribution networks generally rely on a permanent, fixed and largely wired infrastructure that is owned and often operated by large entities such as telecom operators or an Internet Service Provider. A relatively new and emerging technology is wireless Ethernet or wireless networking using the IEEE 802.11 standard. This standard encompasses the lower layers of the OSI model for transport of data as Ethernet frames using a spread spectrum based radio link. This technology opens the possibility of building a network without having the problems associated with, and the cost of putting some sort of physical transmission medium in the ground. Instead, antennas can be used to send and receive data using radio waves through free air. Due to the relative simplicity of the currently available commodity hardware that uses IEEE 802.11 technology it is relatively easy to build a local wireless community network in a community township. Using this network people can share resources among each other and, more importantly, it would facilitate the adaptation of a highly collaborative environment forgoing the language barriers, which is regarded as a major cause of the ethnic conflict in Sri Lanka. DOI: 10.4038/suslj.v6i1.1693 Sabaragamuwa University Journal, vol 6, no. 1, pp 106-115

Scaling Ethernet speeds to 100 Gbits/s and beyond

Dramatic growth in Internet Protocol (IP) traffic demand is driving the need for new high-bandwidth IP interfaces. Today, router-to-router and router-to-transport system connections using Ethernet interfaces are limited to 10 Gbits/s (10GE) or slower. Although techniques, such as link aggregation, allow a limited degree of extensibility beyond 10 Gbits/s, they are limited in terms of scalability, introduce additional complexity, and reduce throughput efficiency. Discussion now centers on defining an Ethernet architecture that meets the needs of carriers and is conducive to implementation by the switch and server vendors. In this paper, we consider aggregation at the physical layer (APL) as a means to reuse existing 10GE physical layers (PHYs), while offering interface scalability to 100 Gbits/s and beyond. With APL, aggregation is performed at the PHY, whereby full Ethernet frames are transmitted across the aggregated PHYs in a parallel fashion. This ensures equal utilization of all links and allows aggregate bandwidth between nodes to scale with each new link added. We have demonstrated the applicability of such an approach by implementing a 100 Gbits/s interface using off-the-shelf components and running it over a live 4,000 km backbone network of a tier-1 Internet service provider.

Efficient implementation of a frame aggregation unit for optical frame-based switching

Aggregating Ethernet frame or IP packet in large fixed-size frames allows for building scalable core network architectures. Classifying the arriving traffic based on destination core node information and quality of service parameters alleviates the need of performing table look-ups on packet basis. These advantages come at the cost of extra logic at the network egress, as regards implementation, and additional jitter due to the frame assembly process. This paper describes the efficient implementation of a frame aggregation unit that gathers Ethernet packets in G.709 containers, handles 10 Gb/s links, performs classification based on 24-byte headers, and includes a highly pipelined Queue Manager to cope with the considered rates while a specific scheduler controls the quality of service per core network flow. Based on the developed demonstrator, we provide results both as regards area and performance for an FPGA (field programmable gate array) Virtex-4 implementation as well as regarding the introduced jitter.

A New Instrument for Real-Time Ethernet Performance Measurement

Ethernet is now becoming a popular physical layer for industrial communications due to its reliability, performance, and widespread use. Its actual cutting edge is a minimum cycle time on the order of 100 mus and a jitter of 1 mus. Usually, high-cost laboratory devices are used to log network traffic, but they are still not suitable for an industrial environment. In this paper, a field-programmable-gate-array-based instrument is proposed to log 100-Mb/s Ethernet frames, assigning them a high-resolution time stamp. Full-duplex full-rate network traffic is duplicated and sent through two auxiliary Ethernet ports to a personal-computer-based monitor station for frame analysis. A prototype has been realized to verify feasibility and performance. Results show that the proposed instrument introduces a maximum delay of about 500 ns. The measurement capabilities are comparable with commercial instruments: The time-stamp assignment has a jitter of 150 ns measured on a test frame set.

Novel WDM-PON Architecture Based on a Spectrally Efficient IM-FSK Scheme Using DMLs and RSOAs

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> This paper proposes a wavelength-division-multiplexing passive optical network architecture with colorless user terminals based on the use of a different modulation scheme for each way of communication. Narrow-frequency-shift keying (FSK) modulation obtained by direct modulation of a distributed feedback laser has been used for the downstream channel, and intensity modulation has been used for the upstream channel. The performance of a link based on this scheme has been assessed, with particular emphasis on the description of the narrow-FSK modulation technique and its range of applicability in terms of bit rates and power levels. The operation of the architecture is demonstrated by simultaneously transmitting Ethernet frames at 1.25 Gb/s (gigabit Ethernet) in both the upstream and downstream channels. Error rates for downstream and upstream channels show excellent performance for distances up to 50 km. </para>

Distinguishing services at physical layer level in autonomic optical Internet

This paper proposes a mathematical model for distinguishing services at bit-level. By using correlation analysis, the features of bit flows are extracted. The feature analyses of time division multiplex (TDM) service and Gigabit Ethernet (GE) service are described in detail, and then the performance of the proposed method is evaluated. Both of the undetected probability and the misjudgment probability for GE service are as low as 2% at the average Ethernet frame length of 300 B.

Research of network technology for Intelligent Circuit Breaker Controller

With the current development trend of Ethernet gradually towards the control network of plant-floor layer and devices layer, much management information on Intelligent Circuit Breaker Controller (ICBC) is becoming distributed and networked. This paper describes a mixing structure of complex industrial field control network based on Ethernet frame, then mainly discusses three network management methods of ICBC, such as the interconnection method based on PCI, embedded gateway and embedded Web server. At the same time, it also gives the basic hardware framework of implementing interconnection, the type of main components, and the real-time operation system supporting the embedded TCP/IP protocols and Web server.

Performance Analysis of Two Ethernet over E1 Schemes

The Ethernet over E1 approach, which takes advantage of widely deployed telecom networks, is an efficient and economical way to interconnect two Ethernets in different regions. Two Ethernet over E1 schemes, namely a byte granularity scheme and a frame granularity scheme are discussed. The byte granularity scheme partitions Ethernet frames into several pieces for transmission and has a strict requirement on the maximum delay difference of multiple E1 links. To solve this problem, the newly proposed frame granularity scheme transmits separately each frame through E1 links without any partitioning. The architecture designs of both schemes are presented. This paper evaluates the throughput and delay performances of both schemes, both analytically from results calculated from delay models and using test results from field programmable gate array (FPGA) implementation. Although the frame granularity scheme has a slightly worse delay performance, it has a higher throughput, and is the only choice able to overcome large delay differences of the E1 links.

Integrating firewire peripheral interface with an ethernet custom network processor

Bandwidth demands on ubiquitous Ethernet have grown immensely, driven by the rapid expansion of real-time applications like audio/video streaming. In a related research, the authors designed a novel high-performance custom network processor chip using field programmable gate arrays (FPGAs). The main function of this chip (named SPEED) is to bypass the operating system processing of network protocol stack at the host computer by off-loading its networking functions to hardware. This simplification is not only required to fit in a hardware solution, but also it improves network performance. The novel chip utilizes the concept of Ethernet channels, where Ethernet frames are addressed in a multicast addressing scheme. In this article, we integrate the chip with a Firewire peripheral interface (FPI). A crucial function of the FPI design is to convert the IEEE 1394 isochronous traffic to the Ethernet frame format via two independent asynchronous write and read buffers. The FPI also manages the SPEED hardware interrupt signals in a bi-directional communication scheme. The goal of this research is to map isochronous Firewire packets into Ethernet frames by utilizing the SPEED Ethernet channel assignment capability. We used Verilog Hardware Description Language (HDL) to synthesize the FPI design. Since the FPI needs to support bi-directional communication, we also present a generic HDL model for bi-directional data sharing, which can be used in similar bi-directional applications. Initial performance measures show that the FPI consumes less that 0.15 W of power. Also we found that the synthesized design utilizes only 28% of the target chip resources. Hence it was possible to incorporate it with the SPEED design in the same FPGA chip. This low power consumption will lead to powering SPEED-FPI based network devices through the network cable and eliminate the process of regular electrical power outlet installations and maintenance. Thus, the SPEED-FPI system reduces the installation complexity, especially for large number of devices (e.g., surveillance cameras).

Narrow-FSK optical packet labeling scheme for optical ethernet networks

In this work, an intensity modulation/frequency-shift keying (IM/FSK) orthogonal modulation scheme is achieved by direct modulation of a distributed feedback laser source using its adiabatic chirp characteristics. Optical frequencies for "1" and "0" bits are separated only 0.7 GHz, obtaining a narrow-FSK modulation and, accordingly, a low residual intensity modulation. Ethernet frames at 1.25 Gb/s (GbE) are transmitted with a label inserted using coded mark inversion codification at a 155-Mb/s rate. Error rates for the Ethernet payload and for the label have been measured for different payload extinction ratios, showing the viability of this scheme for distances up to 25 km

Isolating the performance impacts of network interface cards through microbenchmarks

Many factors can prevent a Gigabit Ethernet network interface card (NIC) from achieving line rate in a modern web server. In fact, the various commercially available NICs have different performance characteristics that lead to throughput differences for actual web servers. For example, Figure 1 shows the performance achieved by the thttpd web server for client traces extracted from the Rice University computer science department (CS), a NASA web site (NASA), and the 1998 soccer World Cup tournament (World Cup). The latter two traces are available from the Internet Traffic Archive (http://ita.ee.lbl.gov/). The server system tested includes an AMD Athlon 2600+ XP processor running the FreeBSD 4.7 operating system, 2 GB of DDR SDRAM, a 64-bit/66 MHz PCI bus, and a single 40 GB IDE disk (none of the workloads are disk intensive). The tested systems differ only in their NIC, with the Intel Pro-1000/MT Server and Desktop, Alteon AceNIC with parallelized firmware [2], Netgear GA622T, 3Com 3C996B, and Alteon AceNIC with released firmware arranged from left to right. There are substantial performance differences across the NICs in the web environment, as the fastest NIC consistently achieves 40–60% more throughput than the slowest. A web server interacts with the network in two primary ways: receiving client HTTP requests and sending HTTP responses. Requests are typically quite small, on the order of 200 bytes of ASCII text, while responses vary from empty files to several hundred megabytes. Since web clients and servers communicate using TCP, the server must acknowledge requests, leading to minimum-sized (64-byte) Ethernet frames. Response data must be segmented and encapsulated in Ethernet frames, which allow up to 1460 bytes of TCP content in a maximum-sized (1518-byte) frame. Then, those segments are sent out according to TCP flow control policies based on the receipt of acknowledgments. A high-performance server NIC must thus support data volumes dominated by sends of large

The latest in VPNs: Part II

We describe the lastest in VPN. Virtual private networks (VPNs) can be configured and operated across a network provider's shared network infrastructure. The layer-2 VPN (L2VPN) is generating much interest and activity in the industry; it's defined as a VPN that transports native L2 frames across a shared IP network. Network providers will be able to reduce infrastructure and operation costs by taking traffic from L2-specific networks and running it over L2VPNs. An L2VPN transports native L2 frames across a shared IP or multiprotocol label-switching (MPLS) packet-switch network (PSN). The L2 frames can be frame-relay (FR) protocol data units, ATM cells, or even Ethernet frames; they're carried across the PSN using one of several different tunnel-encapsulation schemes. An L2VPN essentially provides the same set of services that native L2 LAN and WAN infrastructures support. We also discuss L2VPNs architecture and components.

Jitter Performance Analysis of SOCDMA-Based EPON Using Perfect Difference Codes

Recently the passive optical network (PON) has attracted a lot of attention because it is an excellent solution for broad-band first mile services. Combining Ethernet frame with PON (EPON) and using synchronous optical code-division multiple-access (SOCDMA) technology are very promising for this application. In this paper, we analyze the jitter performance of SOCDMA-based EPON communication systems using perfect difference codes (PDC). We propose the joint jitter estimator and canceller (JJEC) to reduce the impact of jitter and multiple-user interference (MUI). The bit error rate (BER) of the system with JJEC is formulated analytically based on the correlator and the simple sampler receiver structures. The numerical results show that the proposed scheme can significantly suppress the MUI and improve the system performance.

SPEED: Stand-alone programmable ethernet enabled devices

In this paper we present the design and synthesis of Standalone Programmable Ethernet Enabled Devices (SPEED) as a low cost and power consumption embedded system, which also include an Electrical Erasable Programmable Read Only Memory controller for configurable address assignments. The main function of SPEED is to eliminate the operating system processing of network protocol stack running by personal computer processor and simplifying network functions. This simplification is not exclusively required to fit in a hardware solution, but more important it improves network performance. It utilizes the concept of network channels, where Ethernet frames are delivered through a custom multicast addressing scheme. After validating SPEED simulation outputs, we synthesize the design in FPGA chip using Verilog HDL. Performance measures like power consumption and area utilization are computed using Verilog HDL synthesis tools. Initial performance measures had shown that the SPEED would be reducing the power consumption. Consequently, network devices could be powered through the network cable and eliminate the process of regular electrical power outlet installations and maintenance. This way, SPEED reduces the installation complexity, especially for large number of devices (e.g. surveillance cameras).

Efficient transport of packets with QoS in an FSAN-aligned GPON

The standardization of passive optical networks capable of transporting Ethernet frames at gigabit-per-second speeds, currently in progress in both ITU-T and IEEE, constitutes a major milestone toward cost-effective photonization of the last (aka first) mile. The article presents an Ethernet gigabit PON (GPON) system aligned with the philosophy of the evolving FSAN (full service access network) ITU-T specification, which focuses on the efficient support of any level of quality of service. The intelligence of this system, in terms of traffic quality guarantees, lies in the MAC protocol, which controls the distributed multiplexing/concentration function by allocating variable length slots to every user of the shared upstream (toward the network) medium. The way transport of information is organized in an ITU-T GPON system and the operation of a MAC protocol that preserves all QoS guarantees are presented and evaluated.

Measurement and modelling of self-similar traffic in computer networks

Results are noted from the analysis of traffic measured over a departmental switched Ethernet. Self-similar characteristics are seen throughout the network, for example, at the compute servers, web server and intermediate routers. It is shown that data shipped by the web server (i.e. including both static files from a file server and dynamically-generated data) have a heavy-tailed distribution, which is matched extremely well by a Cauchy distribution. It is also shown that the fragmentation of the data (i.e. into Ethernet frames) leads to a departure process whose power spectrum is shown to follow a power law very similar to that of the observed traffic. Importantly, the power law appears to be largely independent of the input process; self-similar behaviour is observed even with Poisson arrivals. This supports the suggested link between file/request size distribution and self-similarity in network traffic. The resulting implication that self-similarity and heavy tails are primarily due to server nodes, rather than being inherent in offered traffic, leads to the possibility of using conventional queueing network models of performance.

Direct connect device core: design and applications

In this paper, we present the design and synthesis of “Direct Connected Device Core” (DCD-Core) as a low cost and low power consumption embedded system, which includes an electrical erasable programmable read only memory (EEPROM) controller for configurable address assignments. The main function of DCD-embedded system is to eliminate the operating system processing of network protocol stack running by personal computers CPU and simplifying network connection requirements. Not only the hardware solution requires connection simplification, but also it improves network performance. Our DCD-Core utilizes the concept of network channels, where Ethernet frames are delivered through a custom multicast addressing scheme. After validating DCD-Core embedded system simulation outputs, we synthesize the design in FPGA chip using Verilog Hardware Description Language (HDL). Performance measures like power consumption and area utilization are computed using Verilog HDL synthesis tools. Initial performance measures had shown that the DCD-Core reduces the power consumption. Thus, network devices may be powered through the network cable and eliminate the process of regular electrical power outlet installations and maintenance. This way, DCD-Core reduces the connection complexity in terms of device installations, especially for large number of devices (e.g. surveillance system cameras).