Etch Stop Layer Research Articles

Selective Etching of SiO2 over Si3N4 through Varying the Concentration of Fluorine Species

Silicon dioxide (SiO2) and silicon nitride (Si3N4) are widely used as an insulating layer to separate interconnection, due to the characteristic of their wide band gap. As the feature size of semiconductors has been continuously decreasing and their structures have become more complex recent years, SiO2 as an insulating layer is reaching its limit. One of the ways to overcome this limitation, next generation 3D structure semiconductors are developed. In order to manufacture these kinds of devices, a removal of SiO2 is required, however, as both SiO2 and Si3N4 layers are revealed, the highly selective SiO2 etching process over Si3N4 is needed. If the Si3N4 layers were etched during the SiO2 layer etching process, the Si3N4 layer could not be function as an insulating layer and an etch stop layer. As an etchant for the SiO2 layer, hydrofluoric acid (HF) and ammonium fluoride (NH4F) combining solution is mainly used. However, it is known that HF solution also causes the material loss of the Si3N4 layers. Therefore, the study of etching behaviors of SiO2 and Si3N4 in HF solution is needed. In HF solutions, main etching species of SiO2 and Si3N4 exists as fluorine species. The concentration of these fluorine species depends on various conditions, such as pH of the solution or the composition of HF and NH4F. Therefore, the dependence of SiO2 and Si3N4 etching rates on the conditions of HF solutions were investigated.To investigate the etching rates of SiO2 and Si3N4, the blanket SiO2 and Si3N4 wafer in which deposited on Si wafer by the low-pressured chemical vapor deposition method were used, respectively. A patterned SiO2/Si3N4 multi-stack structures were fabricated by plasma-enhanced chemical vapor deposition, to verify whether SiO2 was selectively etched over Si3N4 in HF solution. The HF solutions were prepared by adding various concentrations of HF to deionized water and NH4F was added in some cases. The pH of the HF solution was controlled by adding hydrochloric acid or ammonium hydroxide. The temperature maintained at 25 °C during the etching processes using a water bath. The blanket SiO2 and Si3N4 wafers were immersed in these solutions for 3 and 60 mins, respectively. The etching depth of the SiO2 and Si3N4 films was measured by spectroscopic ellipsometry. The morphology of patterned SiO2/Si3N4 multi-stack structures after etching process was observed using field-emission scanning electron microscopy (FE-SEM). The pH and the concentrations of each fluorine species of the prepared HF solutions were calculated based on the equilibrium constants, molar balance, and charge balance.To obtain the HF solution with the high SiO2 etching selectivity over Si3N4, blanket SiO2 and Si3N4 wafers were etched under various pH and initial concentrations of HF solution. As the pH of the HF solution was increased, at the same initial HF concentration, the SiO2/Si3N4 etching selectivity was increased. Meanwhile, the etching selectivity of SiO2 over Si3N4 was increased with the initial concentrations of HF increased, at a fixed pH of the solution. To investigate the reason for the dependencies of the SiO2 and Si3N4 etching rates on pH and initial concentrations of HF, the concentrations of each fluorine species were calculated. As a result, the etching mechanisms and the etching behaviors of SiO2 and Si3N4 in the HF solutions were suggested. Based on the etching kinetics of SiO2 and Si3N4, a patterned SiO2/Si3N4 multi-stack structure etching conditions were controlled to investigate the SiO2/Si3N4 selective etching ability of the HF solution. The cross-sectional FE-SEM images visually showed that high SiO2 etching selectivity compared to Si3N4 was achieved. As a result, highly selective SiO2 etching without loss of Si3N4 was obtained by adjusting only the concentrations of HF and NH4F, without any special additives through the suggested SiO2 and Si3N4 etching kinetics.

Demonstration of HCl-Based Selective Wet Etching for N-Polar GaN with 42:1 Selectivity to Al0.24Ga0.76N

A wet-etching technique based on a mixture of hydrochloric (HCl) and nitric (HNO3) acids is introduced, demonstrating exceptional 42:1 selectivity for etching N-polar GaN over Al0.24Ga0.76N. In the absence of an AlGaN etch stop layer, the etchant primarily targets N-polar unintentionally doped (UID) GaN, indicating its potential as a suitable replacement for selective dry etches in the fabrication of GaN high-electron-mobility transistors (HEMTs). The efficacy and selectivity of this etchant were confirmed through its application to a gate recess module of a deep-recess HEMT, where, despite a 228% over-etch, the 2.6 nm AlGaN etch stop layer remained intact. We also evaluated the proposed method for the selective etching of the GaN cap in the n+ regrowth process, achieving a contact resistance matching that of a BCl3/SF6 ICP process. These findings underscore the applicability and versatility of the etchant in both the electronic and photonic domains and are particularly applicable to the development of N-polar deep-recess HEMTs.

Monolithic back-end-of-line integration of phase change materials into foundry-manufactured silicon photonics

Monolithic integration of novel materials without modifying the existing photonic component library is crucial to advancing heterogeneous silicon photonic integrated circuits. Here we show the introduction of a silicon nitride etch stop layer at select areas, coupled with low-loss oxide trench, enabling incorporation of functional materials without compromising foundry-verified device reliability. As an illustration, two distinct chalcogenide phase change materials (PCMs) with remarkable nonvolatile modulation capabilities, namely Sb2Se3 and Ge2Sb2Se4Te1, were monolithic back-end-of-line integrated, offering compact phase and intensity tuning units with zero-static power consumption. By employing these building blocks, the phase error of a push-pull Mach–Zehnder interferometer optical switch could be reduced with a 48% peak power consumption reduction. Mirco-ring filters with >5-bit wavelength selective intensity modulation and waveguide-based >7-bit intensity-modulation broadband attenuators could also be achieved. This foundry-compatible platform could open up the possibility of integrating other excellent optoelectronic materials into future silicon photonic process design kits.

Three-Step Process for Efficient Solar Cells with Boron-Doped Passivated Contacts

Crystalline silicon (c-Si) solar cells with passivation stacks consisting of a polycrystalline silicon (poly-Si) layer and a thin interfacial silicon dioxide (SiO2) layer show high conversion efficiencies. Since the poly-Si layer in this structure acts as a carrier transport layer, high doping of the poly-Si layer is crucial for high conductivity and the efficient transport of charge carriers from the bulk to a metal contact. In this respect, conventional furnace-based high-temperature doping methods are limited by the solid solubility of the dopants in silicon. This limitation particularly affects p-type doping using boron. Previously, we showed that laser activation overcomes this limitation by melting the poly-Si layer, resulting in an active concentration beyond the solubility limit after crystallization. High electrically active boron concentrations ensure low contact resistivity at the (contact) metal/semiconductor interface and allow for the maskless patterning of the poly-Si layer by providing an etch-stop layer in an alkaline solution. However, the high doping concentration degrades during long high-temperature annealing steps. Here, we performed a test of the stability of such a high doping concentration under thermal stress. The active boron concentration shows only a minor reduction during SiNx:H deposition at a moderate temperature and a fast-firing step at a high temperature and with a short exposure time. However, for an annealing time tanneal = 30 min and an annealing temperature 600 °C ≤ Tanneal≤ 1000 °C, the high conductivity is significantly reduced, whereas a high passivation quality requires annealing in this range. We resolve this dilemma by introducing a second, healing laser reactivation step, which re-establishes the original high conductivity of the boron-doped poly-Si and does not degrade the passivation. After a thermal annealing temperature Tanneal = 985 °C, the reactivated layers show high sheet conductance (Gsh) with Gsh = 24 mS sq and high passivation quality, with the implied open-circuit voltage (iVOC) reaching iVOC = 715 mV. Therefore, our novel three-step process consisting of laser activation, thermal annealing, and laser reactivation/healing is suitable for fabricating highly efficient solar cells with p++-poly-Si/SiO2 contact passivation layers.

Stable High Temperature Operation of p-GaN Gate HEMT With Etch-Stop Layer

Stable High Temperature Operation of p-GaN Gate HEMT With Etch-Stop Layer

Wet etch methods to achieve submicron active area self-aligned vertical Sb-heterostructure backward diodes

Sb-heterostructure backward diodes are attractive for passive millimeter-wave sensing techniques in Earth Observation applications, facilitating superior sensitivity (non-linearity) and low noise as compared to traditional zero-bias Schottky diodes. Reducing diode active area is imperative to achieve both increased sensitivity and operation at higher frequencies. In this work, we report a wet etch method utilizing citric acid, phosphoric acid, and hydrogen peroxide for simplified fabrication of vertical (250 nm height) Sb-heterostructure (InAs/AlSb/AlGaSb/GaSb) devices down to active area of 0.04 μm2 (critical dimensions 0.2 × 0.2 μm2). While conventional citric/peroxide etch chemistries are ineffective for removal of Sb-based etch products, including Sb2O5, the addition of phosphoric acid has shown to promote dissolution of etch stop layers, maintaining a linear etch rate throughout the device heterostructure. Furthermore, we found that citric acid plays a crucial role in the underlying etch mechanism which can be attributed to the formation of soluble Sb(V)-citrate complexes. Conducting the etching at reduced temperatures has also shown to promote slow-etching facets at reduced etch temperature (4 °C) drastically improving anisotropy. Finally, the etch method is evaluated by current-voltage characterization of the fabricated diodes achieving predictible active area scaling of performance-metrics across 190 devices indicating formation of defect free sidewalls.

Wet Cleaning of Ru Semi-Damascene 18 MP Structures

Cleaning of semi-damascene structures after direct metal etch (DME) are becoming more challenging as the size of features are getting smaller and number of materials increase in advanced nodes. Typical DME residues in-between Ru lines, generated during/after semi-damascene patterning by DME, mainly consist of Ti-based residues whereas there are TiN layers present as etch stop layer (ESL) below the SiN HM and underneath Ru lines. Wet cleaning of Ti-based residues selective to TiN and Ru in a decent process time is necessary. Undercut of TiN during wet cleaning results in collapsing of the SiN HM and/or Ru lines. We present a novel FOTOPUR® R solution designed to clean Ti-based residues selective to Ru and TiN. Moreover, the new chemistry can further extend the process window without collapsing the Ru lines.

Laser Activation for Highly Boron-Doped Passivated Contacts

Passivated, selective contacts in silicon solar cells consist of a double layer of highly doped polycrystalline silicon (poly Si) and thin interfacial silicon dioxide (SiO2). This design concept allows for the highest efficiencies. Here, we report on a selective laser activation process, resulting in highly doped p++-type poly Si on top of the SiO2. In this double-layer structure, the p++-poly Si layer serves as a layer for transporting the generated holes from the bulk to a metal contact and, therefore, needs to be highly conductive for holes. High boron-doping of the poly Si layers is one approach to establish the desired high conductivity. In a laser activation step, a laser pulse melts the poly Si layer, and subsequent rapid cooling of the Si melt enables electrically active boron concentrations exceeding the solid solubility limit. In addition to the high conductivity, the high active boron concentration in the poly Si layer allows maskless patterning of p++-poly Si/SiO2 layers by providing an etch stop layer in the Si etchant solution, which results in a locally structured p++-poly Si/SiO2 after the etching process. The challenge in the laser activation technique is not to destroy the thin SiO2, which necessitates fine tuning of the laser process. In order to find the optimal processing window, we test laser pulse energy densities (Hp) in a broad range of 0.7 J/cm2 ≤ Hp ≤ 5 J/cm2 on poly Si layers with two different thicknesses dpoly Si,1 = 155 nm and dpoly Si,2 = 264 nm. Finally, the processing window 2.8 J/cm2≤ Hp ≤ 4 J/cm2 leads to the highest sheet conductance (Gsh) without destroying the SiO2 for both poly Si layer thicknesses. For both tested poly Si layers, the majority of the symmetric lifetime samples processed using these Hp achieve a good passivation quality with a high implied open circuit voltage (iVOC) and a low saturation current density (J0). The best sample achieves iVOC = 722 mV and J0 = 6.7 fA/cm2 per side. This low surface recombination current density, together with the accompanying measurements of the doping profiles, suggests that the SiO2 is not damaged during the laser process. We also observe that the passivation quality is independent of the tested poly Si layer thicknesses. The findings of this study show that laser-activated p++-poly Si/SiO2 are not only suitable for integration into advanced passivated contact solar cells, but also offer the possibility of maskless patterning of these stacks, substantially simplifying such solar cell production.

Thickness and porosity characterization in porous silicon photonic crystals: The etch-stop effect

One-dimensional photonic crystals and microcavities were fabricated using porous silicon via anodization. The study investigated the effect of an etch-stop layer, which is included between two adjacent porous layers to resolve the issue of HF diffusion during pore formation. Although proposed as a solution, no systematic investigation had been conducted on this parameter until now. Our study found that the etch-stop layer induces a redshift in the photonic bandgap, regardless of the electrolyte solution used. The fitting analysis of both single and multilayer structures revealed that the redshift resulted from an increase in the silicon etch rate and a decrease in porosity due to the enhancement of HF diffusion through the porous structure. Furthermore, an analysis of oxidation as a function of temperature demonstrated that the inclusion of the etch-stop layer led to the formation of porous layers with varying microstructures. This effect was particularly pronounced in devices where the first upper layer had high porosity. The thermal treatment caused a photonic bandgap inhibition, which was linked to the contraction-expansion phenomena of the low and high porosity layers, respectively. This resulted in the partial violation of Bragg's law. Overall, our study provides insights into the influence of etch-stop layers on the optical properties of porous silicon-based photonic structures.

43.2: Parasitic Capacitance Model for BGTC TFTs and Verification Using C‐V Measurements from Devices with Various Channel Dimensions

A model of the accumulation and depletion capacitance for a bottom gate top contact (BGTC) thin film transistors (TFT) with an etch stop layer (ESL) was presented. The model, which includes the parasitic capacitance due to device layout, was verified by comparison of measured data and modeled data for TFTs of various dimensions. Good agreement was seen between measured and modeled data, where the model underestimated the capacitance by 2% to 7%, depending on the device dimensions. The impact of the parasitic capacitance on estimates of the Debye length (λD ) are discussed and it is demonstrated that the relative error in the λD estimates is directly proportional to the ratio of the parasitic capacitance over the measured capacitance (CPAR/CM). The relative error was shown to increase as the ratio increases, leading to a larger underestimation of the λD. It was concluded that the parasitic capacitance to measured capacitance should be minimized for devices that are used for extraction of physical parameters from C‐V data. This is especially important in the case where the λD is a critical parameter in the optimization of TFT performance.

Terahertz Resonant-Tunneling Diode With Series-Fed Patch Array Antenna

Resonant-tunneling diodes (RTDs) are promising electronic sources for terahertz (THz) waves. A recently proposed slot-based RTD simplifies the fabrication process by removing the metal–insulator–metal capacitor, which is used for dc separation, and introducing an etch stopper layer for simple air bridge formation. The simplified RTD structure, however, exhibits an unexpected large tilt angle in the main lobe of its radiation pattern due to the coupling between the slot antenna and the bias pads. Here, we present a series-fed patch array design that exploits the biasing structure and directs leakage surface waves to the broadside direction. The simulation result shows that the main lobe is along the broadside, with a maximum directivity over 12 dBi and a 3-dB bandwidth around 20%. The radiation efficiency is improved from 22% to 28% at 275 GHz. An experimental validation with a bullet lens indicates that the RTD device with a series-fed patch array antenna has a narrower beamwidth and a sidelobe level much lower compared with the original RTD. With such improved radiation performance, this simple RTD device becomes a potential source for the development of future array-level designs and flat lens systems.

A high-reliability scan driver integrated circuit by MO TFTs for a foldable display

Foldable displays have become increasingly used as a solution to the portability-practicality trade-off. A new scan driver integrated with metal oxide thin film transistors (MO TFTs) is proposed for foldable displays to overcome the effects of threshold voltage shifts on the scan driver output. In the scan driver, a feedback section and two series to transistor structures are used to keep the voltage of the key node to sustain a normal output, with this structure, the lower the voltage of the negative supply, the more stable the scan driver will be. Some flexible MO TFTs and 60 stage scan drivers are fabricated by etch stop layer structures on the polyimide substrate. Under different strains and 100 000 times bending with the minimum 3.5 mm bending radius, the characteristics of MO TFTs and the output waveform of the scan driver are measured. Experimental results show that the proposed scan driver shows high reliability since only a little voltage fluctuation occurs at the outputs after the bending test and has a better output waveform with a lower voltage of the negative supply.

Inherent selective pulsed chemical vapor deposition of aluminum oxide in nm scale

Inherent selective pulsed chemical vapor deposition (CVD) of aluminum oxide on Si and SiO2 in preference to SiCOH has been studied. SiCOH is alkyl (-CxHy) terminated SiO2, which was used as a non-reactive surface. For aluminum oxide deposition, pulsed CVD processes using aluminum tri sec-butoxide (ATSB) and trimethylaluminum (TMA) were tested. ATSB alone can induce a pulsed thermal CVD reaction to selectively deposit aluminum oxide at 300 °C sample temperature; ∼4 nm of aluminum oxide were selectively deposited on Si and SiO2 in preference to SiCOH. By adding a periodical pulse of TMA during ATSB pulses, higher selectivity was achieved with ∼12 nm and ∼14 nm of aluminum oxide on Si and SiO2 with around 0.4–0.5 nm root mean square (RMS) roughness at 330 °C. The high selectivity persisted on the nanoscale: STEM showed that ∼10 nm of aluminum oxide could be selectively deposited on nanoscale patterned features. The selectively deposited AlOx films showed low k (∼4) dielectric performance with low leakage (around 10−6 A/cm2 at ± 2 V for a 15 nm thick film). This selective aluminum oxide pulsed CVD process has the potential to be applicable in nanoscale fabrication, such as low k spacer and etch stop layer.

Double-sided silicon vias (DSSVs) interconnection for large-sized interposer fabrication

PurposeA large-scale detection system with more data in short time bins, small dead space and small signal identification is the ideology the scientists pursuing. These proposed demands are able to be solved by 2.5 D integration. The substance of a 2.5 D integration is called silicon interposer, which consists of the through silicon via (TSV) and redistribution layer. However, the state-of-the-art silicon interposer is not able to sustain its own mechanical strength with the detector/readout array often sitting as standalone in large science facilities and fails to reduce the expansions on the installation of the components due to its insufficient thickness and size. This study aims to propose a moderation of current interposer with large-sized, standalone properties.Design/methodology/approachThis paper proposes an interposer based on double-sided silicon vias (DSSVs) interconnection. Unlike conventional interposer that is interconnected by TSVs, DSSVs interposer is interconnected by top vias (T-vias) and bottom vias (B-vias).FindingsThe fabrication process of DSSVs interposer is introduced, and the superiority of the double-sided interconnection process with two etch-stop layers is described in detail. The impact of different T-vias depth on DSSVs interconnections in the same wafer is discussed and two times PI opening processes are proposed to eliminate air bubbles in the B-via. The relationship between the interposer thickness and warpage is studied by finite element analysis simulation and experiment. The prototype of the DSSVs interposer with a size of 100 × 100 mm and a thickness of 318.2 µm is fabricated, and electrical tests including short tests and continuity tests are carried out.Originality/valueThis paper proposes a large-sized and stand-alone interposer based on DSSVs interconnection.

Area selective deposition of ruthenium on 3D structures

Trends in device miniaturization have driven the adoption of new materials that, in turn, have enabled significant advancements in the field of process engineering and integration for semiconductor technology. Continued progress for device scaling is necessary and can be enabled by advances in lithographic techniques and deposition schemes. Thin-film deposition for spacers and etch stop layers has become a mainstay to enable and extend traditional 2D scaling into the 3D realm for fabricating advanced semiconductor devices. For processing 3D structures, controlled film deposition with subnanometer resolution in high aspect ratio features is desired. Area selective deposition (ASD) can be a powerful response to such a challenge. ASD is a type of thin-film deposition technique scheme that can be used to eliminate the need for several expensive and time-consuming lithography steps with fewer performance penalties. In this work, we show ASD of ruthenium (Ru) on 3D molybdenum (Mo)–silicon oxide (SiO2) stacks by utilizing the inherent substrate preference of the Ru precursor to a H-terminated surface. In the best selectivity condition, our results show growth of ∼5 nm Ru on Mo, with no film growth on SiO2. Changes in Ru growth kinetics were observed after dilute hydrofluoric acid (DHF) treatment for both surfaces. Post-DHF treatment, the Ru growth rate on Mo was reduced by 5%. However, on SiO2 (after incubation delay), the growth rate was reduced by 94% compared to untreated surfaces. This translates to a very high difference in the growth rate of Ru on Mo vs SiO2, even after considering the incubation delay. Finally, by using 3D topologies with high aspect ratio holes, we have highlighted that it is important to deconvolute the effects of precursor depletion and selectivity. To the best of our knowledge, this is the first demonstration of ASD of Ru on 3D structures without the use of any blocking layers. Therefore, these results demonstrate a new paradigm for ASD in 3D features.

(Digital Presentation) High Performance Back-Channel-Etch Igzo TFT with Self-Passivate HfO2 By Backside Exposure Technology

Recently, amorphous oxide semiconductor (AOS)-based TFTs have drawn much attention for the backplane technologies of the ultra-high resolution TFT-LCDs and AMOLEDs [1-2]. To overcome the degradation of electrical characteristics caused by the ambient, a passivation layer capsulation is proposed to solve the problem. In this work, a capping layer of HfO2 film is studied acting as both a passivation layer and an etch stop layer for TFT device structure with the back channel etching (BCE) process. The BCE type of indium-gallium-zinc-oxide (IGZO) TFT is successfully demonstrated with a self-aligned backside exposure method for the photo-mask reduction, which not only decreases the complexity of the device fabrication but also lowers the manufacturing cost [3-4].ExperimentAmorphous IGZO TFTs with a bottom gate staggered structure were fabricated in this work. A layer of metallic Mo thin film was first deposited on a glass substrate by DC sputtering and patterned as the gate electrode. It was followed by the deposition of HfO2 film as gate insulator and a-IGZO as channel layer by RF sputtering. Besides, a HfO2 capping layer was deposited on top of IGZO channel layer as the passivation and etch stop layer (ESL). The self-aligned backside exposure process was then implemented to pattern the IGZO channel layer and ESL simultaneously. And Mo source/drain (S/D) electrodes were formed to finish the BCE a-IGZO TFT manufacture. The IGZO TFT was also fabricated with a lift-off S/D process. Firstly, the exposure of the S/D area patterns was executed by removing the photoresist covered on the top of the S/D in the development process. Then, a layer of Mo film was deposited by DC sputtering, and followed by performing the lift-off process in acetone for the photoresist stripping. Thus, the open hole on S/D pattern areas will be filled with Mo and form S/D electrodes. The manufacture of lift-off S/D IGZO TFT was completed, and it will be compared with the characteristics of BCE a-IGZO TFT.Result and DiscussionThe experimental results have shown that the HfO2 capping layer can keep IGZO channel from exposing to oxygen and hydrogen in the atmosphere. Also, HfO2 capping layer could be acting as etching stop layer to protect IGZO channel from the damage during BCE process. As compared with a lift-off S/D process without BCE damage, the nearly non-degraded BCE a-IGZO TFT in this work demonstrates the compatible performance such as threshold voltage of 0.03 V, an approximately ideal sub-threshold swing of 65.8 mV/dec., field-effect mobility of 9.91 cm2/V·s, on/off current ratio of 6×107 (at VD=0.1 V), and extremely low electrical hysteresis loop of ~ 0 mV was obtained successfully. Furthermore, the self-aligned process with backside exposure could lower the cost for device fabrication by decreasing the number of photomasks, and the BCE process have the ability for channel size scaling. With the excellent characteristics mentioned above, the BCE a-IGZO TFT is highly applicable to the emerging high-resolution display technologies.Reference[1] T. Kamiya, K. Nomura , and H. Hosono, Science and Technology of Advanced Materials, vol. 11, no. 4, pp. 044305, 2010.[2] P. Y. Kuo, C. M. Chang, I. H. Liu, and P. T. Liu, Scientific reports, vol. 9, no. 1, pp. 1-7, 2019.[3] Y. Kuo, Journal of The Electrochemical Society, vol. 138, no. 2, pp. 637, 1991.[4] N. Münzenrieder, P. Voser, L. Petti, C. Zysset, L. Büthe, C. Vogt, G. A. Salvatore, and G. Tröster, IEEE Electron Device Letters, vol. 35, no. 1, pp. 69, 2014. Figure 1

Study of Etch Stop Layer on Characteristics of Amorphous Aluminum Oxide Thin Film

To protect the active layer, which are inter layer dielectrics (ILD) and metal lines, from being damaged by UV laser during the etching process, etch stop layers (ESL) are used in patterning process of the integrated circuits (ICs) fabrication in back end of line (BEOL). The ESL material should have a higher etch selectivity than the active layer. Therefore, it must have a low dielectric constant and high chemical resistance. Aluminum oxide compounds (AlOx, AlOC, AlON, etc.) are highly suitable for use as ESL due to the low dielectric constant between about 4 and 9, high etch selectivity, high density (2.5-3.8 g/cm3) and pattern transfer capability. We focused on lowering the dielectric permittivity and increasing the density by controlling the precursor/reactant pulsed time of atomic layer deposition (ALD).

Reclaim Mode Post Etch Residue Remover Solutions for Advanced Technology Nodes

Back-end-of-line (BEOL) processing for creation of vias in advanced technology node semiconductor manufacturing warrants a wet chemistry capable of removing post-etch residue (PERR), titanium nitride hardmask (TiN HM) and etch stop layer (ESL), while being compatible with metals, such as copper, tungsten and cobalt. In accordance with BASF’s core competency of innovating sustainable solutions with minimal environmental impact, our reclaim mode BEOL PERR chemistries allow semiconductor manufacturers to minimize not only their cost of ownership (COO) but also their waste footprint.BASF’s reclaim mode PERR chemistries, when mixed with appropriate amount of hydrogen peroxide, facilitate oxidative wet etching of TiN HM. In this paper, we demonstrate that optimization of formulation and spiking protocol extends the bath lifetime of these chemistries beyond 24hr, which is significant improvement vis-à-vis current industry standard of single use (drain mode) chemistries. Beaker-level bath lifetime investigation of BASF’s leading formulation confirms that TiN etch rate (ER) and bath pH are stable for 48hr (Fig. 1a) when bath is loaded with commensurate amount of Ti ions. Beaker-level performance was also corroborated by 300mm wafer level assessment. BASF’s reclaim mode PERR chemistries with bath lifetime greater than 8hr offer progressively favorable cost of ownership (COO) vis-à-vis drain mode chemistry (Fig. 1b). Figure 1

Understanding of Etching Mechanism of Si3N4 Film in H3PO4 Solution For The Fabrication of 3D NAND Devices

Silicon nitride (Si3N4) has been widely used as an insulating or etch stop layer in the semiconductor devices [1]. For example, in a 3D V-NAND flash memory manufacturing process, Si3N4 is alternately stacked with silicon oxide (SiO2) to form a NAND structure. Here, it is necessary to selectively etch Si3N4 avoiding etching of SiO2 in the repeated Si3N4/SiO2 multi-stack layers. In general, phosphoric acid (H3PO4) is used to selectively etch Si3N4 against SiO2 [2]. However, since the concentration of H3PO4 solution changes with the evaporation of H2O, it is not easy to determine the concentration dependence of Si3N4 etching rate in H3PO4 solution. In order to properly control the shape of the 3D V-NAND structure, it is necessary to extensively understand the effect of H3PO4 concentration on the Si3N4 etching. The study of Si3N4 etching has been mainly focused on the effect of additives in H3PO4 on the behavior of Si3N4 etching to solve the issue such as oxide regrowth so far [3, 4]. Fundamental study of the Si3N4 etching reaction mechanism in H3PO4 is lacking. In this study, the Si3N4 etching mechanism in H3PO4 solution is elucidated systematically.For the investigation of Si3N4 etching reaction mechanism, LPCVD Si3N4 blanket wafer and Si3N4/SiO2 multi-stack layered trench wafer were used. Etching experiments of of Si3N4 were conducted in 10-95 wt% H3PO4 solutions at 160 °C. Spectroscopic ellipsometry and field emission scanning electron microscopy were used to measure the etching rate of Si3N4 after etching process.First, the changes in etching rate of Si3N4 in the various concentrations of H3PO4 solution were investigated. As shown in Fig. 1, according to our kinetic calculation and experiments, etching rate of Si3N4 increased as the H3PO4 concentration increased until the concentration of H3PO4 reaches a certain concentration that produced the highest etching rate. However, etching rate of Si3N4 decreased with the concentration of H3PO4 beyond the critical H3PO4 concentration. According to the results, there may be two concentrations of H3PO4 solution which produce an identical etching rate of Si3N4. It is also suggested that not only H3PO4 but also H2O plays an important role in the Si3N4 etching kinetics.To investigate the role of H2O and H3PO4 in the etching reaction of Si3N4, kinetic isotope effect (KIE) of Si3N4 etching reaction in H3PO4 solution was used. KIE provides information about which reactant determines the rate-limiting step. In this study, each reactant of Si3N4 etching reaction, H2O or H3PO4, was substituted with D2O and D3PO4, respectively. Then, etching of Si3N4 was conducted in four different solutions. As shown in Fig. 2, when H3PO4 was replaced by D3PO4, the Si3N4 etching rate was not significantly changed. However, when H2O was replaced by D2O, the Si3N4 etching rate decreased by 30 %. Therefore, it is thought that rate-limiting step of the Si3N4 etching reaction is determined by an elementary reaction related to H2O rather than H3PO4.Based on the above results, Si3N4 etching reaction mechanism was suggested. First, the Si3N4 surface termination (-NH2) is substituted with H2PO4 -, which is a weak nucleophile, by an SN1-like reaction. When H2PO4 - binds to Si, the backbone of Si3N4 is weakened because the electronegativity of O (3.44) is greater than N (3.04). Next, the Si-N of the weakened backbone of Si3N4 is substituted with Si-OH by an SN2-like reaction of H2O. This SN2-like reaction is considered as a rate-limiting step. It is believed that understanding of etching mechanism of Si3N4 in H3PO4 solution will improve selective etching process of Si3N4 for the integration of 3D V-NAND.

Two-dimensional guided-mode resonance gratings with an etch-stop layer and high tolerance to fabrication errors.

Guided-mode resonance (GMR) bandpass filters have many important applications. The tolerance of fabrication errors that easily cause the transmission wavelength to shift has been well studied for one-dimensional (1D) anisotropic GMR gratings. However, the tolerance of two-dimensional (2D) GMR gratings, especially for different design architectures, has rarely been explored, which prevents the achievement of a high-tolerance unpolarized design. Here, GMR filters with common 2D zero-contrast gratings (ZCGs) were first investigated to reveal their differences from 1D gratings in fabrication tolerance. We demonstrated that 2D ZCGs are highly sensitive to errors in the grating linewidth against the case of 1D gratings, and the linewidth orthogonal to a certain polarization direction has much more influence than that parallel to the polarization. By analyzing the electromagnetic fields, we found that there was an obvious field enhancement inside the gratings, which could have a strong effect on the modes in the waveguide layer through the field overlap. Therefore, we proposed the introduction of an etch-stop (ES) layer between the gratings and the waveguide-layer, which can effectively suppress the interaction between the gratings and modal evanescent fields, resulting in 4-fold increased tolerance to the errors in the grating linewidth. Finally, the proposed etch-stop ZCGs (ES-ZCGs) GMR filters were experimentally fabricated to verify the error robustness.