Error Recovery Scheme Research Articles

DVFS Based Error Avoidance Strategy in Wireless Network-on-Chip

In wireless on-chip network, the reliability of data packet transmission in the link faces great challenges due to crosstalk between lines, noise and transient faults, which seriously affects the overall performance of the network. Therefore, fault tolerance becomes critical in link design. In addition, the traditional fault-tolerant solution based on the error recovery strategy brings a lot of retransmission overhead under high failure rate. Hence, in this paper we propose a new fault-tolerant scheme based on DVFS error avoidance strategy, which dynamically adjusts the voltage and frequency in the network based on the real-time status of the network, thereby reducing the occurrence of faults. Experiments indicate that compared with the traditional fault-tolerant scheme based on error recovery strategy, this paper achieves a huge performance improvement with less power consumption and area overhead.

Use of error management theory to quantify and characterize residents’ error recovery strategies

BackgroundTraditional checklist metrics for surgical performance can miss key intraoperative decisions that impact procedural outcomes. Error-based assessments may help identify important metrics for evaluating operative performance and resident readiness for independent practice. MethodsThis study utilized human factors error analysis and error management theory to investigate a previously collected video database of resident performance during a simulated laparoscopic ventral hernia (LVH) repair on a table-top simulator using standard laparoscopic tools and mesh. Errors were deconstructed and coded using a structured observation tool and video analysis software. Error detection events and error recovery events were categorized for each operative step of the ventral hernia repair. ResultsResidents made a total of 314 errors (M = 15.7, SD = 4.96). There were more technical errors (63%) than cognitive errors (37%) and more commission errors (69%) than omission errors (30%). Almost half (47%) of all errors went completely undetected by the residents for the entire LVH repair. Of the errors that residents attempted to recover (n = 136), 86.0% were successfully recovered. Technical errors were four times more likely to be successfully recovered than cognitive errors (p = .020). ConclusionsOur results revealed specific details regarding residents’ error management strategies and provides validity evidence for the use of human factors error frameworks in surgical performance assessments. Practice in simulation-based learning environments may improve resident decision-making and error management opportunities by providing a structured experience where errors are explicitly characterized and used for training and feedback. Error management training may play a major role in equipping residents and junior faculty with the skills required for independent, high-quality operative performance.

Application Health Monitoring for Extreme-scale Resiliency using Cooperative Fault Management.

Resiliency is and will be a critical factor in determining scientific productivity on current and exascale supercomputers, and beyond. Applications oblivious to and incapable of handling transient soft and hard errors could waste supercomputing resources or, worse, yield misleading scientific insights. We introduce a novel application-driven silent error detection and recovery strategy based on application health monitoring. Our methodology uses application output that follows known patterns as indicators of an application's health, and knowledge that violation of these patterns could be indication of faults. Information from system monitors that report hardware and software health status is used to corroborate faults. Collectively, this information is used by a fault coordinator agent to take preventive and corrective measures by applying computational steering to an application between checkpoints. This cooperative fault management system uses the Fault Tolerance Backplane as a communication channel. The benefits of this framework are demonstrated with two real application case studies, molecular dynamics and quantum chemistry simulations, on scalable clusters with simulated memory and I/O corruptions. The developed approach is general and can be easily applied to other applications.

Performance Analysis of Timing-Speculative Processors

We propose a framework to estimate the number of timing errors experienced by an application as it runs on a timing-speculative processor. It takes a hybrid approach combining an accurate gate-level dynamic timing analysis engine to find timing errors in the processor's control network with a fast architecture-level execution-driven simulator based on a path activation model of the datapath. We develop an instruction-level error model that estimates the likelihood of an instruction experiencing a timing error, capturing the effects of process and data variations as well as inter-instruction correlations caused by the error recovery scheme used by the processor. Finally, we utilize two well-known laws of applied statistics, the law of small numbers and the law of large numbers, to estimate, with bounded inaccuracy, the total number of timing errors experienced by a specific application. Our experiments show that the combination of running application and its input data can change performance by as much as 25 percent, demonstrating that application-specific analysis is necessary for accurate evaluation of timing-speculative processors and should be used to inform design decisions and assess the suitability of applications for timing speculation.

Who Is Responsible for a Dialogue Breakdown? An Error Recovery Strategy That Promotes Cooperative Intentions From Humans by Mutual Attribution of Responsibility in Human-Robot Dialogues.

We propose a strategy with which conversational android robots can handle dialogue breakdowns. For smooth human-robot conversations, we must not only improve a robot's dialogue capability but also elicit cooperative intentions from users for avoiding and recovering from dialogue breakdowns. A cooperative intention can be encouraged if users recognize their own responsibility for breakdowns. If the robot always blames users, however, they will quickly become less cooperative and lose their motivation to continue a discussion. This paper hypothesizes that for smooth dialogues, the robot and the users must share the responsibility based on psychological reciprocity. In other words, the robot should alternately attribute the responsibility to itself and to the users. We proposed a dialogue strategy for recovering from dialogue breakdowns based on the hypothesis and experimentally verified it with an android. The experimental result shows that the proposed method made the participants aware of their share of the responsibility of the dialogue breakdowns without reducing their motivation, even though the number of dialogue breakdowns was not statistically reduced compared with a control condition. This suggests that the proposed method effectively elicited cooperative intentions from users during dialogues.

Low-Power Approximate Unsigned Multipliers With Configurable Error Recovery

Approximate circuits have been considered for applications that can tolerate some loss of accuracy with improved performance and/or energy efficiency. Multipliers are key arithmetic circuits in many of these applications including digital signal processing (DSP). In this paper, a novel approximate multiplier with a low power consumption and a short critical path is proposed for high-performance DSP applications. This multiplier leverages a newly designed approximate adder that limits its carry propagation to the nearest neighbors for fast partial product accumulation. Different levels of accuracy can be achieved by using either OR gates or the proposed approximate adder in a configurable error recovery circuit. The approximate multipliers using these two error reduction strategies are referred to as AM1 and AM2, respectively. Both AM1 and AM2 have a low mean error distance, i.e., most of the errors are not significant in magnitude. Compared with a Wallace multiplier optimized for speed, an $8\times 8$ AM1 using four most significant bits for error reduction shows a 60% reduction in delay (when optimized for delay) and a 42% reduction in power dissipation (when optimized for area). In a $16\times 16$ design, half of the least significant partial products are truncated for AM1 and AM2, which are thus denoted as TAM1 and TAM2, respectively. Compared with the Wallace multiplier, TAM1 and TAM2 save from 50% to 66% in power, when optimized for area. Compared with existing approximate multipliers, AM1, AM2, TAM1, and TAM2 show significant advantages in accuracy with a low power-delay product. AM2 has a better accuracy compared with AM1 but with a longer delay and higher power consumption. Image processing applications, including image sharpening and smoothing, are considered to show the quality of the approximate multipliers in error-tolerant applications. By utilizing an appropriate error recovery scheme, the proposed approximate multipliers achieve similar processing accuracy as exact multipliers, but with significant improvements in power.

Image Multiplier Based on Low Power Approximate Unsigned Multiplier

Approximate circuits have been considered for applications that can tolerate some loss of accuracy with improved performance and/or energy efficiency. Multipliers are key arithmetic circuits in many of these applications including digital signal processing (DSP). This multiplier leverages a newly designed approximate adder that limits its carry propagation to the nearest neighbours for fast partial product accumulation. Different levels of accuracy can be achieved by using either OR gates or the proposed approximate adder in a configurable error recovery circuit. The approximate multipliers using these two error reduction strategies are referred to as AM1 and AM2, respectively. Both AM1 and AM2 have a low mean error distance, i.e., most of the errors are not significant in magnitude. Compared with a Wallace multiplier optimized for speed, an 8×8 AM1 using four most significant bits for error reduction shows a 60% reduction in delay (when optimized for delay) and a 42% reduction in power dissipation (when optimized for area). In a 16×16 design, half of the least significant partial products are truncated for AM1 and AM2, which are thus denoted as TAM1 and TAM2, respectively. Compared with the Wallace multiplier, TAM1 and TAM2 save from 50% to 66% in power, when optimized for area. Compared with existing approximate multipliers, AM1, AM2, TAM1, and TAM2 show significant advantages in accuracy with a low power-delay product. AM2 has a better accuracy compared with AM1 but with a longer delay and higher power consumption. Image processing applications, including image sharpening and smoothing, are considered to show the quality of the approximate multipliers in error-tolerant applications. By utilizing an appropriate error recovery scheme, the proposed approximate multipliers achieve similar processing accuracy as exact multipliers, but with significant improvements in power.

CART, a Decision SLA Model for SaaS Providers to Keep QoS Regarding Availability and Performance

Cloud systems are becoming a powerful tool for business. The evidence of the advantages of offering infrastructure as a service (IaaS), platform as a service (PaaS), or software as a service (SaaS) is overwhelming. Therefore, for SaaS providers, it is essential to know the virtual resources required to optimize the service offered and to keep the quality of service (QoS) at the desired levels. This paper presents an analytic model cloud availability and response time (CART) for obtaining the best tradeoff between performance, cost, and availability in a cloud system aimed at providing software as a service. The model aims to guarantee the predetermined availability and response time (RT) agreed with customers in a service-level agreement (SLA) contract while minimizing the cost of the system. A client-transparent error recovery strategy has been considered along with a Poisson traffic model. A sensitivity analysis of the simulated and real workloads is presented to study how a specific SLA influences the cloud service performance regarding the guaranteed RT and availability. The results corroborate the goodness of the model proposed, adjusting the real system accurately. Furthermore, the obtained results provide useful guidelines for cloud or Web-server designers.

Adaptive and Roll-Forward Error Recovery in MEDA Biochips Based on Droplet-Aliquot Operations and Predictive Analysis

Digital microfluidic biochips (DMFBs) are being increasingly used in biochemistry labs for automating bioassays. However, traditional DMFBs suffer from some key shortcomings: 1) inability to vary droplet volume in a flexible manner; 2) difficulty of integrating on-chip sensors; and 3) the need for special fabrication processes. To overcome these problems, DMFBs based on micro-electrode-dot -array (MEDA) have recently been proposed. However, errors are likely to occur on a MEDA DMFB due to chip defects and the unpredictability inherent to biochemical experiments. We present fine-grained error-recovery solutions for MEDA by exploiting real-time sensing and advanced MEDA-specific droplet operations. The proposed methods rely on adaptive droplet-aliquot operations and predictive analysis of mixing. In addition, a roll-forward error-recovery method is proposed to efficiently utilize the unused part of the biochip and reduce the time required for error recovery. Experimental results on three representative benchmarks demonstrate the efficiency of the proposed error-recovery strategy.

Block Cooperation

Block-level cooperation is an endurance management technique that operates on top of error correction mechanisms to extend memory lifetimes. Once an error recovery scheme fails to recover from faults in a data block, the entire physical page associated with that block is disabled and becomes unavailable to the physical address space. To reduce the page waste caused by early block failures, other blocks can be used to support the failed block, working cooperatively to keep it alive and extend the faulty page’s lifetime. We combine the proposed technique with existing error recovery schemes, such as Error Correction Pointers (ECP) and Aegis, to increase memory lifetimes. Block cooperation is realized through metadata sharing in ECP, where one data block shares its unused metadata with another data block. When combined with Aegis, block cooperation is realized through reorganizing data layout, where blocks possessing few faults come to the aid of failed blocks, bringing them back from the dead. Our evaluation using Monte Carlo simulation shows that block cooperation at a single level (or multiple levels) on top of ECP and Aegis, boosts memory lifetimes by 28% (37%) and 8% (14%) on average, respectively. Furthermore, using trace-driven benchmark evaluation shows that lifetime boost can reach to 68% (30%) exploiting metadata sharing (or data layout reorganization).

Study of the Subjective Visibility of Packet Loss Artifacts in Decoded Video Sequences

Packet loss is a significant cause of visual impairments in video broadcasting over packet-switched networks. There are several subjective and objective video quality assessment methods focused on the overall perception of video quality. However, less attention has been paid on the visibility of packet loss artifacts appearing in spatially and temporally limited regions of a video sequence. In this paper, we present the results of a subjective study, using a methodology where a video sequence is displayed on a touchscreen and the users tap it in the positions where they observe artifacts. We also analyze the objective features derived from those artifacts, and propose different models for combining those features into an objective metric for assessing the noticeability of the artifacts. The practical results show that the proposed metric predicts visibility of packet loss impairments with a reasonable accuracy. The proposed method can be applied for developing packetization and error recovery schemes to minimize the subjectively experienced distortion in error-prone networked video systems.

An efficient error prevention and recovery scheme for multicast traffic in data center networks

In cloud application services, data are generally transmitted by multicast-based group communications to avoid transmission of duplicate packets and reduce bandwidth waste. However, the data amount in data center networks (DCNs) has increased to the scale of tremendous data over time. Tremendous data can be processed only through DCNs by using distributed computing technologies. Consequently, a large flow of multicasts has been generated. DCNs comprise a high number of commodity servers and switches, which exhibit limited capabilities to process packets. Subsequently, the rate of multicast congestion in DCNs increases substantially, resulting in severe packet loss and transmission error. Packet loss and transmission error cause all transmitting devices to retransmit data, resulting in network bandwidth waste, transmission delay, and disrupted transmission of other data. Consequently, network congestion is exacerbated, and the entire multicast tree crashes. Therefore, this paper proposes an error prevention and recovery multicast, which enables areas of errors to be effectively inferred and reduces the chain effects of errors by using repair multicast trees and multiple multicast trees that share error information, thereby effectively reducing the costs of reconstructing multicast trees. Simulation results show that the proposed scheme significantly improves the costs of reconstructing multicast trees and the transmission delay.

Efficient and Adaptive Error Recovery in a Micro-Electrode-Dot-Array Digital Microfluidic Biochip

A digital microfluidic biochip (DMFB) is an attractive technology platform for automating laboratory procedures in biochemistry. In recent years, DMFBs based on a micro-electrode-dot-array (MEDA) architecture have been proposed. MEDA biochips can provide advantages of better capability of droplet manipulation and real-time sensing ability. However, errors are likely to occur due to defects, chip degradation, and the lack of precision inherent in biochemical experiments. Therefore, an efficient error-recovery strategy is essential to ensure the correctness of assays executed on MEDA biochips. By exploiting MEDA-specific advances in droplet sensing, we present a novel error-recovery technique to dynamically reconfigure the biochip using real-time data provided by on-chip sensors. Local recovery strategies based on probabilistic-timed-automata are presented for various types of errors. An online synthesis technique and a control flow are also proposed to connect local-recovery procedures with global error recovery for the complete bioassay. Moreover, an integer linear programming-based method is also proposed to select the optimal local-recovery time for each operation. Laboratory experiments using a fabricated MEDA chip are used to characterize the outcomes of key droplet operations. The PRISM model checker and three benchmarks are used for an extensive set of simulations. Our results highlight the effectiveness of the proposed error-recovery strategy.

A Stage-Wise Soft-Error Detection Scheme for Flip-Flop Based Pipelines in Secure Cloud Servers

The shrinking feature sizes make transistors increasingly susceptible to soft errors, which can severely degrade the systems’ RAS (Reliability, Availability, and Serviceability). The tough challenge results from not only increasing SER (soft error rate) of storage cells, but also the increasing susceptibility of combinational logics to soft errors. How to efficiently detect soft errors becomes the primary problem in the Backward Error Recovery (BER) schemes that are cost-effective in soft error tolerance. This paper presents a soft error detection scheme, AUDITOR, for flip-flop based pipelines. The AUDITOR copes with both types of soft errors—single event upset (SEU) and single event transient (SET). We propose a “local-audit” fault detection mechanism, by which each pipeline stage is verified independently and the verifying result registers with a dedicated “audit” bit (V-bit). All the V-bits are distributed across the whole pipeline and synergically monitor the pipeline execution. To relax the constraint of SET detection capability imposed by the inherent fully synchronous operation mode in flip-flop based pipelines, we firstly propose using path-compensation technique to address this constraint. Furthermore, a reuse-based design paradigm is employed to reduce the implementation complexity and area overhead. The AUDITOR possesses robust detection capability and short detection latency, at the expense of about 29 % and 50 % increase in area and power consumption, respectively.

Compiler-Directed Soft Error Detection and Recovery to Avoid DUE and SDC via Tail-DMR

This article presents Clover, a compiler-directed soft error detection and recovery scheme for lightweight soft error resilience. The compiler carefully generates soft-error-tolerant code based on idempotent processing without explicit checkpoints. During program execution, Clover relies on a small number of acoustic wave detectors deployed in the processor to identify soft errors by sensing the wave made by a particle strike. To cope with DUEs (detected unrecoverable errors) caused by the sensing latency of error detection, Clover leverages a novel selective instruction duplication technique called tail-DMR (dual modular redundancy) that provides a region-level error containment. Once a soft error is detected by either the sensors or the tail-DMR, Clover takes care of the error as in the case of exception handling. To recover from the error, Clover simply redirects program control to the beginning of the code region where the error is detected. The experimental results demonstrate that the average runtime overhead is only 26%, which is a 75% reduction compared to that of the state-of-the-art soft error resilience technique. In addition, this article evaluates an alternative technique called tail-wait, comparing it to Clover. According to the evaluation with the different processor configurations and the various error detection latencies, Clover turns out to be a superior technique, achieving 1.06 to 3.49 × speedup over the tail-wait.

Guest Editorial

Guest Editorial

Timely and reliable packets delivery over internet of vehicles for road accidents prevention: a cross‐layer approach

With the envisioned era of internet of things, all aspects of Intelligent Transportation Systems will be connected to improve transport safety, relieve traffic congestion, reduce air pollution, enhance the comfort of transportation and significantly reduce road accidents. In internet of vehicles, regular exchange of current position, direction, velocity and so on, enables mobile vehicles to predict an upcoming accident and alert the human drivers in time or proactively take precautionary actions to avoid the accident. The actualisation of this concept requires the use of channel access protocols that can guarantee reliable and timely broadcast of safety messages. This study investigates the application of network coding concept to increase content of every transmission and achieve improved broadcast reliability with less number of retransmissions. In particular, the authors proposed Code Aided Retransmission-based Error Recovery (CARER) scheme, introduced a request-to-broadcast/clear-to-broadcast (RTB/CTB) handshake to overcome hidden node problem and reduce packets collision rate. In order to avoid broadcast storm problem associated with the use of RTB/CTB packet in a broadcast transmission, they developed a rebroadcasting metric used to successfully select a vehicle to rebroadcast the encoded message. The performance of CARER protocol is clearly shown with detailed theoretical analysis and further validated with simulation experiments.

Adaptive and ubiquitous video streaming over Wireless Mesh Networks

In recent years, with the dramatic improvement on scalability of H.264/MPEG-4 standard and growing demand for new multimedia services have spurred the research on scalable video streaming over wireless networks in both industry and academia. Video streaming applications are increasingly being deployed in Wireless Mesh Networks (WMNs). However, robust streaming of video over WMNs poses many challenges due to varying nature of wireless networks. Bit-errors, packet-losses and burst-packet-losses are very common in such type of networks, which severely influence the perceived video quality at receiving end. Therefore, a carefully-designed error recovery scheme must be employed. In this paper, we propose an interactive and ubiquitous video streaming scheme for Scalable Video Coding (SVC) based video streaming over WMNs towards heterogeneous receivers. Intelligently taking the benefit of path diversity, the proposed scheme initially calculates the quality of all candidate paths and then based on quality of path it decides adaptively the size and level of error protection for all packets in order to combat the effect of losses on perceived quality of reconstructed video at receiving end. Our experimental results show that the proposed streaming approach can react to varying channel conditions with less degradation in video quality.

LSB page refresh based retention error recovery scheme for MLC NAND Flash

NAND Flash memories present inevitable decline in reliability due to scaling down and multilevel cell (MLC) technology. High retention error rate in highly program/erase (P/E) cycled blocks induces stronger ECC requirement in system, causing higher spare bits cost and hardware overhead. In this paper, a least significant bit (LSB) page refresh based retention recovery scheme is proposed to improve the retention reliability of highly scaled MLC NAND Flash. As in the scheme, LSB page refresh operation induces floating gate electron re-injection to compensate charge leakage during long retention time, and realizes retention error rate reduction. Experiment result on 2x-nm MLC NAND Flash exhibits more than 78% retention error rate reduction. Comparing with reported retention error recovery scheme, the proposed scheme presents 2.5 times recovery efficiency promotion and 60% latency reduction.

Extrinsic Information Modification in the Turbo Decoder by Exploiting Source Redundancies for HEVC Video Transmitted Over a Mobile Channel

An iterative turbo decoder-based cross layer error recovery scheme for compressed video is presented in this paper. The soft information exchanged between two convolutional decoders is reinforced both by channel coded parity and video compression syntactical information. An algorithm to identify the video frame boundaries in corrupted compressed sequences is formulated. This paper continues to propose algorithms to deduce the correct values for selected fields in the compressed stream. Modifying the turbo extrinsic information using these corrections acts as reinforcements in the turbo decoding iterative process. The optimal number of turbo iterations suitable for the proposed system model is derived using EXIT charts. Simulation results reveal that a transmission power saving of 2.28% can be achieved using the proposed methodology. Contrary to typical joint cross layer decoding schemes, the additional resource requirement is minimal, since the proposed decoding cycle does not involve the decompression function.