Error Recovery Mechanisms Research Articles

Providing rapid feedback in generated modular language environments

Integrated development environments (IDEs) increase programmer productivity, providing rapid, interactive feedback based on the syntax and semantics of a language. A heavy burden lies on developers of new languages to provide adequate IDE support. Code generation techniques provide a viable, efficient approach to semi-automatically produce IDE plugins. Key components for the realization of plugins are the language's grammar and parser. For embedded languages and language extensions, constituent IDE plugin modules and their grammars can be combined. Unlike conventional parsing algorithms, scannerless generalized-LR parsing supports the full set of context-free grammars, which is closed under composition, and hence can parse language embeddings and extensions composed from separate grammar modules. To apply this algorithm in an interactive environment, this paper introduces a novel error recovery mechanism, which allows it to be used with files with syntax errors -- common in interactive editing. Error recovery is vital for providing rapid feedback in case of syntax errors, as most IDE services depend on the parser from syntax highlighting to semantic analysis and cross-referencing. We base our approach on the principles of island grammars, and derive permissive grammars with error recovery productions from normal SDF grammars. To cope with the added complexity of these grammars, we adapt the parser to support backtracking. We evaluate the recovery quality and performance of our approach using a set of composed languages, based on Java and Stratego.

Amplify-and-Forward Cooperative Diversity Wireless Networks: Model, Analysis, and Monotonicity Properties

This paper models and analyzes the performance of an amplify-and-forward cooperative diversity wireless network. We propose a Markov-based model, which encompasses the following aspects: 1) the transmission using amplify-and-forward cooperative diversity at the physical layer; 2) a flow control protocol, finite and infinite transmitting buffers, and an ARQ-based error recovery mechanism at the radio link layer; and 3) a bursty traffic pattern at the application layer. We derive expressions for packet delivery probability and distribution of packet delivery delay. We numerically quantify improvement in terms of packet delivery probability and packet delivery delay for increasing SNR and/or cooperative nodes. For an additional cooperative node, we quantify the amount of SNR which can be reduced (i.e., SNR saving) without degrading the system performance. Also, the minimum SNR and cooperative nodes which satisfy a probabilistic delay bound are computed. We then derive a sufficient condition that ensures an increase in packet delivery probability. Unlike numerical evaluation of the model, this sufficient condition does not require computation of stationary distribution of the Markov chain. It only involves parameter adjustment at physical, radio link, and application layers, hence substantially reducing the computation effort. Based on the developed model, we design a power allocation algorithm, which computes the minimum transmission power under a packet delivery probability constraint. We then use the derived sufficient condition to reduce complexity of the power allocation algorithm.

Dynamic Verification of Memory Consistency in Cache-Coherent Multithreaded Computer Architectures

Multithreaded servers with cache-coherent shared memory are the dominant type of machines used to run critical network services and database management systems. To achieve the high availability required for these tasks, it is necessary to incorporate mechanisms for error detection and recovery. Correct operation of the memory system is defined by the memory consistency model. Errors can therefore be detected by checking if the observed memory system behavior deviates from the specified consistency model. Based on recent work, we design a framework for dynamic verification of memory consistency (DVMC). The framework consists of mechanisms to verify three invariants that are proven to guarantee that a specified memory consistency model is obeyed. We describe an implementation of the framework for the SPARCv9 architecture, and we experimentally evaluate its performance using full-system simulation of commercial workloads.

Stability of digital control systems implemented in error-recoverable computers

Safety-critical, real-time applications make use of fault-tolerant digital control systems to achieve their performance goals. Even though these digital control systems are fault-tolerant, they are susceptible to errors induced by common-mode faults, since these errors cannot be masked by standard redundancy provisions. Such errors can be handled by special error correction mechanisms, which could require stopping the control law computations while the errors are removed. Thus, the effect of these special error recovery mechanisms on digital control systems needs to be understood. This paper presents a comprehensive study of the effect of three error recovery mechanisms–rollback, reset and cold restart–on the stability of digital closed-loop control systems. The effect of the faults, detected and handled by these error recovery mechanisms, on the digital control system is modelled by a set of interference maps. It is assumed that the arrival and departure of common-mode faults can be represented by a Markov process. The overall system behaviour is then described by a Markov jump linear model, whose stability is explored using standard techniques from the literature. The result of this analysis is a new metric, the minimum average interarrival spacing (MAIS), which is useful for comparing the performance of different error recovery mechanisms and for designing new fault-tolerant controllers. The theoretical results are illustrated via Monte Carlo simulations that show the effects of common-mode faults on the closed-loop stability of the longitudinal dynamics of an AFTI/F-16 aircraft.

Frameworks for designing and implementing dependable systems using Coordinated Atomic Actions: A comparative study

This paper 1 Some preliminary results included in this paper were presented at 17th International Symposium on Software Reliability Engineering (ISSRE’06) (see Capozucca et al., 2006). 1 presents ways of implementing dependable distributed applications designed using the Coordinated Atomic Action (CAA) paradigm. CAAs provide a coherent set of concepts adapted to fault tolerant distributed system design that includes structured transactions, distribution, cooperation, competition, and forward and backward error recovery mechanisms triggered by exceptions. DRIP (Dependable Remote Interacting Processes) is an efficient Java implementation framework which provides support for implementing Dependable Multiparty Interactions (DMI). As DMIs have a softer exception handling semantics compared with the CAA semantics, a CAA design can be implemented using the DRIP framework. A new framework called CAA-DRIP allows programmers to exclusively implement the semantics of CAAs using the same terminology and concepts at the design and implementation levels. The new framework not only simplifies the implementation phase, but also reduces the final system size as it requires less number of instances for creating a CAA at runtime. The paper analyses both implementation frameworks in great detail, drawing a systematic comparison of the two. The CAAs behaviour is described in terms of Statecharts to better understand the differences between the two frameworks. Based on the results of the comparison, we use one of the frameworks to implement a case study belonging to the e-health domain.

Interlayer Interaction in a Layered Error-Control Scheme for Mobile Wireless-Data Networks

Interlayer interaction of a layered error-recovery mechanism to act against channel errors for wireless-data communications is examined in this paper. Error-control designs are implemented at two different layers in the protocol stack. A finite number of retransmissions is performed at the lower layer by a mix-mode automatic-repeat request as the primary error removal. At the upper layer, a time-out mechanism is employed, together with a packet-level coding technique, as the secondary error elimination. Performance of the proposed scheme is analyzed and verified by simulations. Through numerical experiments, we have demonstrated how the system performance is influenced by layer parameters. It is discovered that error-correcting capability needs to function at the upper layer to ensure a good system performance

Error recovery mechanism for grid-based workflow within SLA context

Service Level Agreements (SLAs) serve as a foundation for a reliable and predictable job execution at remote grid sites. In this paper, we describe an error recovery mechanism for workflow within the SLA context, coping with catastrophic failure when one or several High Performance Computing Centers (HPCCs) are detached from the grid system. We propose an algorithm to detect all affected sub-jobs when the error happens and an algorithm to remap those sub-jobs to the remaining healthy HPCCs with makespan optimise. The experiment result shows that our mechanism discovers a higher quality solution in a shorter time period than other existing methods.

Enhancements of T-REFWA to mitigate link error-related degradations in hybrid wired/wireless networks

With the on-going wireless access technologies, the Internet has become accessible anytime anywhere. In wireless networks, link errors significantly degrade the performance of the transmission control protocol (TCP). To cope with this issue, this paper improves the recently-proposed terrestrial REFWA (T-REFWA) scheme by adding a new error recovery mechanism to its original design. In the T-REFWA scheme, senders are acknowledged with appropriate sending rates at which an efficient and fair utilization of network resources can be achieved. As the feedback values are computed independently of link errors, senders can keep transmitting data at high rates even in case of link error occurrences. Using this feature, the proposed error recovery mechanism can achieve high throughput in environments with high bit error rates. The throughput is further improved by disabling the exponential backoff algorithm of TCP so that long idle times are avoided in case of link errors. We show through simulations that the proposed method improves TCP performance in high bit error rates. Compared with several TCP variants, the proposed error recovery scheme exhibits higher link utilization and guarantees system fairness for different bit error rates.

Generic Fault Tolerant Software Architecture Reasoning and Customization

This paper proposes a novel heterogeneous software architecture GFTSA (Generic Fault Tolerant Software Architecture) which can guide the development of safety critical distributed systems. GFTSA incorporates an idealized fault tolerant component concept, and coordinated error recovery mechanism in the early system design phase. It can be reused in the high level model design of specific safety critical distributed systems with reliability requirements. To provide precise common idioms & patterns for the system designers, formal language Object-Z is used to specify GFTSA. Formal proofs based on Object-Z reasoning rules are constructed to demonstrate that the proposed GFTSA model can preserve significant fault tolerant properties. The inheritance & instantiation mechanisms of Object-Z can contribute to the customization of the GFTSA formal model. By analyzing the customization process, we also present a template of GFTSA, expressed in x-frames using the XVCL (XML-based Variant Configuration Language) methodology to make the customization process more direct & automatic. We use an LDAS (Line Direction Agreement System) case study to illustrate that GFTSA can guide the development of specific safety critical distributed systems

Lateral error recovery for media streaming in application-level multicast

We consider media streaming using application-level multicast (ALM) where packet loss has to be recovered via retransmission in a timely manner. Since packets may be lost due to congestion, node failures, and join and leave dynamics, traditional "vertical" recovery approach where upstream nodes retransmit the lost packets is no longer effective. We therefore propose lateral error recovery (LER). In LER, hosts are divided into a number of planes, each of which forms an independent ALM tree. Since error correlation across planes is low, a node effectively recovers its error by "laterally" requesting retransmission from nearby nodes in other planes. We present analysis on the complexity and recovery delay on LER. Using Internet-like topologies, we show via simulations that LER is an effective error recovery mechanism. It achieves low overhead in terms of delivery delay (i.e., relative delay penalty) and physical link stress. As compared with traditional recovery schemes, LER attains much lower residual loss rate (i.e., loss rate after retransmission) under a certain deadline constraint. The performance can be substantially improved in the presence of some reliable proxies.

트랜스포트 계층 이동성 지원 방안에서의 오류 및 혼잡제어 알고리즘 성능분석

IPv6 네트워크에서 SCTP를 기반으로 하여 트랜스포트 계층에서 이동성을 지원하는 방안을 제안하였다. 제안하는 방안에서는 단말의 이동에 따라 SCTP 연결에 매핑되는 종단 주소를 변경하기 위한 적절한 시점을 판단하는 기준을 제안하였고, 핸드오버에 효율적으로 대처하는 오류 복구 메커니즘을 제안하였다. 또한, 수치적 분석을 통해 기존 SCTP에 비하여 제안하는 방안이 핸드오버 지연과 손실복구시간을 줄임을 보였다. In this paper, we propose an approach to transport layer mobility support leveraging the SCTP extension dubbed dynamic address reconfiguration in IPv6 networks. Timing issues related to the end-to-end address management, and a novel error recovery mechanism associated with a handover are discussed. The proposed error recovery mechanism is analyzed and compared to that of the plain SCTP to show that it reduces the handover latency and error recovery time.

Secure performance enhancing proxy: To ensure end-to-end security and enhance TCP performance over IPv6 wireless networks

It is a well known fact that TCP is incapacitated to distinguish congestion losses in the wired network from corruption losses occurring in the wireless link and this inability results in poor performance of TCP in a hybrid wired-cum-wireless scenario. Most of the solutions previously proposed to address this problem are designed oblivious of the security considerations and violate end-to-end TCP semantics. Achieving improved TCP performance together with ensuring end-to-end security necessitates the co-existence of security mechanisms like IPSEC and performance enhancing solutions. However, IP security and TCP performance have been traditionally dealt with in a mutually exclusive manner. We propose an innovative mechanism, Secure Performance Enhancing Proxy (SPEP), to address the seemingly arduous problem of enhancing TCP performance over wireless networks, preserving end-to-end TCP semantics as well as ensuring end-to-end security. The proposed SPEP scheme decouples error detection and error distinction mechanism from error recovery mechanism which not only facilitates in performance improvement but also offers multifarious advantages discussed in the paper. We have implemented the proposed scheme in FreeBSD 4.5 and conducted experiments in a controlled test bed setup. Our results show improved TCP performance in a secured environment with introduction of minimal overhead.

Dependability Evaluation of a Fault-Tolerant Processor by GSPN Modeling

High dependability has become a paramount requirement for computing systems, as they are increasingly used in business & life critical applications. Advances in the design & manufacturing of semiconductor devices have increased the performance of computing systems at a dazzling pace. However, smaller transistor dimensions, lower power voltages, and higher operating frequencies have negatively impacted dependability by increasing the probability of occurrence of transient & intermittent faults. This paper discusses the main trends in dependability of semiconductor devices, and presents a candidate architecture for a fault-tolerant microprocessor. Dependability of the processor is analyzed, and the advantages provided by fault tolerance are underscored. The effect of the higher rates of occurrence of the transient & intermittent faults on a typical microprocessor is evaluated with the aid of GSPN modeling. Dependability analysis shows that a five times increase of the rate of occurrence of the transients leads to about five time lower MTBF, if no error recovery mechanisms are employed. Significantly lower processor availability is also observed. The fault-tolerant processor is devised to mitigate the impact of the higher transient & intermittent fault rates. The processor is based on core redundancy & state checkpointing, and supports three levels of error recovery. First, recovery from a saved state (SSRC) is attempted. The second level consists of a retry (SSRR), and is activated when the first level of recovery fails. Processor reset, followed by reintegration under the operating system control (RB), is the third level of recovery. Dependability analysis, based on GSPN, shows that fault-tolerance features of the processor preserve the MTBF, even if the rate of the transient faults nearly doubles. In terms of availability, a four-time increase of the rate of occurrence of the transients is compensated. The effect of intermittent faults is also analyzed. A five-time increase of the failure rate of the intermittent faults may lower MTBF by 31% to 33%. MTBF decreases even more, by 45% to 67%, if bursts of errors are considered. Intermittent faults have a negative impact on availability as well. Maintaining the dependability of complex integrated circuits to the level available today is becoming a challenge as semiconductor integration continues at a fast pace. Fault avoidance techniques, mainly based on process technology & circuit design, will no be able to fully mitigate the impact of higher rates of occurrence of transient & intermittent faults. As a result, fault-tolerant features, specific to custom designed components today, ought to be employed by COTS circuits, in the future. Enhanced concurrent error detection & correction, self checking circuits, space & time redundancy, triplication, and voting all need to be integrated into semiconductor devices in general, and microprocessors in particular, in order to improve fault & error handling.

Analysis of Error Recovery Schemes for Networks on Chips

In this article, we discuss design constraints to characterize efficient error recovery mechanisms for the NoC design environment. We explore error control mechanisms at the data link and network layers and present the schemes' architectural details. We investigate the energy efficiency, error protection efficiency, and performance impact of various error recovery mechanisms.

Syntax error repair for a Java-based parser generator

This article presents an implementation of an error repair algoritm for the JavaCC parser generator. Three different approaches, the Burke-Fisher error repair, follow-set error repair and panic mode, have been implemented. These algorithms have been altered and combined in order to get improved results. Using this adapted implementation of JavaCC an improved syntax error recovery mechanism is available.

Designing and evaluating a human factors investigation tool (HFIT) for accident analysis

In an attempt to improve the investigation of the human factors causes of accidents in the UK offshore oil and gas industry, a Human Factors Investigation Tool (HFIT) was developed with the sponsorship of the UK Regulator, the Health and Safety Executive, and four exploration-related companies. The tool was developed on a theoretical basis with reference to existing tools and models and it collects four types of human factors information including (a) the action errors occurring immediately prior to the incident, (b) error recovery mechanisms, in the case of near misses, (c) the thought processes which lead to the action error and (d) the underlying causes. The investigation tool was evaluated on the basis of (i) an inter-rater reliability assessment, (ii) usability assessment, (iii) case studies and (iv) an evaluation system developed by Benner [Benner, L. 1985. Rating accident models and investigation methodologies. Journal of Safety Research 16, 105–126] Evaluation system. Although there is a need for further validation and analysis of HFIT using more realistic accident scenario exercises, some validation of the tool has been possible. In addition, it has been shown, in a small sample of accident investigations, that HFIT was found to be useful for the development of remedial actions, one of the main objectives of the tool.

An Approach to Modeling Error in Air-Midas Using Contextual Control Model

Predictability of the possible avenues of human error is important for designing error recovery mechanisms in systems' interfaces. Our approach for modeling errors during the taxiing and pre-flight phase, involves using Hollnagel's (1993) Contextual Control Model (CoCoM). Hollnagel postulates that changes in the human's operational context make her switch control modes or cognitive strategies. Previously, Verma & Corker (2002) encoded rules to implement CoCoM for Air Traffic Controllers (ATCo) in the Air-MIDAS (Man-Machine Integrated Design and Analysis System) architecture. They defined the operational context as the number of simultaneous goals and the event horizon time required to successfully complete those goals, and also encoded behavior associated with three types of cognitive strategies- unplanned, tactical, and strategic. In this study, new sets of rules are being coded for the pilots, such mat changes in the context will cause the simulated operator to change cognitive strategies. The dependent variables of interest are cognitive strategies used by pilot-agents, workload, status of tasks (completed, aborted, working), and consequences of errors performed.

A fault-tolerant software architecture for COTS-based software systems

This paper considers the problem of integrating Commercial off-the-shelf (COTS) components into systems with high dependability requirements. Such components are built to be reused as black boxes that cannot be modified. The system architect has to rely on techniques that are external to the component for resolving mismatches between the services required and provided that might arise in the interaction of the component and its environment. The paper puts forward an approach that employs the layer-based C2 architectural style for structuring error detection and recovery mechanisms to be added to the component during system integration.

Generating LR syntax error messages from examples

LR parser generators are powerful and well-understood, but the parsers they generate are not suited to provide good error messages. Many compilers incur extensive modifications to the source grammar to produce useful syntax error messages. Interpreting the parse state (and input token) at the time of error is a nonintrusive alternative that does not entangle the error recovery mechanism in error message production. Unfortunately, every change to the grammar may significantly alter the mapping from parse states to diagnostic messages, creating a maintenance problem. Merr is a tool that allows a compiler writer to associate diagnostic messages with syntax errors by example, avoiding the need to add error productions to the grammar or interpret integer parse states. From a specification of errors and messages, Merr runs the compiler on each example error to obtain the relevant parse state and input token, and generates a yyerror() function that maps parse states and input tokens to diagnostic messages. Merr enables useful syntax error messages in LR-based compilers in a manner that is robust in the presence of grammar changes.

Undo as concurrent inverse in group editors

As an important mechanism for error recovery and exploration of alternatives in interactive and collaborative applications, an undo facility should have the capability of undoing any operation at any time. However, supporting undo in collaborative applications is technically challenging and none of the existing group undo solutions is able to offer such a capability. In this article, we contribute an undo solution with such a capability for group text editors. The basic idea is to interpret an undo command as a concurrent inverse operation by means of operational transformation. To cope with the high complexity of group undo, a generic undo framework has been adopted to separate undo policy from the undo mechanism and to separate transformation control algorithms from transformation functions. The proposed undo solution consists of a generic transformation control algorithm that is capable of generating, transforming, and representing valid inverse operations in any context, and a set of transformation functions that are capable of preserving undo-related transformation conditions and properties. Formal proofs are provided to show the correctness of the undo transformation control algorithm in achieving the required undo effect, undo property, and consistency properties. Solutions to the known undo puzzles are provided to show soundness of the transformation functions. A Web-based group text editor REDUCE (REal-time Distributed Unconstrained Cooperative Editing) has been implemented to demonstrate the feasibility and usability of the proposed undo and other technical solutions. The proposed undo solution is generally applicable to collaborative applications that support concurrent insertion and deletion on shared documents consisting of one or multiple dimensions of linearly ordered data objects with positional references.