Practical realization of decision feedback equalizers (DFEs) has to date been limited to at most two taps in 100-Gb/s long-reach (LR) wireline applications due to significant power, area, and timing costs. This article presents a systolic many-tap low-complexity sliding-block decision feedback equalizer (SB-DFE) that overcomes the implementation challenges of conventional DFEs with no performance loss. A nine-tap configuration is demonstrated in a 112-Gb/s analog-to-digital converter (ADC)-digital signal processing (DSP) four-level pulse amplitude modulation (PAM-4) LR wireline receiver implemented in 7-nm FinFET. The architecture partitions the received signal into overlapping but computationally independent blocks thereby breaking the feedback loop of the DFE and allowing logic pipelining. Unlike existing feedback-breaking techniques, the computational overhead of the SB-DFE can be made arbitrarily small for any tap count—indeed, we show the practicality of SB-DFE implementations exceeding 30 taps. Optimized pipeline cuts are employed to minimize the latency through the SB-DFE while maintaining timing margin. The nine-tap SB-DFE is paired with a five-precursor tap feedforward equalizer (FFE) and compared to a two-tap-DFE 15-tap-FFE reference DSP implemented in the same receiver. A bit error rate of 2 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times $ </tex-math></inline-formula> 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">−12</sup> is measured over a 36-dB loss channel—at least an order-of-magnitude reduction compared to the reference DSP. Power is reduced by 0.33 pJ/b. DSP gate area is reduced by 30%. Noise tolerance is improved by 0.2-mV <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">RMS</sub> . Error-free operation is demonstrated on an RS(544,514) KP4 forward error correction (FEC)-encoded link even when the DFE tap values are manually stressed. Techniques for further reduction in complexity are described.
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