Error Floor Region Research Articles

A General Structure for Rate-Compatible Concatenated Codes

In this letter, a general concatenated code structure is presented, encompassing both parallel and serially concatenated codes as special cases. The structure provides a unifying framework for the analysis of concatenated codes and offers new degrees of freedom for code design. Performance analysis based on error bounds in the error floor region and suggestions for suitable design criteria are provided, together with a design approach for the waterfall region. The proposed structure allows for constructing very high-rate codes with no penalty in the error floor region and good performance in the waterfall region

On the design of rate‐compatible serially concatenated convolutional codes

AbstractA powerful class of rate‐compatible serially concatenated convolutional codes (SCCCs) has been proposed based on minimising analytical upper bounds on the error probability in the error floor region. In this paper, this class of codes is further investigated by combining analytical upper bounds with extrinsic information transfer chart analysis to improve performance in the waterfall region. Following this approach, we construct a family of rate‐compatible SCCCs with low complexity and good performance in both the error floor and the waterfall regions over a broad range of code rates. The proposed codes outperform standard SCCCs and have a similar performance as more complex parallel concatenated convolutional codes (PCCCs). The proposed codes perform particularly well for high code rates. Copyright © 2007 John Wiley & Sons, Ltd.

LDPC Codes Based on Latin Squares: Cycle Structure, Stopping Set, and Trapping Set Analysis

It is well known that certain combinatorial structures in the Tanner graph of a low-density parity-check (LDPC) code exhibit a strong influence on its performance under iterative decoding. These structures include cycles, stopping/trapping sets, and parameters such as the diameter of the code. In general, it is very hard to find a complete characterization of such configurations in an arbitrary code, and even harder to understand the intricate relationships that exist between these entities. It is, therefore, of interest to identify a simple setting in which all the described combinatorial structures can be enumerated and studied within a joint framework. One such setting is developed in this paper, for the purpose of analyzing the distribution of short cycles and the structure of stopping and trapping sets in Tanner graphs of LDPC codes based on idempotent and symmetric Latin squares. The parity-check matrices of LDPC codes based on Latin squares have a special form that allows for connecting combinatorial parameters of the codes with the number of certain subrectangles in the Latin squares. Subrectangles of interest can be easily identified, and in certain instances, completely enumerated. This study can be extended in several different directions, one of which is concerned with modifying the code design process in order to eliminate or reduce the number of configurations bearing a negative influence on the performance of the code. Another application of the results includes determining to which extent a configuration governs the behavior of the bit-error rate curve in the waterfall and error-floor regions

Weight distribution of turbo codes with convolutional interleavers

A simple algorithm for the weight calculation of turbo codes with convolutional interleavers is presented. For codes with short interleaver lengths, the weight distributions are computed using conventionally proposed methods and then utilised together with the interleaver properties to determine the weight specifications for the code with a longer desired length. Based on the calculated weights, a new upper bound for the code is computed. It agrees with simulation results of the code performance in the error-floor region.

The Capacity Region of Frequency-Selective Gaussian Interference Channels Under Strong Interference

Practical applications that employ coding for large alphabets often partition the alphabet set into two or more layers and encode each symbol by using some suitable prefix coding for each layer. In this paper, we formulate the problem of finding an alphabet partitioning for the de- sign of a two-layer semiadaptive code as an optimization problem, and give a solution based on dynamic programming. However, the complexity of the dynamic-programming approach can be quite prohibitive for a long se- quence and a very large alphabet size. Hence, we also give a simple greedy heuristic algorithm whose running time is linear in the length of the input sequence, irrespective of the underlying alphabet size. Although our dy- namic programming and greedy algorithms do not provide a globally op- timal solution for the alphabet-partitioning problem, experimental results demonstrate that superior prefix coding schemes for large alphabets can be designed using our new approach. One such setting is developed in this paper, for the purpose of analyzing the distribution of short cycles and the structure of stopping and trapping sets in Tanner graphs of LDPC codes based on idempotent and symmetric Latin squares. The parity-check matrices of LDPC codes based on Latin squares have a special form that allows for connecting the combinatorial parameter of the codes with the number of certain subrectangles in the Latin squares. Subrectangles of interest can be easily identified, and in certain instances, completely enumerated. The presented study can be extended in several different directions, one of which is concerned with modifying the code-de- sign process in order to eliminate or reduce the number of configurations bearing a negative influence on the performance of the code. Another ap- plication of the results includes determining to which extent a configura- tion governs the behavior of the bit-error rate curve in the waterfall and error-floor regions.

On the design of bit-interleaved turbo-coded modulation with low error floors

In this paper, we introduce an algorithm to optimize the performance in the error-floor region of bit-interleaved turbo-coded modulation (BITCM) on the additive white Gaussian noise channel. The key ingredient is an exact turbo code weight distribution algorithm producing a list of all codewords in the underlying turbo code of weight less than a given threshold. In BITCM, the information sequence is turbo-encoded, bit-interleaved, and mapped to signal points in a signal constellation. Using the union-bounding technique, we show that a well-designed bit interleaver is crucial to have a low error floor. Furthermore, the error-rate performance in the waterfall region depends on the bit interleaver, since the level of protection from channel noise on the bit level depends on the bit position and the neighboring bit values within the same symbol in the transmitted sequence. We observe a tradeoff between error-rate performance in the waterfall and error-floor regions, as illustrated by an extensive case study of a high-rate BITCM scheme. This tradeoff is typical in iterative decoding of turbo-like codes. The reported case study shows that it is possible to design bit interleavers with our proposed algorithm with equal or better performance in the waterfall region and superior performance in the error-floor region, compared with randomly generated bit interleavers. In particular, we were able to design BITCM schemes with maximum-likelihood decoding frame-error rates of 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-12</sup> and 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-17</sup> at 2.6 and 3.8 dB away from unconstrained channel capacity, at spectral efficiencies of 3.10 and 6.20 b/s/Hz using square 16 and 256-quadrature amplitude modulation signal constellations, respectively

Study of Turbo Codes and Decoding in Binary Erasure Channel Based on Stopping Set Analysis

SUMMARY In this paper, we define a stopping set of turbo codes with the iterative decoding in the binary erasure channel. Based on the stopping set analysis, we study the block and bit erasure probabilities of turbo codes and the performance degradation of the iterative decoding against the maximum-likelihood decoding. The error floor performance of turbo codes with the iterative decoding is dominated by the small stopping sets. The performance degradation of the iterative decoding is negligible in the error floor region, so the error floor performance is asymptotically dominated by the low weight codewords.

Simulation Probability Density Function Design for Turbo Codes

We research on an importance sampling (IS) simulation to estimate a low error probability of turbo codes. The simulation time reduction in IS depends on another probability density function (p.d.f.) called simulation p.d.f. The previous IS simulation method can not evaluate the error probability on the low SNR and waterfall region. We derive the optimal simulation p.d.f. which gives the perfect estimator. A new simulation p.d.f. design, which is related to the optimal one, is proposed to overcome the problem of the previous IS method. The proposed IS simulation can evaluate all possible error patterns. Finally, some computer simulations show that the proposed method can evaluate the error probability on the low SNR, waterfall, and error floor regions. At the evaluation of the BER of 10-7, the simulation time of the proposed method is about 1/350 times as short as that of the Monte-Carlo simulation. When the BER is less than 7 × 10-8, the proposed method requires shorter simulation time than the conventional IS method.

Time-Varying Turbo Codes

Turbo codes typically utilize time-invariant component codes whose total encoder memory is no greater than 4. In this letter, turbo codes with time-varying component codes are studied via EXIT analysis, distance spectrum analysis and simulation. Turbo codes with time-varying component codes and memory 6 are shown to have similar performance in the waterfall region and superior performance in the error floor region when compared to both the original memory 4 Berrou turbo code and the memory 8 big numerator-little denominator turbo codes.

On the frame-error rate of concatenated turbo codes

Turbo codes with long frame lengths are usually constructed using a randomly chosen interleaver. Statistically, this guarantees excellent bit-error rate (BER) performance but also generates a certain number of low weight codewords, resulting in the appearance of an error floor in the BER curve. Several methods, including using an outer code, have been proposed to improve the error floor region of the BER curve. We study the effect of an outer BCH code on the frame-error rate (FER) of turbo codes. We show that additional coding gain is possible not only in the error floor region but also in the waterfall region. Also, the outer code improves the iterative APP decoder by providing a stopping criterion and alleviating convergence problems. With this method, we obtain codes whose performance is within 0.6 dB of the sphere packing bound at an FER of 10/sup -6/.

Performance of a turbo coded multicarrier DS/CDMA system with nonuniform repetition coding

This paper presents a turbo coded multicarrier direct sequence code division multiple access (DS/CDMA) system, where the outputs of a turbo encoder are repetition coded at multiple rates and transmitted in parallel over a number of subchannels. A performance bound useful in the so-called error floor region is obtained for Rayleigh fading channels when different diversity orders are given to each turbo code symbol. Simulation results are also provided for the low signal-to-noise ratio (SNR) region where the bound is not applicable. It is observed that the error floor can be lowered, with some performance loss in the low SNR region, by applying nonuniform repetition coding to the turbo code symbols.