Error Floor Performance Research Articles

Jointly Decoded Raptor Codes: Analysis and Design for the BIAWGN Channel

We are interested in the analysis and optimization of Raptor codes under a joint decoding framework, that is, when the precode and the fountain code exchange soft information iteratively. We develop an analytical asymptotic convergence analysis of the joint decoder, derive an optimization method for the design of efficient output degree distributions, and show that the new optimized distributions outperform the existing ones, both at long and moderate lengths. We also show that jointly decoded Raptor codes are robust to channel variation: they perform reasonably well over a wide range of channel capacities. This robustness property was already known for the erasure channel but not for the Gaussian channel. Finally, we discuss some finite length code design issues. Contrary to what is commonly believed, we show by simulations that using a relatively low rate for the precode, we can improve greatly the error floor performance of the Raptor code.

Combinatorial Interleavers for Systematic Regular Repeat-Accumulate Codes [Transactions Letters

This paper proposes novel interleaver and accumulator structures for systematic, regular repeat-accumulate (RA) codes. It is well known that such codes are amenable to iterative (sum-product) decoding on the Tanner graph of the code, yet are as readily encodable as turbo codes. In this paper, interleavers for RA codes are designed using combinatorial techniques as a basis for deterministic interleaver constructions, yielding RA codes whose Tanner graphs are free of 4-cycles. Further, a generalized RA code accumulator structure is proposed, leading to codes, termed w3RA codes, whose parity-check matrices have many fewer weight-2 columns than conventional RA codes. The w3RA codes retain the low-complexity encoding of conventional RA codes and exhibit improved error-floor performance.

Constructing LDPC codes by error minimization progressive edge growth

A novel approach to constructing Tanner graphs using progressive edge growth (PEG) is introduced. It yields LDPC codes providing minimized block error probability in Binary Erasure Channels (BEC). The constructed codes exhibit superior performance over codes generated by previously known algorithms, both for BEC and AWGN channels. Furthermore, an upper bound on the expected block error probability in the error floor region of the generated codes is derived. This allows analytical prediction of the codes' error floor performance. Finally, the method is generalized for generating simple in implementation LDPC codes based on lifted graphs.

Concatenated twist Hadamard codes

In this letter, a new class of low-rate error-correcting codes named twist Hadamard codes (TwHC) are designed based on two single parity check constraints in bi-orthogonal Hadamard codes. TwHC consists of two branches zigzag Hadamard codes (ZHC) twisted together. Its decoding complexity is very low with the help of fast Hadamard transform. Simulation results show that, compared with concatenated ZHC, parallel concatenated TwHC can significantly improve error floor performance of short codes.

On Analysis and Design of Low Density Generator Matrix Codes for Continuous Phase Modulation

We investigate the analysis and design of low density generator matrix (LDGM) codes for continuous phase modulation (CPM). The system uses LDGM codes as an outer code for CPM. For additive white Gaussian noise channels, we derive the union bound to analyze the error floor performance. Design principles for lowering error floors are suggested from this analysis. We propose a design approach of jointly considering the LDGM code degree and the CPM modulation index. Then we consider the rate-adaptive system for slowly fading channels. By changing the rate of the LDGM codes, the information rate of the CPM signals is adapted according to channel variations. We use a low-rate LDGM code as the mother code. Higher rates are achieved by puncturing the output of these codes. To exploit the rate-flexible property of punctured LDGM codes, a rate function is proposed to calculate the rate of each transmitted block. Thus, we can have a quasi-continuous information rate. Numerical results show that this approach can improve the energy efficiency from a discrete-rate adaptation. Using the rate-adaptive approach, up to 11 dB transmitted energy gain can be achieved from the non-adaptive scheme in the low bit-error-rate region (smaller than 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-3</sup> ) for minimum shift keying (MSK).

Design of Prunable Interleavers for Parallel Turbo Decoder Architectures

In this paper we propose a technique to implement in a parallel fashion a turbo decoder based on an arbitrary permutation, and to expand its interleaver in order to produce a family of prunable S-random interleavers suitable for parallel implementations. We show that the spread properties of the obtained interleavers are almost optimal and we prove by simulation that they are very competitive in terms of error floor performance. A few details on the decoder architecture are also provided

Improvements in belief-propagation decoding based on averaging information from decoder and correction of clusters of nodes

In this letter we provide several methods to improve belief-propagation (BP) decoding of low-density parity-check codes. The methods use additional processing of the decoded information during the decoding process and are grouped into two categories. The first category is useful in the waterfall performance region and is based on processing averaged information obtained from the decoder. Several choices of the feedback information utilized in additional processing are introduced. The second category is useful in the error-floor performance region and is based on fixing clusters of symbols simultaneously, again utilizing the information obtained by monitoring the decoder. We demonstrate on a code example that our methods achieve sizeable gains compared to the original BP decoder

Study of Turbo Codes and Decoding in Binary Erasure Channel Based on Stopping Set Analysis

SUMMARY In this paper, we define a stopping set of turbo codes with the iterative decoding in the binary erasure channel. Based on the stopping set analysis, we study the block and bit erasure probabilities of turbo codes and the performance degradation of the iterative decoding against the maximum-likelihood decoding. The error floor performance of turbo codes with the iterative decoding is dominated by the small stopping sets. The performance degradation of the iterative decoding is negligible in the error floor region, so the error floor performance is asymptotically dominated by the low weight codewords.

Constraining LDPC degree distributions for improved error floor performance

The error floor performance of finite-length irregular low-density parity-check (LDPC) codes can be very poor if code degree distributions are chosen to optimize the threshold performance. In this paper we show that by constraining the optimization process, a balance between threshold and error floor' performance can be obtained. The resulting degree distributions give the best threshold performance subject to some minimum requirement on the error floor

Constraining LDPC degree distributions for improved error floor performance

The error floor performance of finite-length irregular low-density parity-check (LDPC) codes can be very poor if code degree distributions are chosen to optimize the threshold performance. In this paper we show that by constraining the optimization process, a balance between threshold and error floor' performance can be obtained. The resulting degree distributions give the best threshold performance subject to some minimum requirement on the error floor

Field programmable gate array (FPGA) for iterative code evaluation

Iterative codes such as low density parity check (LDPC) codes and turbo product codes (TPC) are of interest for data storage applications. To apply these codes to digital recording systems, two possible schemes are considered in this paper. In the first scheme, a single LDPC code of column weight j>2 is used to replace the Reed-Solomon (RS) code of the conventional channel. In the second scheme, an iterative code is used as the inner code and is concatenated with an outer RS code. Single parity check TPC code is considered for this scheme. We developed a high-throughput field programmable gate array (FPGA) platform to evaluate the error floor performance of LDPC codes and the error statistics of TPC codes in partial response (PR) channel with turbo equalization. High rate codes (rate 8/9 for LDPC code and rate 0.935 for TPC code) are evaluated for magnetic recoding application. The bit error rate (BER) performance of LDPC code down to 10/sup -10/ can be reached within 2 h using the FPGA platform. The TPC code error statistics are evaluated using about 10/sup 11/ bits at different signal-to-noise (SNR) levels. For practical implementation complexity and power consumption, 2 channel iterations and 2 TPC decoder iterations are employed. The results show that the gain by applying TPC code under 2 channel iterations and 2 TPC decoder iterations is marginal.

Flexible construction of irregular partitioned permutation LDPC codes with low error floors

Irregular partitioned permutation (IPP) low-density parity-check (LDPC) codes have been recently introduced to facilitate hardware implementation of belief propagation (BP) decoders. In this letter, we present a new method to construct IPP LDPC codes with great flexibility in the selection of code parameters. Meanwhile, small stopping sets are avoided in the code construction, thus good error floor performance can be achieved.

Analysis and design of symbol mappers for iteratively decoded BICM

Iterative decoding and demodulation of bit-interleaved coded modulation (BICM) is investigated. The union bound on the error probability of BICM with maximum-likelihood (ML) decoding is derived with the assumption of a uniform interleaver. Based on the union bound, it is shown that an interleaving gain is achievable for BICM at high signal-to-noise ratio (SNR). The design rules on the symbol mapper for optimal asymptotic performance at high SNR are derived and a new symbol mapper, called the maximum squared Euclidean weight (MSEW) symbol mapper, is proposed with examples given for 8-PSK and 16-QAM. The MSEW mapper is shown by means of an extrinsic information transfer (EXIT) chart to provide the best error-floor performance for BICM at high SNR. At low SNR, a mapper doping technique is proposed that combines the MSEW mapper with Gray mapper to provide a good match to a given outer code. Simulation results are also presented to confirm our analysis.

Transmission of Nonuniform Memoryless Sources via Nonsystematic Turbo Codes

We investigate the joint source-channel coding problem of transmitting nonuniform memoryless sources over binary phase-shift keying-modulated additive white Gaussian noise and Rayleigh fading channels via turbo codes. In contrast to previous work, recursive nonsystematic convolutional encoders are proposed as the constituent encoders for heavily biased sources. We prove that under certain conditions, and when the length of the input source sequence tends to infinity, the encoder state distribution and the marginal output distribution of each constituent recursive convolutional encoder become asymptotically uniform, regardless of the degree of source nonuniformity. We also give a conjecture (which is empirically validated) on the condition for the higher order distribution of the encoder output to be asymptotically uniform, irrespective of the source distribution. Consequently, these conditions serve as design criteria for the choice of good encoder structures. As a result, the outputs of our selected nonsystematic turbo codes are suitably matched to the channel input, since a uniformly distributed input maximizes the channel mutual information, and hence, achieves capacity. Simulation results show substantial gains by the nonsystematic codes over previously designed systematic turbo codes; furthermore, their performance is within 0.74-1.17 dB from the Shannon limit. Finally, we compare our joint source-channel coding system with two tandem schemes which employ a fourth-order Huffman code (performing near-optimal data compression) and a turbo code that either gives excellent waterfall bit-error rate (BER) performance or good error-floor performance. At the same overall transmission rate, our system offers robust and superior performance at low BERs (< 10/sup -4/), while its complexity is lower.

Selective Avoidance of Cycles in Irregular LDPC Code Construction

This letter explains the effect of graph connectivity on error-floor performance of low-density parity-check (LDPC) codes under message-passing decoding. A new metric, called extrinsic message degree (EMD), measures cycle connectivity in bipartite graphs of LDPC codes. Using an easily computed estimate of EMD, we propose a Viterbi-like algorithm that selectively avoids small cycle clusters that are isolated from the rest of the graph. This algorithm is different from conventional girth conditioning by emphasizing the connectivity as well as the length of cycles. The algorithm yields codes with error floors that are orders of magnitude below those of random codes with very small degradation in capacity-approaching capability.