Error Detection Techniques Research Articles

Neural in-memory checksums: an error detection and correction technique for safe in-memory inference.

The advent of in-memory computing has introduced a new paradigm of computation, which offers significant improvements in terms of latency and power consumption for emerging embedded AI accelerators. Nevertheless, the effect of the hardware variations and non-idealities of the emerging memory technologies may significantly compromise the accuracy of inferred neural networks and result in malfunctions in safety-critical applications. This article addresses the issue from three different perspectives. First, we describe the technology-related sources of these variations. Then, we propose an architectural-level mitigation strategy that involves the coordinated action of two checksum codes designed to detect and correct errors at runtime. Finally, we optimize the area and latency overhead of the proposed solution by using two accuracy-aware hardware-software co-design techniques. The results demonstrate higher efficiency in mitigating the accuracy degradation of multiple AI algorithms in the context of different technologies compared with state-of-the-art solutions and traditional techniques such as triple modular redundancy. Several configurations of our implementation recover more than 95% of the original accuracy with less than 40% of the area and less than 30% of latency overhead.This article is part of the themed issue 'Emerging technologies for future secure computing platforms'.

Fault correcting adder design for low power applications

Field Programmable Gate Arrays are extensively used in space, military, and commercial sectors due to their reprogrammable nature. In high-safety environments, ensuring fault tolerance is crucial to improving the performance of electronic and computational systems. Common fault-tolerant methods include time redundancy, double modular redundancy, triple modular redundancy, hardware redundancy, self-checking, self-repairing, and Operand Width Aware Hardware Reuse. This paper introduces a novel approach based on error correction and detection techniques, aimed at reducing hardware complexity while optimizing for low power consumption, high speed, and minimal transistor count. The proposed technique is applicable to various arithmetic circuits. Fault-correcting and fault-detecting adders were designed using a combination of components, including a full adder (comprising one XOR gate, one NOT gate, and two 2:1 multiplexers), three XOR gates, three XNOR gates, one functional unit, two inverters, and two multiplexers (2:1 MUX). To assess the fault tolerance of the design, the technique was applied to an adder circuit, with its performance in terms of power consumption, hardware usage, energy efficiency, and delay simulated using Cadence Virtuoso @90 nm technology. Pre-layout and post-layout simulation results showed a 98% reduction in power consumption, 82% energy savings, 36.5 and 55.95% transistor savings, and a 215% reduction in area overhead compared to existing fault-tolerant adders. Additionally, multiplier designs were tested to validate the fault-correcting adder design.

Integrating error correction and detection techniques in RISC-V processor microarchitecture for enhanced reliability

An essential consideration in processor design is ensuring reliability, particularly in demanding environments such as outer space and nuclear plants. To mitigate the effects of errors and enable error recovery, processors need to incorporate fault tolerance techniques. One common type of error is SEU (Single Event Upset), which affects various microelectronic devices including microprocessors, microcontrollers, and semiconductor memory devices. While error mitigation techniques have been developed for processors based on architectures like ARM (Advanced RISC Machine) and MIPS (Million Instructions Per Second), there is a gap in research for open-source ISAs (Instruction Set Architecture) like RISC-V, which this paper aims to address. This paper focuses on designing a fault-tolerant microarchitecture for a RISC-V processor that can correct one-bit errors, detect up to two-bit errors, and integrate lockstep and pipeline rollback features at a lower LUTs (Look Up Tables) consumption by re-using the same hardware pipeline for error mitigation and recovery through instruction mimicking. By incorporating these features, the proposed approach enhances the system’s fault tolerance by detecting and correcting errors caused by transient events and achieves a lower effective die size upon realization compared to contemporary works. The proposed microarchitecture design was simulated and synthesized using the Vivado Design Suite 2023.1 and implemented on a Zynq 7000 SoC ZC702 Evaluation Kit.

False Positives and Deceptive Errors in SQL Assessment: A Large-Scale Analysis of Online Judge Systems

Online Judge Systems (OJSs) play a crucial role in evaluating SQL programming skills. However, OJSs may not accurately evaluate students’ queries as the error-detection capabilities of test sets are insufficient, resulting in false positives that can mislead students and hinder their learning. This study analyzes a large-scale OJS’s evaluation dataset and identifies more than 110,000 (1.94%) false-positive queries. It also validates existing SQL error categorization and reveals a new type of logical error called deceptive error, which occurs when students construct queries that pass specific test cases but fail to solve the actual problem. This type of error has been overlooked in previous research and can provide new insights into how to improve OJSs by enhancing test cases and feedback. This study contributes to the understanding of assessment and evaluation practices and processes in programming education, particularly the contribution that OJSs make to student learning and to course, staff, and institutional development. It also suggests error prevention and detection techniques that can improve the effectiveness and fairness of OJSs in programming education and competitions.

Optimized Ensemble Techniques For Precise Software Error Detection

Optimized Ensemble Techniques For Precise Software Error Detection

Leveraging CRC Error Detection for Enhanced Error Correction in Digital Communication Systems

In this study, CRC error detection techniques will be used to not only identify but fix single-bit errors in digital communication systems. In the past, CRC codes have been employed mainly for their ability to detect errors efficiently. However, this paper suggests a new way that will make it possible to modify CRC functions and thus correct the identified errors. It is intended that by using an optimized look-up table in Verilog hardware description language with an advanced Xilinx 14.7 toolchain, this research can increase the dependability and effectiveness of error correction mechanisms found in digital systems. The study presents how to create a detailed hardware description, optimize lookup tables for minimal resource usage and increased error correction capability; then synthesizes design with Xilinx 14.7.The conclusion makes a practical contribution towards identification and removal of single-bit errors which indicates a turning point in the use of Cyclic Redundancy Check (CRC) technology from being just about error detection to full scale error correction. This enhancement has the potential to greatly increase the durability and reliability of data transmission and storage systems, especially in critical applications requiring utmost data integrity. Keywords: Cyclic Redundancy Check (CRC), Error detection, Single-bit errors, Optimized lookup table, Xilinx 14.7 toolchain.

Advanced proactive anomaly detection in multi-pattern home appliances for energy optimization

As far as home appliances are concerned, a major issue arises as malfunctions frequently go unnoticed by homeowners, consuming a significant amount of energy. Identifying this problem highlights the need for an error detection technique, which is vital to minimize energy waste while enhancing household appliance efficiency. This paper introduces an innovative method for advanced proactive anomaly detection in multi-pattern home appliances using variational autoencoders (VAE). Specifically, a CNN-LSTM based VAE integrating a novel dynamic threshold method is exploited for identifying abnormal consumption usage. The overall suggested framework is a complete integrated approach comprising a training and testing phase. Both phases are initiated from robust feature engineering to enhance the multipattern operation program classification. Additionally, a smoothing and decomposition process is applied to optimize the performance of the CNN-LSTM VAE. The efficacy of the method is evaluated on data from 26 different front-load washing machines, demonstrating its effectiveness in identifying anomaly points across various washing programs. Furthermore, compared to the same approach with a static threshold, the proposed method showed improvements of up to 11. 4% on the F1 score. Finally, simulated use case scenarios indicate a reduction of nearly 30% of energy consumption, due to error prevention. As a result, the suggested approach is a robust and applicable tool for energy and demand side management.

Evaluating the Effects of Reducing Voltage Margins for Energy-Efficient Operation of MPSoCs

Voltage margins, or guardbands, are imposed on DVFS systems to account for process, voltage, and temperature variability effects. While necessary to assure correctness, guardbands reduce energy efficiency, a crucial requirement for embedded systems. The literature shows that error detection techniques can be used to maintain the system’s reliability while reducing or eliminating the guardbands. This letter assesses the practically available margins of a commercial RISC-V MPSoC while violating its guardband limits. The primary motivation of this work is to support the development of an efficient system leveraging the redundancy of multicore architectures for an error detection and correction scheme capable of mitigating the errors caused by aggressive voltage margin reduction. For an equivalent performance, we achieved up to 27% energy reduction while violating the manufacturer’s defined guardband, leaving reasonable energy margins for further development.

Gradual error detection technique for non-destructive assessment of density and tensile strength in fused filament fabrication processes

Fused filament fabrication (FFF) is a widely used additive manufacturing process for producing functional components and prototypes. The FFF process involves depositing melted material layer-by-layer to build up 3D physical parts. The quality of the final product depends on several factors, including the component density and tensile strength, which are typically determined through destructive testing methods. X-ray microtomography (XCT) can be used to investigate the pore sizes and distribution. These approaches are time-consuming, costly, and wasteful, making it unsuitable for high-volume manufacturing. In this paper, a new method for non-destructive determination of component density and estimation of the tensile strength in FFF processes is proposed. This method involves the use of gradual error detection by sensors and convolutional neural networks. To validate this approach, a series of experiments has been conducted. Component density and tensile strength of the printed specimens with varying extrusion factor were measured using traditional destructive testing methods and XCT. The cumulative error detection method was used to predict the same properties without destroying the specimens. The predicted values were then compared with the measured values, and it was observed that the method accurately predicted the component density and tensile strength of the tested parts. This approach has several advantages over traditional destructive testing methods. The method is faster, cheaper, and more environmentally friendly since it does not require the destruction of the product. Moreover, it facilitates the testing of each individual part instead of assuming the same properties for components from one series. Additionally, it can provide real-time feedback on the quality of the product during the manufacturing process, allowing for adjustments to be made as needed. The advancement of this approach points toward a future trend in non-destructive testing methodologies, potentially revolutionizing quality assurance processes not only for consumer goods but various industries such as electronics or automotive industry. Moreover, its broader applications extend beyond FFF to encompass other additive manufacturing techniques such as selective laser sintering (SLS), or electron beam melting (EBM). A comparison between the old destructive testing methods and this innovative non-destructive approach underscores the possible fundamental change toward more efficient and sustainable manufacturing practices. This approach has the potential to significantly reduce the time and cost associated with traditional destructive testing methods while ensuring the quality of FFF-manufactured products.

Highly Efficient Self-checking Matrix Multiplication on Tiled AMX Accelerators

General Matrix Multiplication (GEMM) is a computationally expensive operation that is used in many applications such as machine learning. Hardware accelerators are increasingly popular for speeding up GEMM computation, with Tiled Matrix Multiplication (TMUL) in recent Intel processors being an example. Unfortunately, the TMUL hardware is susceptible to errors, necessitating online error detection. The Algorithm-based Error Detection (ABED) technique is a powerful technique to detect errors in matrix multiplications. In this article, we consider implementation of an ABED technique that integrates seamlessly with the TMUL hardware to minimize performance overhead. Unfortunately, rounding errors introduced by floating-point operations do not allow a straightforward implementation of ABED in TMUL. Previously an error bound was considered for addressing rounding errors in ABED. If the error detection threshold is set too low, it will a trigger false alarm, while a loose bound will allow errors to escape detection. In this article, we propose an adaptive error threshold that takes into account the TMUL input values to address the problem of false triggers and error escapes and provide a taxonomy of various error classes. This threshold is obtained from theoretical error analysis but is not easy to implement in hardware. Consequently, we relax the threshold such that it can be easily computed in hardware. While ABED ensures error-free computation, it does not guarantee full coverage of all hardware faults. To address this problem, we propose an algorithmic pattern generation technique to ensure full coverage for all hardware faults. To evaluate the benefits of our proposed solution, we conducted fault injection experiments and show that our approach does not produce any false alarms or detection escapes for observable errors. We conducted additional fault injection experiments on a Deep Neural Network (DNN) model and find that if a fault is not detected, it does not cause any misclassification.

Improving dependability with low power fault detection model for skinny-hash.

The increasing popularity and prevalence of Internet of Things (IoT) applications have led to the widespread use of IoT devices. These devices gather information from their environment and send it across a network. IoT devices are unreliable due to their susceptibility to defect that arise intentionally or spontaneously. IoT devices must be dependable and secure since they form an integral part of the network that connects millions of connected objects. IoT devices are secured by cryptographic algorithms, but their dependability is a major concern. Concurrent error detection (CED) techniques, sometimes referred to as fault detection techniques, are extensively employed to enhance the dependability of embedded devices. Two fault detection approaches are proposed to detect faults in cryptographic algorithms running on IoT devices. Recomputing with complemented operands (RECO) and Double modular redundancy with complemented operands (DMRC) is proposed. Generally, IoT applications deploy resource-constrained devices and cannot support high-level security techniques. Therefore, the mentioned fault detection technique is assimilated for the lightweight SKINNY block cipher. The resource-sharing concept is applied to the SKINNY block cipher to reduce area overhead caused by DMRC. The SKINNY-Hash function construct is described using Very Large-Scale Hardware Description Language (VHDL). Functional behaviour is tested using ModelSim SE-64. The proposed architecture is synthesised using the Genus synthesis tool by Cadence, and area-power reports are generated. The proposed work is compared with the other CED techniques in terms of area and power consumption, and the work proves to have less overhead.

Design and Implementation of Multi-operative Reversible Gate for Even/Odd Parity Generators in Quantum based Technologies

Quantum technology is graciously budding in nano-communication due to its properties and logical function, having the momentous prosperity of being reversible. It has gained an appeal to future-generation research owing to those sole aspects that may not be explored in the classical realm. A reliable nano-communication system utilizes varied error detection and correction techniques. Beyond low device density, authentic random number generation is a crucial issue in the cryptographic aspects of future communication architecture. To our knowledge, this is the innate study of an intriguing prospect: the design and implementation based on the lower level of power 'even/odd parity generator' using a single multi-operative reversible gate that has been achieved and functionally authenticated in the QCA nanotechnology, likewise in the IBMQ experience allied to quantum-based technologies. This breakthrough in nanotechnology and quantum-based technologies could have significant implications for blooming more efficient, secure communication systems in post-quantum cryptography.

Efficient Error Detection for Matrix Multiplication With Systolic Arrays on FPGAs

Matrix multiplication has always been a cornerstone in computer science. In fact, linear algebra tools permeate a wide variety of applications: from weather forecasting, to financial market prediction, radio signal processing, computer vision, and more. Since many of the aforementioned applications typically impose strict performance and/or fault tolerance constraints, the demand for fast and reliable matrix multiplication (MxM) is at an all-time high. Typically, increased reliability is achieved through redundancy. However, coarse-grain duplication incurs an often prohibitive overhead, higher than 100%. Thanks to the peculiar characteristics of the MxM algorithm, more efficient algorithm-based hardening solutions have been designed to detect (and even correct) some types of errors with lower overhead. We show that, despite being more efficient, current solutions are still sub-optimal in certain scenarios, particularly when considering persistent faults in Field-Programmable Gate-Arrays (FPGAs). Based on a thorough analysis of the fault model, we propose an error detection technique for MxM that decreases both algorithmic and architectural costs by over a polynomial degree, when compared to existing algorithm-based strategies. Furthermore, we report arithmetic overheads at the application level to be under 1% for three state-of-the-art Convolutional Neural Networks (CNNs).

Comparative Analysis of Post-editing Techniques for Chinese-to-English Translation Tasks: A Quasi-Experimental Study

This study aimed to examine the differences in translation time and quality between human translation (HT), machine translation post-editing (MTPE), and ChatGPT post-editing (ChatGPT PE). A quasi-experimental design was employed, involving 30 junior participants majoring in English from a Chinese university. A translation task consisting of 532 words from Chinese to English was assigned to the three groups and the translation speed and quality were assessed using the Multidimensional Quality Metrics (MQM) and Dynamic Quality Framework (DQF). The results demonstrated that the post-editing technique could produce translation quality comparable to human translation while achieving faster translation speed. It was observed that ChatGPT PE outputs exhibited the highest number of terminology errors but had the fewest accuracy errors, while mean differences in two of accuracy dimensions were observed among the three groups. The utilization of post-editing in language teaching would allow for the integration of machine translation strengths and human expertise, resulting in high-quality translations on par with human translations. To optimize post-editing outcomes, it is crucial to develop and teach error-detection techniques and avoid excessive reliance on AI technology.

Adaptive LDPC coded high data rate based IR-UWB combined with VMIMO system for vehicular communication links

The automotive industry is developing significantly with the evolution of vehicular networks, intelligent transportation systems, and autonomous cars. These technologies are made achievable by recent advances in software, hardware, and communication systems, along with various applications and standardization efforts. On the other side, many impairments have existed due to these evolving, limiting the process of vehicular networks. So, this paper proposes an implementation of adaptive LDPC-coded, high data rate-based Impulse Radio-Ultra Wide Band (IR-UWB) combined with Virtual Multiple Input Multiple Output (VMIMO) systems for Vehicle-to-Vehicle (V2V) and Vehicle-to-Infrastructure (V2I) wireless communications. Furthermore, they are merged with orthogonal pulse shaping using a modified Hermite pulse. Besides, the paper compares Zero-Forcing (ZF) and Minimum Mean Square Error (MMSE) detection techniques. To enhance and mitigate the existing impairments facing the vehicular networks. The proposed system’s performance is evaluated using both techniques, utilizing Bit Error Rate (BER), processing time, and resultant throughput analysis for both channel models. The simulation results include Non-Line of Sight (NLoS) and Line of Sight (LoS) scenarios for both channel models. Moreover, the simulation considers the effect of path loss and noise on the transmitted signal. In addition, the recent LDPC decoding algorithm termed “Modified Implementation Efficient Reliability Ratio Weighted Bit Flipping” (MIERRWBF) is evaluated through all latter channel models. At last, a novel adaptive LDPC decoder is proposed to further enhance the performance of all vehicular communication links under study. Consequently, the paper proposed an integrated adaptive LDPC-coded high data rate communication system to enhance vehicular communications using VMIMO mixed with modified Hermite orthogonal pulse shaping and deploying the MMSE recommended detection technique.

Sampling technique for noisy and borderline examples problem in imbalanced classification

Class imbalance Learning (CIL) is an important machine learning branch. Due to an imbalanced dataset, the efficiency of the classifiers is impacted. Various under/oversampling approaches are applied to the dataset to solve the class imbalance problem. The most successful among all the present solutions for data imbalance is the Synthetic Minority Oversampling Technique (SMOTE) which has a broad range of handling real-world applications. Noise and borderline examples are the two factors that degrade the performance of SMOTE and its variants. To address these issues, filtering-based methods have been developed. However, there are drawbacks associated with the filtering method. Firstly, error detection approaches in filtering methods are highly dependent on parameter settings. Secondly, samples identified during error detection are deleted or filtered from the sampling process which leads to abnormality of obtaining decision boundary and thus problem of again the class imbalance problem. To fix the problems associated with state-of-the-art filtering-based approaches, a novel oversampling filter-based method SMOTE-TLNN-DEPSO is proposed in this paper. In this hybrid variant SMOTE-TLNN-DEPSO, using SMOTE method the synthetic samples are generated to enhance the original class-imbalance data. Next, the two-layer natural neighbors’ technique is used for error detection which identifies the noisy and borderline examples. Lastly, instead of deleting the identified noisy and borderline examples, the hybrid variant of the differential evolution (DE) algorithm based on particle swarm optimization (PSO) called DEPSO is applied to optimize and modify iteratively the position (attributes). SMOTE-TLNN-DEPSO technique shows the advantage over other state of art SMOTE-based filtering-based approaches by solving the noise problem; the error detection technique using the nearest neighbor is parameter-free; Utilizing DEPSO approach the identified noisy samples by error detection technique are optimized instead of removing them. This helps in maintaining the imbalance ratio and improving the boundary; this approach is very appropriate for data sets having more noisy attributes especially class attributes the efficiency and usefulness of the proposed SMOTE-TLNN-DEPSO are demonstrated by exhaustive comparison experiments on artificial and real data sets.

DETECTING SUPPLIER PAYMENT ERRORS AND FRAUD USING A DATA WAREHOUSE AUDIT APPROACH

ABSTRACT This study provides management, accountants, and auditors with immediately applicable knowledge on supplier payment error discovery using a data warehouse. Despite the universality of supplier payment processing across government and non-government sectors, the associated error risks have received little attention in the academic literature and only limited attention in the practitioner literature. This paper seeks to articulate the data mining methods needed to perform such audits. A case study approach was used to analyze 15 client auditees in five countries using a variety of accounts payable systems. Action research methodology brought rigor to the development of incremental knowledge of error hypotheses and detection techniques. In this way, the prior knowledge gained from each case enriched the subsequent iterations. Even among clients whose management presumed human and system controls were robust, findings showed an average 0.19 percent error rate in payments to suppliers. These were mostly recoverable as cash refunds or credit notes. The audit cost-to-benefit ratio averaged 1:33, suggesting clients received financial returns 33 times higher than the cost of the audit, on average. Concurrently, internal controls were also hardened in accounts payable, tax compliance, and fraud prevention to secure additional future cost savings. Besides material cash recoveries and the occasional discovery of fraud, incremental lessons were also learned in data warehouse construction, data cleansing, privacy assurance, and tax compliance.

A Unified Clock-Gated Error Correction Scheme with Three-Phase Latch-Based Pipeline for Energy-Efficient Wide Supply Voltage Range Router

Network-on-chip (NoC) has played a vital role in enabling high-speed and energy-efficient data communication among different cores in a multi-or many-core System-on-Chip (SoC). To mitigate the pessimistic timing margin reversed for severe process, voltage, and temperature (PVT) variations, we presented a wide supply voltage range router with a novel error detection and correction (EDAC) technique adopted in its latch-based pipeline for high energy efficiency. Especially, a unified clock-gated error correction scheme is presented to address dynamic timing errors under PVT variations and functional pipeline stalls when occurring allocation failure (packet fails to obtain an output port) or flow control (the next router stalls the current packet transmitting) in one cycle. Moreover, a latch-based pipeline structure with three non-overlapped clocks is adopted to further reduce the short-path padding overhead, which is significantly increased in the ultra-low voltage (ULV) regime. Consequently, we prototyped a 2 × 2 2D mesh NoC test chip with 28-nm CMOS technology. Compared with the margined baseline with a 10% VDD drop, measurement results show that the proposed router enables 1.4×, 32.4%, and 7.5% improvements in frequency, energy, and area, respectively. Furthermore, the proposed techniques can reduce packet loss by 200× and increase throughput by 19.9% for the NoC at 0.4 V, 25∘C.

An Efficient Viterbi Algorithm for Communication System

The method of decoding by Viterbi is used in areas like convolutional codes in digital TV, wireless local area networks, satellite communication, mobile relay. Also, the method is used in the development of Automatic Speech Recognition (ASR) and storage systems that work automatically. For Viterbi decoder-based architectures with low latency and complexity, which proposes error detection techniques that are effective. This paper explores the Viterbi algorithm which has two types of approaches for two types of subparts. Important aspects of any communication system are area/power consumption and throughput /efficiency. Minimization of these aspects is the need for an efficient system. This paper explores unwanted logical block reduction by modifying the present logical block. This paper explores signature-based approaches which result in acceptable efficiency. Also, another approach is used to achieve error detection in permanent and transient faults. This error detection is achieved by recomputing with encoded operands. Encoding means the use of shifting operation or the use of rotation operation. This approach makes the system slightly reliable and efficient.

Implementation of Control Flow Checking—A New Perspective Adopting Model-Based Software Design

A common requirement of embedded software in charge of safety tasks is to guarantee the identification of random hardware failures (RHFs) that can affect digital components. RHFs are unavoidable. For this reason, the functional safety standard devoted to automotive applications requires embedded software designs able to detect and eventually mitigate them. For this purpose, various software-based error detection techniques have been proposed over the years, focusing mainly on detecting control flow errors. Many control flow checking (CFC) algorithms have been proposed to accomplish this task. However, applying these approaches can be difficult because their respective literature gives little guidance on their practical implementation in high-level programming languages, and they have to be implemented in low-level code, e.g., assembly. Moreover, the current trend in the automotive industry is to adopt the so-called model-based software design approach, where an executable algorithm model is automatically translated into C or C++ source code. This paper presents two novelties: firstly, the compliance of the experimental data on the capabilities of control flow checking (CFC) algorithms with the ISO 26262 automotive functional safety standard; secondly, by implementing the CFC algorithm in the application behavioral model, the off-the-shelves code generator seamlessly produces the hardened source code of the application. The assessment was performed using a novel fault injection environment targeting a RISC-V (RV32I) microcontroller.