Error Correction Coverage Research Articles

Clustered Error Resilient SRAM-Based Reconfigurable Computing Platform

In the present age of high-density integrated circuits, radiation-induced adjacent multibit upsets (AMBUs) or clustered errors are very prominent in the configuration memory of static-random-access-memory-based field-programmable gate array (FPGA) devices. Radiated particles with high energy and low momentum may damage a group of adjacent logic cells and switches in reconfigurable devices, which can lead to clustered errors. Commonly used error mitigation techniques in the FPGA either have large overheads, complex decoding circuitry, or are not very efficient to correct AMBUs. Hence, efficient multibit error-correcting codes with low redundancy are of utmost need to mitigate the effect of AMBUs. Configuration data of the FPGAs are composed of a number of configuration frames (CFs), and there is a high probability that multiple physically adjacent CFs may be affected by clustered error. Hence, interleaving among CFs is quite advantageous for mitigation of clustered errors in the configuration memory of the FPGA. In this article, we have proposed a simple and efficient error mitigation model combining Hamming product code (HPC) with frame interleaving and selective bit placement, termed as “HPCFISBP” to correct AMBUs in the configuration memory of the FPGA without any modification in its basic architecture. The HPCFISBP provides better bit error rate performance nearly by 20 and 10 dB compared to Hamming code and HPC, respectively. The enhanced performance of the HPCFISBP has also been established through comparison with the state-of-the-art techniques in terms of error correction coverage, error correction time, redundancy, and residual error.

Latency optimized clustered error mitigation for multi-level flash memory using product code

Soft errors due to radiation-induced multi-bit upsets (MBUs) are very prominent in the present flash memories built with ultra large scale VLSI technology. Use of multi-level cells in flash memories increase the chance of adjacent MBUs or clustered error. Single bit error detection and correction (EDAC) codes are not enough to mitigate the effect of clustered error due to their small error correction capability. On the other hand, commonly used multi-bit EDAC codes have large overhead, complex decoding circuitry, high error correction latency and are unable to correct large number adjacent erroneous bits. In this paper, we have proposed a product code coined as linear shortened block code based product code (LSBCPC) for mitigation of clustered error in the flash memory devices. LSBCPC utilizes latency optimized scalable shortened block code as the component code and can correct higher number of adjacent erroneous bits in memory devices compared to the other state of the art solutions. The proposed LSBCPC promises better error correction coverage with 28%, 14%, and 13% reduction in terms of redundant bits, 13%, 11%, and 10% reduction in terms of area and 24%, 26%,and 22% reduction in terms of latency in 16 × 16, 32 × 32 and 64 × 64 memory devices respectively compared to the highly cited research work. The performance of the proposed method is validated in terms of redundant bits, error correction coverage, mean error to failure, area consumption, power utilization and decoding latency.

Silent Data Corruption Resilient Two-sided Matrix Factorizations

This paper presents an algorithm based fault tolerance method to harden three two-sided matrix factorizations against soft errors: reduction to Hessenberg form, tridiagonal form, and bidiagonal form. These two sided factorizations are usually the prerequisites to computing eigenvalues/eigenvectors and singular value decomposition. Algorithm based fault tolerance has been shown to work on three main one-sided matrix factorizations: LU, Cholesky, and QR, but extending it to cover two sided factorizations is non-trivial because there are no obvious \textit{offline, problem} specific maintenance of checksums. We thus develop an \textit{online, algorithm} specific checksum scheme and show how to systematically adapt the two sided factorization algorithms used in LAPACK and ScaLAPACK packages to introduce the algorithm based fault tolerance. The resulting ABFT scheme can detect and correct arithmetic errors \textit{continuously} during the factorizations that allow timely error handling. Detailed analysis and experiments are conducted to show the cost and the gain in resilience. We demonstrate that our scheme covers a significant portion of the operations of the factorizations. Our checksum scheme achieves high error detection coverage and error correction coverage compared to the state of the art, with low overhead and high scalability.

Live-Out Register Fencing

This article introduces Live-Out Register Fencing (LoRF), a soft error correction mechanism that uses the novel Spill Register File as a container of checkpointing data. LoRF’s Spill Register File holds the values shared among basic blocks in the program, and, coupled with a new compilation strategy, LoRF allows for error correction in the same basic block where the error was detected. In LoRF, error correction is triggered by a hardware interrupt that restores the registers of a basic block from the Spill Register File. After these registers are restored, the basic block where the error was detected can just be re-executed, thus reducing the costs of error recovery. LoRF’s error correction policy eliminates the need for expensive architectural support for checkpointing and rollback, reducing the performance overhead of online soft error correction. LoRF relies on both a modified processor architecture and a corresponding compiler. The architecture was implemented in synthesizable VHDL, whereas the compiler was developed as an extension of the LLVM framework. Fault injection experiments support an error correction coverage of 99.35% and a mean performance overhead of 1.33 for the entire life cycle of an error from its occurrence to its elimination from the system.

Refractive Error and Presbyopia in Timor-Leste: The Impact of 5 Years of a National Spectacle Program

To characterize refractive error, presbyopia, and spectacle correction among adults aged ≥40 years in Timor-Leste in 2010 and examine the impact of the National Spectacle Program by comparing results to those obtained 5 years earlier. A population-based, cross-sectional survey sampled 50 clusters of 45 people each. Participants with uncorrected and undercorrected refractive error (presenting visual acuity <6/18, but ≥6/18 in the better eye with pinhole), uncorrected and undercorrected presbyopia (<N8 binocular), corrected refractive error (≥6/18 in the better eye with presenting spectacles), and corrected presbyopia (binocular ≥N8 with presenting spectacles) were identified. Willingness to wear and to pay for spectacles was elicited. Data were adjusted for sex, age, and urban/rural domicile, to compare results from 2005 and 2010. A participation rate of 89.5% (n = 2014) was achieved. The 2010 sex-age-domicile-adjusted parameters were as follows: 3.7% (95% confidence interval [CI], 2.8%-4.5%) met refractive error need; 9.6% (95% CI, 8.3%-10.9%) unmet refractive error need; 27.6% (95% CI, 22.2%-32.9%) refractive error correction coverage; 8.6% (95% CI, 7.4%-9.8%) met presbyopia need; 41.8% (95% CI, 39.7%-44.0%) unmet presbyopia need; and, 17.0% (95% CI, 14.7%-19.3%) presbyopia correction coverage. Refractive error correction coverage was significantly higher in 2010 than in 2005 (8.0%; 95% CI, 4.5%-11.6%), but presbyopia correction coverage was unchanged. Almost all the 2010 sample (99.5%) were willing to wear spectacles if needed. Sex-age-domicile-adjusted willingness to pay at least US$1.00 for spectacles was 56.9% (95% CI, 54.7%-59.1%) in 2010, significantly greater than in 2005 (47.2%; 95% CI, 44.5%-49.9%). The National Spectacle Program has not produced uniform improvement across all service indicators. Evidence-based enhancements may now be initiated.

Error-Correcting Unordered Codes and Hardware Support for Robust Asynchronous Global Communication

This paper introduces a new family of error-correction unordered (ECU) codes for global communication, called Zero-Sum. They combine the timing-robustness of delay-insensitive (i.e., unordered) codes with the fault-tolerance of error-correcting codes (providing 1-bit error correction or 2-bit detection). Two key features of the codes are that they are systematic, allowing direct extraction of data, and weighted, where the check field is computed as the sum of data index weights. A wide variety of weight assignments is shown to be feasible. Two practical enhancements are also proposed. The Zero-Sum <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> code extends error detection to 3-bit errors, or alternatively handles 2-bit detection and 1-bit correction. The Zero-Sum* code supports heuristic 2-bit correction, while still guaranteeing 2-bit detection, under different strategies of weight assignment. Detailed hardware implementations of the supporting components (encoder, completion detection, error corrector) are given, as well as an outline of the system microarchitecture. In comparison to the best alternative systematic ECU code, the basic Zero-Sum code provided better or comparable coding efficiency, with a 5.74%-18.18% reduction in average number of wire transitions for most field sizes. Several Zero-Sum* codes were also evaluated for their 2-bit error correction coverage; initial results are promising, where the best strategy corrected 52.92%-71.16% of all 2-bit errors for most field sizes, with only a moderate decrease in coding efficiency and increase in wire transitions. Technology-mapped pre-layout implementations of the supporting Zero-Sum code hardware were synthesized with the UC Berkeley ABC tool using a 90 nm industrial standard cell library. Results indicate that they have moderate area and delay overheads. In comparison, supporting hardware for the best nonsystematic ECU codes have 3.82-10.44× greater area for larger field sizes.

HVD: horizontal-vertical-diagonal error detecting and correcting code to protect against with soft errors

This paper presents a high level error detection and correction method called HVD code to tolerate multiple bit upsets (MBUs) occurred in memory cells. The proposed method uses parity codes in four directions in a data part to assure the reliability of memories. The proposed method is very powerful in error detection while its error correction coverage is also acceptable considering its low computing latency. HVD code is useful for applications whose high error detection coverage is very important such as memory systems. Of course, this code can be used in combination with other protection codes which have high correction coverage and low detection coverage. The proposed method is evaluated using more than one billion multiple fault injection experiments. Multiple bit flips were randomly injected in different segments of a memory system and the fault detection and correction coverages are calculated. Results show that 100% of the injected faults can be detected. We proved that, this method can correct up to three bit upsets. Some hardware implementation issues are investigated to show tradeoffs between different implementation parameters of HVD method.

Refractive Error and Presbyopia Among Adults in Fiji

Purpose: To characterize refractive error, presbyopia and their correction among adults aged ≥ 40 years in Fiji, and contribute to a regional overview of these conditions.Methods: A population-based cross-sectional survey using multistage cluster random sampling. Presenting distance and near vision were measured and dilated slitlamp examination performed.Results: The survey achieved 73.0% participation (n = 1381). Presenting binocular distance vision ≥ 6/18 was achieved by 1223 participants. Another 79 had vision impaired by refractive error. Three of these were blind. At threshold 6/18, 204 participants had refractive error. Among these, 125 had spectacle-corrected presenting vision ≥ 6/18 (“met refractive error need”); 79 presented wearing no (n = 74) or under-correcting (n = 5) distance spectacles (“unmet refractive error need”). Presenting binocular near vision ≥ N8 was achieved by 833 participants. At threshold N8, 811 participants had presbyopia. Among these, 336 attained N8 with presenting near spectacles (“met presbyopia need”); 475 presented with no (n = 402) or under-correcting (n = 73) near spectacles (“unmet presbyopia need”). Rural residence was predictive of unmet refractive error (p = 0.040) and presbyopia (p = 0.016) need. Gender and household income source were not. Ethnicity-gender-age-domicile-adjusted to the Fiji population aged ≥ 40 years, “met refractive error need” was 10.3% (95% confidence interval [CI] 8.7–11.9%), “unmet refractive error need” was 4.8% (95%CI 3.6–5.9%), “refractive error correction coverage” was 68.3% (95%CI 54.4–82.2%),”met presbyopia need” was 24.6% (95%CI 22.4–26.9%), “unmet presbyopia need” was 33.8% (95%CI 31.3–36.3%), and “presbyopia correction coverage” was 42.2% (95%CI 37.6–46.8%).Conclusion: Fiji refraction and dispensing services should encourage uptake by rural dwellers and promote presbyopia correction. Lack of comparable data from neighbouring countries prevents a regional overview.