BCH Error Correction Research Articles

NLP-BCH-Ens: NLP-based intelligent computational model for discrimination of malaria parasite

Plasmodium falciparum causes malaria, which is an infectious and fatal disease. In early days, malaria-infected cells were diagnosed using a microscope. owing to a huge number of instances for analysis and intricacy of time, it may lead to false detection. Automated parasite detection technologies are in high demand due to increased time consumption and erroneous detection. To create effective cures and treatments, it is critical to use an accurate approach for predicting malaria parasite. Here, numerous protein sequences formulation techniques namely: discrete methods, Biochemical, physiochemical and Natural language processing techniques are applied for transformation of protein sequences in to numerical descriptors. Four classification algorithms are utilized and the anticipated results of these classifiers were then fused to establish ensemble classification model via simple majority and genetic algorithm. In addition, BCH error correction code is incorporated with support vector machine using all the feature spaces. The simulated results demonstrate the remarkable achievement of proposed compared to previous models. Thus, our proposed model may be an effective tool for discriminating the secretory and non-secretory proteins of malaria parasite.

High performance optical image hiding based on computational ghost imaging with BCH error correction coding technique

The conventional image hiding scheme based on computational ghost imaging (CGI) has low-quality reconstructed watermark and unsatisfied security. In this paper, a high performance optical image hiding scheme is proposed to cope with these issues. The watermark is first read as a binary number sequence and processed by exclusive-OR operation with a random number sequence that generated by chaotic system. Thereafter, the result is coded with Bose-Chaudhuri-Hocquenghem error correction code and encrypted by the CGI system. Finally, the obtained cyphertext is quantified into two levels and hidden in the host image. Differing from other watermarking schemes, binary images, grayscale images and color images can be used as watermarks to be reconstructed losslessly, and a series of simulation results illustrate the feasibility and effectiveness of the proposed scheme.

A BCH error correction scheme applied to FPGA with embedded memory

A BCH error correction scheme applied to FPGA with embedded memory

A 4-fJ/b Delay-Hardened Physically Unclonable Function Circuit With Selective Bit Destabilization in 14-nm Trigate CMOS

This paper describes a full-entropy 128-b key generation platform based on a 1024-b hybrid physically unclonable function (PUF) array, fabricated in 14-nm trigate high-k/metal-gate CMOS. Delay-hardened hybrid PUF cells use differential clock delay insertion to favor circuit evaluation in the desired direction while leveraging burn-in-induced aging for selective bit destabilization enabling quick identification and masking of unstable cells, and subsequent temporal-majority-voting with soft dark-bit masking to reduce PUF bit error by 3.9 times to 1.45% resulting in ~5 ppb failure probability. A stable full-entropy 128-b key is finally generated from the 1024 raw PUF bits using BCH error correction and AES-CBC-based entropy extraction. An all-digital design with compact PUF cell layout occupying $1.84~\mu \text{m}^{2}$ achieves: 1) 4-fJ/b energy-efficiency with 3-μW leakage at 0.65 V, 70 °C; 2) peak operating frequency of 1 GHz resulting in 1.2-μs key generation latency; 3) robust operation with stable key generation across 0.55–0.75 V, and 25 °C–110 °C; 4) 14 times separation between intra/inter-PUF hamming distances with 0.99993 entropy ensuring cryptographic quality randomness and uniqueness; 5) 48% higher PUF stability with long-term aging by leveraging transistor degradation to reinforce favorable cell bias; and 6) resiliency to power cycling attacks with common centroid clock routing measured from 49.5% hamming distance between array’s evaluation and wake-up states.

Double expanding robust image watermarking based on Spread Spectrum technique and BCH coding

This paper presents a new algorithm for blind image watermarking which has a high robustness against common image processing attacks such as noise addition (Gaussian noise, Salt & Pepper noise, Speckle noise and etc.), JPEG and JPEG2000 compressions, Histogram Equalization, Average and Gaussian filters, Scaling and Cropping. According to this fact that a watermark with about 70 bits is enough for copyright protection, consequently in this paper a small watermark (64 bits) have been double expanded into multi larger meaningful bits with applying BCH error correction code and Spread Spectrum technique in order to reduce errors in extraction phase. Approximation subband of two levels DWT transform is divided into non-overlapping blocks and high frequency coefficients of DCT transform of each block is used for embedding the watermark. Embedding technique, which is used in this paper, is Spread Spectrum. Correlation between some coefficients of each embedded block and two predefined groups of random bits is used for watermark extraction, so this method is blind and does not need to the original image or additional information in extraction phase. Another idea, which is used in this paper, is calculating different gain factors for each block of approximation subband according to the texture of each block. Consequently this method allocates smaller gain factors to smooth blocks and larger gain factors to texture and rough blocks. So, manipulating in image will be more robust and imperceptible.

The weight distributions of two classes of binary cyclic codes

For two positive integers m and k, let Ce be a class of cyclic code of length 2m−1 over F2 with three nonzeros γ−1, γ−(2k+1) and γ−(2ek+1) for e=2 or 3, where γ is a primitive element of F2m. When mgcd⁡(m,k) is odd, Kasami in 1971 determined the weight distributions of cyclic codes C2 and C3, which is the same as that of the dual of the triple error-correcting BCH code. This paper obtains the weight distributions of C2 and C3 for the case of mgcd⁡(m,k) being even.

Time-space test response compaction and diagnosis based on BCH codes

A test response compaction and diagnosis technique based on BCH error correction code is presented. Traditional time-domain BCH compaction is not very useful in practice because the area overhead is too large. On the other hand, space-domain BCH compaction does not have a sufficient compression ratio to support a multiple error diagnosis. The proposed time-space compaction technique shares the polynomials among scan chains to reduce the area overhead A Boolean satisfiability optimiser is employed to diagnose the minimum number of errors. In addition, an analytical model is proposed to estimate the aliasing probability, which helps to determine key parameters of the proposed compactor. To diagnose ten errors in a design of 500 k flip-flops, the compression ratio is more than 2600 and the area overhead is <5% of flip-flops.

The two covering radius of the two error correcting BCH code

The $m$-covering radii of codes are natural generalizations of the covering radii of codes. In this paper we analyze the 2-covering radii of double error correcting BCH code. In particular, we show that the 2-covering radius of the double error correcting BCH code is $(n+1)/2$ for sufficiently large $n$.

Performance of turbo detection in a variable rate wireless system using linear block codes and interleaving

Linear block coding with an iterative detecting-decoding process, namely, turbo detection, is examined for data transmission within the framework of the HIPERLAN Type 1 standard. By means of simulations, performance is evaluated in Gaussian and frequency selective Rayleigh fading channels and the turbo detection method is shown to offer superior performance when compared to soft-decision algorithms; although its high potential is restricted by the predefined standard, which makes use of a single error-correcting BCH(31, 26) code and a block interleaver of depth 16. In order to improve the performance, we devise an alternative variable coding system, having the same physical layer as HIPERLAN, but with the additional channel coding options of a three error-correcting BCH(31, 16) code, or of a seven error-correcting BCH(31, 6) code. Besides having a modular structure, which adapts easily to different information rates, this approach allows the system to work at lower signal-to-noise ratios (SNRs), ensuring user connectivity under very hostile channel conditions.

Uniformly Packed Codes and More Distance Regular Graphs from Crooked Functions

Let i>V and i>W be i>n-dimensional vector spaces over GF(2). A function i>Q : i>V → i>W is called i>crooked (a notion introduced by Bending and Fon-Der-Flaass) if it satisfies the following three properties: We show that crooked functions can be used to construct distance regular graphs with parameters of a Kasami distance regular graph, symmetric 5-class association schemes similar to those recently constructed by de Caen and van Dam from Kasami graphs, and uniformly packed codes with the same parameters as the double error-correcting BCH codes and Preparata codes.

Association Schemes Related to Kasami Codes and KerdockSets

Two new infinite series of imprimitive 5-class association schemes are constructed. The first series of schemes arises from forming, in a special manner, two edge-disjoint copies of the coset graph of a binary Kasami code (double error-correcting BCH code). The second series of schemes is formally dual to the first. The construction applies vector space duality to obtain a fission scheme of a subscheme of the Cameron-Seidel 3-class scheme of linked symmetric designs derived from Kerdock sets and quadratic forms over GF(2).

Sound data interpolating circuit

A sound data interpolating circuit includes data converting means for converting inputted serial sound data to parallel sound data to thereby output the same; pulse generating means for generating interpolating pulses, channel gating pulses and loading pulses according to a double error signal outputted from a BCH error correction circuit and a clock signals generated from clock generating means; data extracting means for maintaining prior data during a double error occurrence and outputting data interpolated using the prior and following non-erroneous data in accordance with the interpolating pulses inputted from the pulses and clock signals generated from the clock generating means; data selecting means for outputting data outputted from the data extracting means according to a sound channel; and average value calculating means for striking an average from the data outputted from the data converting means and data selecting means to thereafter output the average value. The sound data interpolating circuit improves tone quality by performing an average value interpolation using the prior and following non-erroneous samples per respective sound channels in the case of an individual double error, and by performing pre-interpolation in the case of continuous double error occurrence, in a state where correction is impossible by way of BCH error correction during occurrence of sample errors in aural PCM data.

A high-performance full-motion video compression chip set

A seven-chip set which performs the functions associated with video and image compression algorithms, and CCITT H.261 in particular, has been designed, fabricated, and is fully functional. The major functions performed by the devices include motion estimation, DCT and IDCT, forward and inverse quantization, Huffman coding and decoding, BCH error correction, and loop filtering. The chips that perform the predictive and transform coding section of the algorithm operate with pixel rates up to 40 MHz. Array-based technologies of 1.5 and 1.0 mu m CMOS were used extensively to achieve a 28 man-month design time. Each die is less than 10 mm on a side. >

Decoder malfunction in BCH decoders

A t-error-correcting bounded-distance decoder either produces the codeword nearest the received vector (if there is a codeword at distance no more than t) or indicates that no such codeword exists. However, BCH decoders based on the Peterson-Gorenstein-Zierler algorithm or the Euclidean algorithm can malfunction and produce output vectors that are not codewords at all. For any integer i no greater than t/2, if the received vector is at distance at most t-2i from a codeword belonging to a (t-i)-error-correcting BCH supercode, then the BCH decoder output is that codeword from the supercode.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Binary-decision approach to fast Chien search for software decoding of BCH codes

A fast decoding algorithm for binary double error-correcting BCH codes is presented. A binary-decision approach to the Chien search is introduced to reduce the search time by a factor of two, and hence to increase the decoding speed. This algorithm is suitable for microprocessorbased implementation. An illustrative design of a (128, 112, 2) binary BCH decoder using the 16-bit 8086 microprocessor is presented. Complexity, memory space and decoding time are discussed.