Erroneous Output Research Articles

Exploiting Polydopamine Nanospheres to DNA Computing: A Simple, Enzyme-Free and G-Quadruplex-Free DNA Parity Generator/Checker for Error Detection during Data Transmission.

Molecular logic devices with various functions play an indispensable role in molecular data transmission/processing. However, during any kinds of data transmission, a constant and unavoidable circumstance is the appearance of bit errors, which have serious effects on the regular logic computation. Fortunately, these errors can be detected via plugging a parity generator (pG) at the transmitting terminal and a parity checker (pC) at the receiving terminal. Herein, taking advantage of the efficient adsorption/quenching ability of polydopamine nanospheres toward fluorophore-labeled single-stranded DNA, we explored this biocompatible nanomaterial to DNA logic computation and constructed the first simple, enzyme-free, and G-quadruplex-free DNA pG/pC for error detection through data transmission. Besides, graphene oxide (GO) was innovatively introduced as the "corrective element" to perform the output-correction function of pC. All the erroneous outputs were corrected to normal conditions completely, ensuring the regular operation of later logic computing. The total operation of this non-G4 pG/pC system (error checking/output-correction) could be completed within 1 h (about 1/3 of previous G4 platform) in a simpler and more efficient way. Notably, the odd pG/pC with analogous functions was also achieved through negative logic conversion to the fabricated even one. Furthermore, the same system could also perform three-input concatenated logic computation (XOR-INHIBIT), enriching the complexity of PDs-based logic computation.

Error Detector Placement for Soft Computing Applications

The scaling of Silicon devices has exacerbated the unreliability of modern computer systems, and power constraints have necessitated the involvement of software in hardware error detection. At the same time, emerging workloads in the form of soft computing applications (e.g., multimedia applications) can tolerate most hardware errors as long as the erroneous outputs do not deviate significantly from error-free outcomes. We term outcomes that deviate significantly from the error-free outcomes as Egregious Data Corruptions (EDCs). In this study, we propose a technique to place detectors for selectively detecting EDC-causing errors in an application. We performed an initial study to formulate heuristics that identify EDC-causing data. Based on these heuristics, we developed an algorithm that identifies program locations for placing high coverage detectors for EDCs using static analysis. Our technique achieves an average EDC coverage of 82%, under performance overheads of 10%, while detecting 10% of the Non-EDC and benign faults. We also evaluate the error resilience of these applications under the 14 compiler optimizations.

Detecting Silent Data Corruptions in Aerospace-Based Computing Using Program Invariants

Soft error caused by single event upset has been a severe challenge to aerospace-based computing. Silent data corruption (SDC) is one of the results incurred by soft error. SDC occurs when a program generates erroneous output with no indications. SDC is the most insidious type of results and very difficult to detect. To address this problem, we design and implement an invariant-based system called Radish. Invariants describe certain properties of a program; for example, the value of a variable equals a constant. Radish first extracts invariants at key program points and converts invariants into assertions. It then hardens the program by inserting the assertions into the source code. When a soft error occurs, assertions will be found to be false at run time and warn the users of soft error. To increase the coverage of SDC, we further propose an extension of Radish, named Radish_D, which applies software-based instruction duplication mechanism to protect the uncovered code sections. Experiments using architectural fault injections show that Radish achieves high SDC coverage with very low overhead. Furthermore, Radish_D provides higher SDC coverage than that of either Radish or pure instruction duplication.

Digital Compensation Method for the Path Delay Mismatches in GRO-TDC

The digital compensation method for path delay mismatches in the time-to-digital converter (TDC) based on gated-ring oscillator (GRO) is proposed and demonstrated. The output of the GRO is digitized by the combination of a counter and a phase-to-digital converter (PDC) producing an integer and a fractional digital value, respectively. Due to the delay mismatches between two paths, the integer and fractional digital values are not synchronized thereby causing calculation errors. In order to reduce the errors, a correction bit (CB) is generated and then the erroneous output is fixed by the additional but simple digital circuits. Measurement results show that calculation errors due to the delay mismatches are corrected by the proposed compensation method and it reduces the quantization noise power by 10[Formula: see text]dB at high frequency offset.

Optimum steepest descent higher level learning radial basis function network

Dynamically changing real world applications, demands for rapid and accurate machine learning algorithm. In neural network based machine learning algorithms, radial basis function (RBF) network is a simple supervised learning feed forward network. With its simplicity, this network is highly suitable to model and control the nonlinear systems. Existing RBF networks in literature are applied to static applications and also faces challenges such as increased model size, neuron removal, improper center selection etc leading to erroneous output. To overcome the challenges and handle complex real world problems, this paper proposes a new optimum steepest descent based higher level learning radial basis function network (OSDHL-RBFN). The proposed OSDHL-RBFN implements major components inspired from the human brain for efficient learning, adaptive structure and accurate classification. Higher level learning and thinking components of the proposed network are sample deletion, neuron addition, neuron migration, sample navigation and neuroplasticity. These components helps the classifier to think before learning the samples and regulates the learning strategy. The knowledge gained from the trained samples are used by the network to identify the incomplete sample, optimal center and bond strength of hidden & output neurons. Adaptive network structure is employed to minimize classification error. The proposed work also uses optimum steepest descent method for weight parameter update to minimize the sum square error. OSDHL-RBFN is tested and evaluated in both static and dynamic environments on nine benchmark classification (binary and multiclass) problems for balanced, unbalanced, small, large, low dimensional and high dimensional datasets. The overall and class wise efficiency of OSDHL-RBFN is improved when compared to other RBFN’s in the literature. The performance results clearly show that the proposed OSDHL-RBFN reduces the architecture complexity and computation time compared to other RBFN’s. Overall, the proposed OSDHL-RBFN is efficient and suitable for dynamic real world applications in terms of detection time and accuracy. As a case study, OSDHL-RBFN is implemented in real time remote health monitoring application for classifying the various abnormality levels in vital parameters.

Design and Implementation of Booth Multiplier using Approximate Adders

Low power is an imperative requirement for portable multimedia devices employing various signal processing algorithms and architectures. In most multimedia applications, human beings can gather useful information from slightly erroneous outputs. Therefore, we do not need to produce exactly correct numerical outputs. Previous research in this context exploits error resiliency primarily through voltage overscaling, utilizing algorithmic and architectural techniques to mitigate the resulting errors. In this paper, we propose logic complexity reduction at the transistor level as an alternative approach to take advantage of the relaxation of numerical accuracy. We demonstrate this concept by proposing various imprecise or approximate full adder cells with reduced complexity at the transistor level, and utilize them to design approximate multi-bit adders. In addition to the inherent reduction in switched capacitance, our techniques result in significantly shorter critical paths, enabling voltage scaling. Keyword: Approximate computing, low power, mirror adder. Booths multiplier, Wallace tree multiplier I. INTRODUCTION Digital signal processing (DSP) blocks form the backbone of various multimedia applications used in portable devices. Most of these DSP blocks implement image and video processing algorithms, where the ultimate output is either an image or a video for human consumption. Human beings have limited perceptual abilities when interpreting an image or a video. This allows the outputs of these algorithms to be numerically approximate rather than accurate. This relaxation on numerical exactness provides some freedom to carry out imprecise or approximate computation. We can use this freedom to come up with low-power designs at different levels of design abstraction, namely, logic, architecture, and algorithm. The paradigm of approximate computing is specific to select hardware implementations of DSP blocks. It is shown in (1) that an embedded reduced instruction set computing processor consumes 70% of the energy in supplying data and instructions, and 6% of the energy while performing arithmetic only. Therefore, using approximate arithmetic in such a scenario will not provide much energy benefit when considering the complete processor. Programmable processors are designed for general-purpose applications with no application-specific specialization. Therefore, there may not be many applications that will be able to tolerate errors due to approximate computing. This also makes general-purpose processors not suited for using approximate building blocks. This issue has already been discussed in (13). Therefore, in this paper, we consider application-specific integrated circuit implementations of error-resilient applications like image and video compression.

Bipolar latch with compensated keep‐alive current

A permanent current in addition to the main clocked current is sometimes used to increase the maximum clock rate of a bipolar latch. Although it speeds up the activation of a clocked differential stage, it deteriorates the latch function by the additional current in the inactive phase of each differential stage. Thus, a keep-alive current must be kept small with respect to the main clocked current. In this Letter, a compensation technique is shown avoiding the erroneous output of a keep-alive current. It still speeds up the activation of the main transistor pair, but results in a constant symmetric offset without affecting the differential value of the output voltage. In simulations of flip-flops and clocked comparators, this compensated keep-alive current has a much larger effect on the maximum clock rate than the uncompensated keep-alive current used so far.

효율적인 센서 노드 고장 진단 알고리즘

The possible erroneous output data of the sensor nodes can cause the performance limit or the degradation of the reliability in the whole wireless sensor networks(WSN). In this paper, we propose a new sensor node scheme with multiple sensors and a new fault diagnostic algorithm. The algorithm can increase the reliability of the whole WSNs by utilizing measurements of the multiple sensors on the node and by determining the validity of the date by comparing the value of each sensor. It can increase the cost and complexity of the node, but is suitable for the area where the high reliability is critical.

Minimizing bugs in cognitive neuroscience programming.

Rigorous data analysis is a cornerstone of empirical scientific research. In recent years, much attention in the field of cognitive neuroscience has been paid to the issue of correct statistical procedures (e.g., Kriegeskorte et al., 2009; Nieuwenhuis et al., 2011; Kilner, 2013). However, an additional essential aspect of data analysis, which has attracted relatively little attention, is the errors (bugs) in custom data analysis programming code. Whereas, in its broad definition a bug can be any type of an error, here I refer to it as a problem in the code that does not lead to a failure (error or crash) during execution; that is, code that contains a bug completes its execution properly, but the output result is incorrect. Notably, if an erroneous output result consists of reasonable values, then the programmer might have no indication that something went wrong. It is impossible to estimate how many published studies contain results with bugs; however, given the ubiquity of bugs in non-scientific (industrial) software (Zhivich and Cunningham, 2009), it is plausible that academic code is no exception. Furthermore, the quality of custom code in cognitive neuroscience field in particular, is probably even worse than in the industry because (a) code in the field of cognitive neuroscience is usually written by people with only basic programming training—after all, they are brain researchers and not software engineers; (b) the code most often is programmed by a single researcher, without any code peer-review procedure (Wiegers, 2002); and (c) the custom code is usually used by a single or few lab members only. This last point is critical, because when the code is used by many, as is the case with large open-source projects like SPM (http://www.fil.ion.ucl.ac.uk/spm/), FieldTrip (http://fieldtrip.fcdonders.nl/), EEGLab (http://sccn.ucsd.edu/eeglab/) or PyMVPA (http://www.pymvpa.org/), the likelihood is low that a serious bug would remain unnoticed for a long time. The goal of this paper is to give practical advice to cognitive neuroscientists on how to minimize bugs in their custom data analysis code. The advice is illustrated using MATLAB schematic samples; executable code examples can be found in the Supplementary Materials.

Smartphone and medical applications use by contemporary surgical trainees: A national questionnaire study

Results: Thirty three percent (76/233) of trainees responded. Ninety two percent owned a smartphone. Trainees used smartphones at work for email (96%), calls (85%), SMS/MMS (81%), Internet browsing (76%) and medical app access (55%). Eighty two percent of respondents had downloaded at least one app, including clinical guidelines (70%), medical calculators (59%), anatomy guides (50%) and study aids (32%). There was no statistical difference between demographics and smartphone use or app downloads. Thirty five percent had used apps to help make clinical decisions. Thirteen percent felt they had encountered erroneous outputs, according to their own judgement and/or calculation. Fifty eight percent felt apps should be compulsorily regulated however only one trainee could name a regulatory body. Conclusion: Smartphone possession amongst NHS surgical trainees is high. Knowledge of app regulation is poor, with potential safety concerns regarding inaccurate outputs. Integration of apps, developed and approved by an appropriate authority, may improve confidence when integrating them into training and healthcare delivery.

Experimental evaluation of water vapour cross-sensitivity for accurate eddy covariance measurement of CO2 flux using open-path CO2/H2O gas analysers

Non-dispersive infrared CO2/H2O gas analysers produce erroneous CO2 outputs when CO2 is measured in humid air, unless a correction for water vapour cross-sensitivity is applied. Spectroscopic cross-sensitivities arising from direct absorption interference and from the pressure broadening effect are significant in CO2 flux measurements by the eddy covariance technique using open-path gas analysers over the ocean, as opposed to land-surface measurements, where CO2 fluxes are orders of magnitude larger. In this study, a widely used analyser with manufacturer-determined correction coefficients for both cross-sensitivities was tested by laboratory experiments. Our results showed that the correction coefficient for direct absorption interference was not optimised to calculate CO2 flux accurately, and that the correction coefficient for the pressure broadening caused overestimation of the CO2 mixing ratio flux in the same direction as the water vapour flux. Overestimations of open-path eddy covariance measurements of upward CO2 fluxes in previous ocean observations probably resulted from inaccuracies in both of these correction coefficients. We also found that slight changes in spectroscopic cross-sensitivities due to contamination of the analyser's optical windows by sea salt caused a low bias in CO2 outputs with increasing H2O; however, this contamination effect was not always observed in repeated tests under different contamination conditions. We suggest that previously proposed methods for correcting the effect of optical window contamination is of limited value and that measurement of small CO2 fluxes by the open-path eddy covariance technique over the ocean should be performed after confirming the spectroscopic cross-sensitivity and ensuring that the optical windows are as clean as possible.

Empirical Analysis of Controller Event Data to Select Vehicle Detector Fault Triggers

The proper detection of both vehicles and pedestrians is critical for operations of signalized intersections, especially intersections with adaptive traffic signal control. Faulty detectors must be identified as quickly as possible so that they can be repaired and their erroneous output corrected (e.g., preventing an adaptive algorithm from continuing to allocate green time to a detector that is stuck on). This study establishes a procedure to determine static detector fault thresholds (e.g., maximum detector on time and maximum detector off time) that can be programmed into a traffic signal controller. This procedure analyzes detector on and off durations over multiple days to define distributions of those parameters. The study analyzes data for 154 detectors in Morgantown, West Virginia, to generate on and off distributions and calculate the resulting 90th, 95th, and 99th percentile values. The detectors are divided into three groups on the basis of their physical locations relative to the intersection (e.g., stop bar or advance) and the approach function (e.g., mainline or minor). Default thresholds for the three groups are recommended for the signal system through the application of a 95% confidence limit to the 99th percentile values and local knowledge of the system. The procedure defined here can be applied to other signal systems to determine these thresholds.

A VELOUR PLEBISCITE TRACING FOR HARDWARE AND SOFTWARE MISCUE REMEDIAL SYSTEMS

Referending algorithms are used to adjudicate among the consequences of surplus modules in miscue-remedial systems. Not exactly, popular allies entail a request-precise ’Disciple Point’ value to be précised, whereas biased standard allies are incapable to generate a compassionate productivity while refusal concurrence exists between the allies inputs. The disciple is tentatively appraised from the summit of vision security and accessibility, and contrast with the imperfect popular disciple in a Triple Modular Redundancy prearranged outline. We show that the Velour disciple gives extra exact outputs (advanced accessibility) than the wrong popular disciple with petite and hefty slip-ups, fewer false outputs (superior security) than the imperfect popular disciple in the occurrence of tiny slip-ups, and a smaller amount kind outputs than the inaccurate popular choose. The proportion of the kind outputs of the bulk disciples that are fruitfully hold by the Velour fanatic (ensuing in accurate outputs) is more than the proportion of those that are disastrously determined by the Velour fanatic (ensuing in erroneous outputs).

New Metrics for the Reliability of Approximate and Probabilistic Adders

Addition is a fundamental function in arithmetic operation; several adder designs have been proposed for implementations in inexact computing. These adders show different operational profiles; some of them are approximate in nature while others rely on probabilistic features of nanoscale circuits. However, there has been a lack of appropriate metrics to evaluate the efficacy of various inexact designs. In this paper, new metrics are proposed for evaluating the reliability as well as the power efficiency of approximate and probabilistic adders. Reliability is analyzed using the so-called sequential probability transition matrices (SPTMs). Error distance (ED) is initially defined as the arithmetic distance between an erroneous output and the correct output for a given input. The mean error distance (MED) and normalized error distance (NED) are then proposed as unified figures that consider the averaging effect of multiple inputs and the normalization of multiple-bit adders. It is shown that the MED is an effective metric for measuring the implementation accuracy of a multiple-bit adder and that the NED is a nearly invariant metric independent of the size of an adder. The MED is, therefore, useful in assessing the effectiveness of an approximate or probabilistic adder implementation, while the NED is useful in characterizing the reliability of a specific design. Since inexact adders are often used for saving power, the product of power and NED is further utilized for evaluating the tradeoffs between power consumption and precision. Although illustrated using adders, the proposed metrics are potentially useful in assessing other arithmetic circuit designs for applications of inexact computing.

Erroneous continuous cardiac output by calibrated pulse contour analysis

Pulse contour analysis techniques are used for beat-to-beat tracking of cardiac output in critically ill patients. However, an adequate pulse pressure waveform signal and identification of the appropriate (i.e. systolic) part of the waveform by the monitor are crucial for correct calculation of continuous cardiac output. We observed a case where the monitor failed to correctly identify the systolic part of the waveform during tachycardia thus giving false readings. We would like to emphasize the importance of visually checking the waveform for any irregularities that may cause erroneous calculations before initiating a therapy based on these values. One advantage of the system used here is that the part of the pressure curve used for analysis is automatically indicated.

Low-Power Digital Signal Processing Using Approximate Adders

Low power is an imperative requirement for portable multimedia devices employing various signal processing algorithms and architectures. In most multimedia applications, human beings can gather useful information from slightly erroneous outputs. Therefore, we do not need to produce exactly correct numerical outputs. Previous research in this context exploits error resiliency primarily through voltage overscaling, utilizing algorithmic and architectural techniques to mitigate the resulting errors. In this paper, we propose logic complexity reduction at the transistor level as an alternative approach to take advantage of the relaxation of numerical accuracy. We demonstrate this concept by proposing various imprecise or approximate full adder cells with reduced complexity at the transistor level, and utilize them to design approximate multi-bit adders. In addition to the inherent reduction in switched capacitance, our techniques result in significantly shorter critical paths, enabling voltage scaling. We design architectures for video and image compression algorithms using the proposed approximate arithmetic units and evaluate them to demonstrate the efficacy of our approach. We also derive simple mathematical models for error and power consumption of these approximate adders. Furthermore, we demonstrate the utility of these approximate adders in two digital signal processing architectures (discrete cosine transform and finite impulse response filter) with specific quality constraints. Simulation results indicate up to 69% power savings using the proposed approximate adders, when compared to existing implementations using accurate adders.

Error analysis to improve the speech recognition accuracy on Telugu language

Speech is one of the most important communication channels among the people. Speech Recognition occupies a prominent place in communication between the humans and machine. Several factors affect the accuracy of the speech recognition system. Much effort was involved to increase the accuracy of the speech recognition system, still erroneous output is generating in current speech recognition systems. Telugu language is one of the most widely spoken south Indian languages. In the proposed Telugu speech recognition system, errors obtained from decoder are analysed to improve the performance of the speech recognition system. Static pronunciation dictionary plays a key role in the speech recognition accuracy. Modification should be performed in the dictionary, which is used in the decoder of the speech recognition system. This modification reduces the number of the confusion pairs which improves the performance of the speech recognition system. Language model scores are also varied with this modification. Hit rate is considerably increased during this modification and false alarms have been changing during the modification of the pronunciation dictionary. Variations are observed in different error measures such as F-measures, error-rate and Word Error Rate (WER) by application of the proposed method.

Error Rate Estimation for Defective Circuits via Ones Counting

With VLSI circuit feature size scaling down, it is becoming more difficult and expensive to achieve a desired level of yield. Error-tolerance employs defective chips that occasionally produce erroneous yet acceptable results in targeted applications, and has been proposed as one way to increase effective yield. These chips are characterized by criteria set by specific applications. Error rate, an upper-bound on how frequent errors occur at an output, is one such criterion. In this article we focus on the following problem: given a combinational logic circuit that is defective, and hence occasionally produces an erroneous output, how can we determine the error rate of each output line by using ones counting? The results of this work can also be used for runtime error estimation in aging systems and in environments where soft-errors are produced.

Beware the range in RANGE, and the academic in AWL

Abstract This article examines a recent example of published research on the vocabulary profile of a financial corpus based on the Academic Word List (AWL) to illustrate not only the erroneous output from vocabulary profiling tools but also the pitfalls of using the AWL as a filter for academic lexis. Recent research has cautioned against eschewing high frequency common words in deference to the indiscriminate use of the AWL as the basis of a syllabus to teach academic English. Researchers, however, continue to use the AWL as a measure of academic vocabulary and vocabulary profiling of texts and corpora. The resulting misconceptions about the nature of academic lexis are further compounded by the limitations of profiling tools that can lead to anomalies in statistical analysis and consequent misinterpretation of the data. The evidence provided clearly mitigates against excluding ’common‘ words in English from any academic word list, and suggests that academic word lists of any type may, in fact, be entirely redundant.

On the Improvement of Neural Cryptography Using Erroneous Transmitted Information With Error Prediction

Neural cryptography deals with the problem of "key exchange" between two neural networks using the mutual learning concept. The two networks exchange their outputs (in bits) and the key between the two communicating parties is eventually represented in the final learned weights, when the two networks are said to be synchronized. Security of neural synchronization is put at risk if an attacker is capable of synchronizing with any of the two parties during the training process. Therefore, diminishing the probability of such a threat improves the reliability of exchanging the output bits through a public channel. The synchronization with feedback algorithm is one of the existing algorithms that enhances the security of neural cryptography. This paper proposes three new algorithms to enhance the mutual learning process. They mainly depend on disrupting the attacker confidence in the exchanged outputs and input patterns during training. The first algorithm is called "Do not Trust My Partner" (DTMP), which relies on one party sending erroneous output bits, with the other party being capable of predicting and correcting this error. The second algorithm is called "Synchronization with Common Secret Feedback" (SCSFB), where inputs are kept partially secret and the attacker has to train its network on input patterns that are different from the training sets used by the communicating parties. The third algorithm is a hybrid technique combining the features of the DTMP and SCSFB. The proposed approaches are shown to outperform the synchronization with feedback algorithm in the time needed for the parties to synchronize.