Erroneous Bits Research Articles

Latency optimized clustered error mitigation for multi-level flash memory using product code

Soft errors due to radiation-induced multi-bit upsets (MBUs) are very prominent in the present flash memories built with ultra large scale VLSI technology. Use of multi-level cells in flash memories increase the chance of adjacent MBUs or clustered error. Single bit error detection and correction (EDAC) codes are not enough to mitigate the effect of clustered error due to their small error correction capability. On the other hand, commonly used multi-bit EDAC codes have large overhead, complex decoding circuitry, high error correction latency and are unable to correct large number adjacent erroneous bits. In this paper, we have proposed a product code coined as linear shortened block code based product code (LSBCPC) for mitigation of clustered error in the flash memory devices. LSBCPC utilizes latency optimized scalable shortened block code as the component code and can correct higher number of adjacent erroneous bits in memory devices compared to the other state of the art solutions. The proposed LSBCPC promises better error correction coverage with 28%, 14%, and 13% reduction in terms of redundant bits, 13%, 11%, and 10% reduction in terms of area and 24%, 26%,and 22% reduction in terms of latency in 16 × 16, 32 × 32 and 64 × 64 memory devices respectively compared to the highly cited research work. The performance of the proposed method is validated in terms of redundant bits, error correction coverage, mean error to failure, area consumption, power utilization and decoding latency.

Convolutional Neural Network-Aided Tree-Based Bit-Flipping Framework for Polar Decoder Using Imitation Learning

Known for their capacity-achieving abilities and low complexity for both encoding and decoding, polar codes have been selected as the control channel coding scheme for 5G communications. To satisfy the needs of high throughput and low latency, belief propagation (BP) is chosen as the decoding algorithm. However, it suffers from worse error performance than that of cyclic redundancy check (CRC)-aided successive cancellation list (CA-SCL). Recently, convolutional neural network-aided bit-flipping (CNN-BF) is applied to BP decoding, which can accurately identify the erroneous bits to achieve a better error rate and lower decoding latency than prior critical-set bit-flipping (CS-BF) mechanism. However, successive BF, having better error correction capability, has not been explored in CNN-BF since the more complicated flipping strategy is out of the scope of supervised learning. In this work, by using imitation learning, a convolutional neural network-aided tree-based multiple-bits BF (CNN-Tree-MBF) mechanism is proposed to explore the benefits of multiple-bits BF. With the CRC information as additional input data, the proposed CNN-BF model can further reduce 5 flipping attempts. Besides, a tree-based flipping strategy is proposed to avoid useless flipping attempts caused by wrongly flipped bits. From the simulation results, our approach can outperform CS-BF and reduce flipping attempts by 89% when code length is 64, code rate is 0.5 and SNR is 1 dB. It also achieves a comparable block error rate (BLER) as CA-SCL.

Improved Belief Propagation Polar Decoders With Bit-Flipping Algorithms

Since the inherent serial nature of successive cancellation list (SCL) decoding results in a long latency, belief propagation (BP) decoding for polar codes has drawn attention for high-throughput applications. However, its error correction performance is inferior to that of SCL decoding. Therefore, the bit-flipping strategy has been recently applied to BP decoding, which can approach the SCL decoding performance through multiple additional decoding attempts. The original BP flip (BPF) decoding suffers from an inaccurate identification of erroneous bits by a fixed flip set (FS), which has been improved by the generalized BPF (GBPF) decoding. In this article, the GBPF decoding is extended to support multiple bits being flipped in one decoding attempt. In addition, for two types of decoding errors: detected errors and undetected errors, we propose two novel methods to more effectively identify erroneous bits. For detected errors, the concept of loop sets is defined and a loop-based identification method is introduced based on the study of error patterns of BP decoding. On the other hand, a method to generate a more accurate fixed FS is proposed for undetected errors, which considers the bit error distribution under BP decoding. Combining the two methods, the GBPF with merged sets (GBPF-MS) decoding can achieve the SCL-8 performance and outperforms the state-of-the-art BPF, BP list, and SC flip (SCF) decoding, for polar codes with length 1024 and information rate 1/2. Implemented by 40nm CMOS technology, the proposed GBPF-MS decoder with ten flips exhibits an average throughput of 4.19 Gbps at 2.5 dB, which is $1.6\times $ and $1.72\times $ faster than the state-of-the-art SCL-4 and SCF decoders, respectively.

Nonbinary Low-Density Parity Check Decoding Algorithm Research-Based Majority Logic Decoding

In the nonbinary low-density parity check (NB-LDPC) codes decoding algorithms, the iterative hard reliability based on majority logic decoding (IHRB-MLGD) algorithm has poor error correction performance. The essential reason is that the hard information is used in the initialization and iterative processes. For the problem of partial loss of information, when the reliability is assigned during initialization, the error correction performance is improved by modifying the assignment of reliability at initialization. The initialization process is determined by the probability of occurrence of the number of erroneous bits in the symbol and the Hamming distance. In addition, the IHRB-MLGD decoding algorithm uses the hard decision in the iterative decoding process. The improved algorithm adds soft decision information in the iterative process, which improves the error correction performance while only slightly increasing the decoding complexity, and improves the reliability accumulation process which makes the algorithm more stable. The simulation results indicate that the proposed algorithm has a better decoding performance than IHRB algorithm.

Novel confidence level labelling methods for ADS‐B signals with coherent demodulation scheme

In the satellite-based application, low signal-to-noise ratio (SNR) is a considerable obstacle for automatic dependent surveillance-broadcast (ADS-B), leading to some erroneous bit declarations. In this case, the confidence level of each bit should be declared legitimately to make full use of error correction. In this study, the authors focus on methods to optimise the confidence declaration for ADS-B signals with coherent demodulation scheme. A novel optimal-threshold labelling method is firstly proposed for known and unknown amplitudes. They also present a dynamic-threshold labelling method, in which a specific threshold is unnecessary. Detailed theoretical analyses are carried out for the proposed methods and are verified by simulations. Finally, they make a comparison between different confidence level labelling methods in terms of reception performance and complexity. A conclusion is set forth that the methods have a high probability of correct reception at low SNRs.

Codes for Limited Magnitude Error Correction in Multilevel Cell Memories

Multilevel cell (MLC) memories have been advocated for increasing density at low cost in next generation memories. However, the feature of several bits in a cell reduces the distance between levels; this reduced margin makes such memories more vulnerable to defective phenomena and parameter variations, leading to an error in stored data. These errors typically are of limited magnitude, because the induced change causes the stored value to exceed only a few of the level boundaries. To protect these memories from such errors and ensure that the stored data is not corrupted, Error Correction Codes (ECCs) are commonly used. However, most existing codes have been designed to protect memories in which each cell stores a bit and thus, they are not efficient to protect MLC memories. In this paper, an efficient scheme that can correct up to magnitude-3 errors is presented and evaluated. The scheme is based by combining ECCs that are commonly used to protect traditional memories. In particular, Interleaved Parity (IP) bits and Single Error Correction and Double Adjacent Error Correction (SEC-DAEC) codes are utilized; both these codes are combined in the proposed IP-DAEC scheme to efficiently provide a strong coding function for correction, thus exceeding the capabilities of most existing coding schemes for limited magnitude errors. The SEC-DAEC code is used to detect the cell in error and correct some bits, while the IP bits identify the remaining erroneous bits in the memory cell. The use of these simple codes results in an efficient implementation of the decoder compared to existing techniques as shown by the evaluation results presented in this paper. The proposed scheme is also competitive in terms of number of parity check bits and memory redundancy. Therefore, the proposed IP-DAEC scheme is a very efficient alternative to protect and correct MLC memories from limited magnitude errors.

Lightweight (Reverse) Fuzzy Extractor With Multiple Reference PUF Responses

A physical unclonable function (PUF), like a fingerprint, exploits manufacturing randomness to endow each physical item with a unique identifier. One primary PUF application is the secure derivation of volatile cryptographic keys using a fuzzy extractor (FE) comprising: 1) a secure sketch and 2) an entropy extractor. Although the entropy extractor can be lightweight, the overhead of the secure sketch responsible for correcting naturally noisy PUF responses is usually high. We observe that, in general, response unreliability with respect to an enrolled reference measurement increases with increasing differences between the in-the-field PUF operating condition and the operating condition used in evaluating the enrolled reference response. For the first time, we exploit such an inadvertent but important observation. In contrast to the conventional single reference response enrollment, we propose enrolling multiple reference responses (MRRs) subject to the same challenge but under multiple distinct operating conditions. The critical observation here is that one of the reference operating conditions is likely to be closer to the operating condition of the field deployed PUF, thus resulting in minimizing the expected unreliability when compared to the single reference under the nominal condition. As a consequence, MRR greatly reduces the demand for the expected number of erroneous bits requiring correction and, subsequently, achieves a significant reduction in the error correction overhead. The significant implementation efficiency gains from the proposed MRR method are demonstrated from software implementations of FEs on batteryless resource constraint computational radio frequency identification devices, where realistic PUF data are collected from intrinsic static random access memory PUFs.

The Effect of Error Propagation on the Performance of Polar Codes Utilizing Successive Cancellation Decoding Algorithm

In this paper, we discuss and analyze the effect of error propagation on the performance polar codes decoded using the successive cancellation algorithm. We show that error propagation due to erroneous bit decision is a catastrophic issue for the successive cancellation decoding of polar codes. Even a wrong decision on a single bit may cause an abundance of successor bits to be wrongly decoded. Furthermore, we observe that the performance of polar codes is significantly improved if even single bit errors are detected and corrected before the decoding of successor bits.

Path Splitting Selecting Strategy-Aided Successive Cancellation List Algorithm for Polar Codes

Successive cancellation list (SCL) decoder provides a good trade-off between error-correcting performance and complexity. To simplify the decoding algorithm with negligible performance loss, a path splitting selecting (PSS) strategy is proposed based on analyzing the reason why the SCL decoder fails. On the basis of the PSS strategy, two schemes are proposed to find erroneous information bits more accurately. Simulation results show that the proposed strategy based on the search set and decision function is a good solution to reduce the complexity with almost no performance loss.

EPLC-CMAC: An enhanced cooperative MAC protocol for broadband PLC systems

In this work, we introduce an enhanced cooperative medium access control protocol which merges a cooperative protocol with a packet correction technique at the link layer level. The proposed protocol aims to improve data communication reliability of in-home broadband power line communication (PLC) systems. More specifically, the cooperative protocol performs relayed retransmissions according to the relay availability, for assisting data communication between nodes source and destination. In case a data packet retransmission fails, the node destination uses corrupted copies from the transmitted and the retransmitted packets from nodes source and relay, respectively, which are stored in its buffer, in order to detect and correct the erroneous bits. The performance evaluation of the proposed protocol is accomplished by simulations based on measured power line channel frequency responses and an additive noise model of in-home electric power grids, which cover broadband applications and bit error pattern at the link layer level. The physical layer makes use of orthogonal frequency division multiplexing and orthogonal frequency division multiple access schemes. Furthermore, a comparison among PLC systems using the proposed protocol to others using only a cooperative protocol and without any cooperative protocol at link layer is analyzed. Numerical results show that improvements in terms of data communication reliability can be achieved in comparison with previous protocols under the presence of background and impulsive noises.

Improved Polar SCL Decoding by Exploiting the Error Correction Capability of CRC

Novel successive cancellation list (SCL) decoding schemes of Polar codes by exploiting the error correction (EC) capability of the cyclic redundancy check (CRC) codes are proposed in this paper. Different from the schemes in the literature that only considered the error detection capability of CRC, the proposed schemes aim to improve the performance of CRC-aided Polar decoding to the most by benefiting from the potential EC capability of CRC. Specifically, we first propose a basic decoding scheme, named CRC error-correction-aided successive cancellation list (CRC-EC-SCL) decoding, by introducing the look-up-table-based CRC EC method into the Polar SCL decoding process. Then, based on the basic scheme, we further propose the segmented-CRC-EC-SCL decoding scheme. By segmented-CRC, the information block is divided into multiple segments and each segment is attached with a shorter CRC sequence. By conducting the CRC-EC-aided coding for each of the segments, multiple erroneous bits can be corrected early and error propagation can, thus, be efficiently suppressed. The simulation results show that both of the proposed decoding schemes have a significant performance gain over the classic CRC-EC-SCL decoding scheme. Especially for the segmented-CRC-EC-SCL, the performance gain at a frame error rate of 10−4 is about 0.4 dB. Moreover, the average computation complexity of the segmented-CRC-EC-SCL is close to the classic scheme.

OFDM comparison with FFT and DWT processing for DVB-T2 wireless channels

Introduction: Recent studies on the FFT processing (Fast Fourier Transform) or DWT (Discrete Wavelet Transform) of the OFDM signal (Orthogonal Frequency Division Multiplexing) have shown pros and cons for DVB-T2 (Digital Video Broadcasting-Second Generation Terrestrial) radio communications; however, the benefits of both types of processing have yet to be compared for the same scenario.
 Objective: The objective of this research is to compare the response of the wireless channel with AWGN noise (Additive White Gaussian Noise Channel) and Rayleigh and Rician fading in the UHF (Ultra High Frequency) band.
 Methodology: The transmission of DVB-T2 information with OFDM modulation and FFT and DWT processing was simulated in Matlab®, specifically in Simulink.
 Results: The results of the study proved to be more efficient for DWT system than FFT system, due to the low rate of erroneous bits, spectral efficiency and reduction of the Peak-to-Average Power Ratio (PAPR), for Eb / No relations greater than 10dB.
 Conclusions: In this article, we present the designs of both systems and the results of the research experience; likewise, the practical applicability of these systems is discussed, and improvements are suggested for future work.

TriZone: A Design of MLC STT-RAM Cache for Combined Performance, Energy, and Reliability Optimizations

Spin-transfer torque random access memory (STT-RAM) is a promising technology for future nonvolatile caches and memories. To increase the storage density, multilevel cell (MLC) technique was recently introduced to STT-RAM designs at the cost of degraded access speed, reliability, and energy efficiency. Existing MLC STT-RAM cache architectures primarily focus on the performance and energy optimizations but ignore the crucial demand for reliability. In this paper, we propose “TriZone”—a holistic design scheme for MLC STT-RAM cache to simultaneously meet the requirements of performance, energy, and reliability. Three cache block configurations, namely hard, soft, and mixed, are constructed with the hard-bit, soft-bit, and both hard-bit and soft-bit of MLC STT-RAM, respectively. By observing the difference of these cache blocks, a nonuniform strength ECC (NUS-ECC) is developed to guarantee the operational reliability of a cache block with a variable decoding delay adapting to the needs of error correction (e.g., the number of the erroneous bits). The whole MLC STT-RAM cache is then partitioned into three regions, each of which is composed of different cache blocks. In order to achieve the best tradeoff among performance, energy, and reliability, we then introduce the dynamic cache partitioning to determine the partition of this tri-way MLC STT-RAM cache according to the runtime characteristic of various applications. Experiment results show that compared with conventional performance-driven MLC STT-RAM cache design with pessimistic ECC, TriZone can improve the system performance and energy by averagely 11.7% (10.0%) and 13.3% (15.7%), respectively, for single-threaded (multiprogram) applications. The additional area overhead associated with NUS-ECC is limited by ~ 3%.

Cross-layer energy model for beacon-enabled 802.15.4 networks

A transmitted frame in a wireless sensor network (WSN) may get corrupted due to erroneous bits in the frame, an event characterized at the physical (PHY) layer. The frame may also get dropped at medium access control (MAC) layer due to collision with other frames. As energy is wasted due to both, a combined cross-layer (PHY + MAC) model is needed for evaluating the energy for every successful transmission at frame/bit level. The model would also help in assessing how green a technique is, which might be proposed for PHY/ MAC layer of any WSN, by computing the improvement in energy efficiency. In this paper, we present a cross-layer energy model for communication in beacon-enabled 802.15.4 networks operating in star topology. IEEE 802.15.4 is the worldwide accepted WSN standard. Further, for status monitoring and event detection, which are the most common low data rate WSN applications, sensor nodes form a star topology where a central node sends periodic beacons to access data from all other nodes. Our model includes energy consumption for both source and destination node during the actual frame transmission as well as during the operations that precede frame transmission such as backoff and clear channel assessment (CCA). A two dimensional Markov model has been adopted for the purpose and parameters like average number of backoffs and average number of CCAs have been computed. Finally, the energy consumption per successful bit transmission is found by combining the collision probability in MAC layer and error probability in PHY layer. The results revealed that while the number of nodes in a WSN does not affect the energy consumption much, the frame length has a huge influence. Also, energy consumption rises considerably when acknowledgement is opted for.

A simple, label-free, electrochemical DNA parity generator/checker for error detection during data transmission based on "aptamer-nanoclaw"-modulated protein steric hindrance.

Versatile DNA logic devices have exhibited magical power in molecular-level computing and data processing. During any type of data transmission, the appearance of erroneous bits (which have severe impacts on normal computing) is unavoidable. Luckily, the erroneous bits can be detected via placing a parity generator (pG) at the sending module and a parity checker (pC) at the receiving module. However, all current DNA pG/pC systems use optical signals as outputs. In comparison, sensitive, facilely operated, electric-powered electrochemical outputs possess inherent advantages in terms of potential practicability and future integration with semiconductor transistors. Herein, taking an even pG/pC as a model device, we construct the first electrochemical DNA pG/pC system so far. Innovatively, a thrombin aptamer is integrated into the input-strand and it functions as a "nanoclaw" to selectively capture thrombin; the electrochemical impedance changes induced by the "nanoclaw/thrombin" complex are used as label-free outputs. Notably, this system is simple and can be operated within 2 h, which is comparable with previous fluorescent ones, but avoids the high-cost labeled-fluorophore and tedious nanoquencher. Moreover, taking non-interfering poly-T strands as additional inputs, a cascade logic circuit (OR-2 to 1 encoder) and a parity checker that could distinguish even/odd numbers from natural numbers (0 to 9) is also achieved based on the same system. This work not only opens up inspiring horizons for the design of novel electrochemical functional devices and complicated logic circuits, but also lays a solid foundation for potential logic-programmed target detection.

Soft Error Tolerance in Memory Applications

This paper proposes a new method to detect and correct multi bit errors in memory applications using a combination of a clustering approach, Bit-Per-Byte error detection technique, and Majority Logic Decodable (MLD) codes. The likelihood of soft errors accelerates with system complexity, reduction in operational voltages, exponential growth in transistor per chip, increases in clock frequencies, breakdown of memory reliability and device shrinking. Memories are the sensitive part of a computer system. Soft errors in memories may cause an instruction to malfunction. Several techniques are already in practice to mitigate the soft errors. Majority logic decodable codes are proved as effective for memory applications because of their ability to correct a massive number of errors. Since memories are used to hold large number of bits that’s the restraint of Majority logic decodable codes method, so we emphasize on the size of data word in this method. The proposed method aims to detect and correct up to seven bit errors with lesser computational time. It works in an efficient manner in case of adjacent errors which is not possible in Majority logic decodable codes (MLD). It is delineated by Experimental reviews that the proposed approach outperforms existing dominant approach with respect to number of erroneous bit detection and correction, and computational time overhead.

Towards Extended Bit Tracking for Scalable and Robust RFID Tag Identification Systems

The surge in demand for Internet of Things (IoT) systems and applications has motivated a paradigm shift in the development of viable radio frequency identification technology (RFID)-based solutions for ubiquitous real-time monitoring and tracking. Bit tracking-based anti-collision algorithms have attracted considerable attention, recently, due to its positive impact on decreasing the identification time. We aim to extend bit tracking to work effectively over erroneous channels and scalable multi RFID readers systems. Towards this objective, we extend the bit tracking technique along two dimensions. First, we introduce and evaluate a type of bit errors that appears only in bit tracking-based anti-collision algorithms called false collided bit error in single reader RFID systems. A false collided bit error occurs when a reader perceives a bit sent by tag as an erroneous bit due to channel imperfection and not because of a physical collision. This phenomenon results in a significant increase in the identification delay. We introduce a novel, zero overhead algorithm called false collided bit error selective recovery tackling the error. There is a repetition gain in bit tracking-based anti-collision algorithms due to their nature, which can be utilized to detect and correct false collided bit errors without adding extra coding bits. Second, we extend bit tracking to “error-free” scalable mutli-reader systems, while leaving the study of multi-readers tag identification over imperfect channels for future work. We propose the multi-reader RFID tag identification using bit tracking (MRTI-BT) algorithm which allows concurrent tag identification, by neighboring RFID readers, as opposed to time-consuming scheduling. MRTI-BT identifies tags exclusive to different RFIDs, concurrently. The concept of bit tracking and the proposed parallel identification property are leveraged to reduce the identification time compared to the state-of-the-art.

Quantized Feedback-Based Diagonal Precoding for $N \times 1$ MISO System With Generalized Orthogonal Space-Time Block Codes

In this paper, we propose an imperfect quantized feedback-based diagonal precoding scheme for generalized orthogonal space-time block codes in an $N \times 1$ multiple-input single-output (MISO) wireless communication system employing $M$ -QAM constellation. It is well known that a feedback-based precoding scheme aids channel adaptive signaling in wireless communication system and capitulates large improvements in almost all performance metrics. However, a practical feedback link is susceptible to error due to wireless channel fading and leads to wrong precoder selection. Therefore, a signal-to-noise ratio (SNR) adaptive error-tolerant weighting scheme is introduced which provides significant gain in comparison with another proposed arbitrarily fixed SNR error-tolerant weighting scheme. At first, a tight approximate closed-form expression of average symbol-error-rate (SER) and an exact analytical expression of outage probability are derived under imperfect feedback information with the help of order statistics. By minimizing the derived average SER, optimized transmit weights for the diagonal precoding matrix (based on feedback bits) are obtained. Later, a closed-form expression of the ergodic capacity with erroneous feedback bits for arbitrary MISO system is also provided by using the moment generating function approach. Further, numerical results show that the considered error-tolerant schemes outperform the uniform power allocation scheme in term of all the investigated performance metrics.

Efficient Decoding of LDM Core Layer at Fixed Receivers in ATSC 3.0

In order to decode an enhanced layer (EL) signal for a layered-division multiplexing (LDM) system at fixed receivers in ATSC 3.0, low-density parity-check (LDPC)/BCH decoding and successive interference cancellation should be performed to eliminate the core layer (CL) signal. For a high signal-to-noise ratio environment and sufficient low injection level of the EL signal, the CL bit-interleaved coded modulation decoder can easily achieve quasi error free for the whole LDPC codeword. However, for high injection levels, there may be still many erroneous bits in the parity part even after LDPC/BCH decoding since the ATSC 3.0 LDPC codes have the characteristic of unequal error protection due to the unequal weight distributions in their parity-check matrices. Therefore, ATSC 3.0 receivers should include re-encoding module for CL LDPC codes to completely recover the CL signal for LDM system. In this paper, we propose an efficient method to reconstruct CL signal in ATSC 3.0 LDM systems, which can be realized by a modified re-encoding after LDPC decoding of the CL signal. It significantly reduces the computational complexity and worst case latency without any loss of coding performance.

A Novel Error Correction Scheme In Quantum Key Distribution (Qkd) Protocol

Ideally, in any quantum key distribution (QKD) communication system, each sifted key is expected to be received without error. However in practice, due to infeasibility of generating pure single photon and device impairment problem, some of the sifted key may experience errors. This results to the increment of quantum bit error rate (QBER) that requires error reconciliation for correcting error. The main concept in error reconciliation is very much related to the capability of correcting all errors while minimizing eavesdrop information. The quantum error correcting code such as Hamming code which used in Winnow protocol is found to be more attractive. However the Winnow protocol can only correct one error out of seven bits. Adopting this classical error correcting code, an improved reconciliation scheme namely Siao Ping 1985 (SP 1985) protocol is proposed in this paper to correct more errors in faster pace without additional formulation for the overall simplicity criterion. This research is aimed at building up efficiency and effectiveness of reconciliation of the robust BB84 protocol in coping with noise interference. The proposed SP 1985 reconciliation protocol utilizes a pair of forward and reverse order syndromes for error pattern recognition. It is carried out in a simple structure which can correct up to double erroneous bits and detect four erroneous bits for each seven bits. Therefore, it is sufficient to deliver the desirable outcome after investigating its capability by correcting two errors out of seven bits compared to Winnow protocol. Its effectiveness can be measured based on simulation result which leads to reducing the QBER.