Equivalent Parallel Conductance Research Articles

Analysis of fast and slow responses in AC conductance curves for p-type SiC MOS capacitors

We used a conductance method to investigate the interface characteristics of a SiO2/p-type 4H-SiC MOS structure fabricated by dry oxidation. It was found that the measured equivalent parallel conductance–frequency (Gp/ω–f) curves were not symmetric, showing that there existed both high- and low-frequency signals. We attributed high-frequency responses to fast interface states and low-frequency responses to near-interface oxide traps. To analyze the fast interface states, Nicollian’s standard conductance method was applied in the high-frequency range. By extracting the high-frequency responses from the measured Gp/ω–f curves, the characteristics of the low-frequency responses were reproduced by Cooper’s model, which considers the effect of near-interface traps on the Gp/ω–f curves. The corresponding density distribution of slow traps as a function of energy level was estimated.

Fast and slow traps in Al2O3/(GaN)/AlGaN/GaN heterostructures studied by conductance technique

Influence of interface traps at Al2O3/(GaN)/AlGaN interface at low and high frequency on equivalent parallel conductance of Al2O3/(GaN)/AlGaN/GaN heterostructure capacitor was studied. By the conductance measurements two types of traps were identified in the measured structure. The traps differ in time constants by more than one order in magnitude. Fast traps with low time constants have narrow energy distribution and are probably located in the semiconductor energy gap close to the insulator semiconductor interface. Slow traps have wider distribution and are assumed to be directly at the insulator semiconductor interface. The presence of the fast traps which are able to respond to external ac signal is given into connection with the recently published increase of the structure capacitance in the plateau region with decreasing frequency.

(NH4)2S Passivation of High-k/In0.53Ga0.47As Interfaces: A Systematic Study of (NH4)2S Concentration

In this work we present the results of an investigation into the effectiveness of varying (NH4)2S concentrations in the passivation of n-type and p-type In0.53Ga0.47As, as determined through analysis of electrical properties. Samples were degreased and immersed in aqueous (NH4)2S solutions of concentrations 22%, 10%, 5%, or 1% for 20 minutes at 295K, immediately prior to ALD growth. Capacitance-voltage results on capacitor structures indicate that the lowest frequency dispersion over the bias range examined occurs for n and p-type devices treated in 10% (NH4)2S solution. The deleterious effect on interface state density of increased ambient exposure time after removal from (NH4)2S solution is also presented. Estimations of peak interface state density, Dit, extracted from the equivalent parallel conductance Gp, using an approximation to the conductance method, are used for comparison of the different passivation conditions.

Electrical Analyses of Germanium MIS Structure and Spectroscopic Measurement of the Interface Trap Density in an Insulator/Germanium Interface at Room Temperature

In this paper, we present an equivalent circuit model of a germanium (Ge) MIS structure that is biased in the inversion region, which includes the effects of the high intrinsic carrier density and high diffusion-limited conductance of the Ge substrate at room temperature. The model can successfully express the gate bias and frequency dependences of the capacitance characteristics that are specific to the Ge MIS capacitor. Moreover, it will be shown that the interface trap density and its gate bias dependence in the inversion region can be spectroscopically determined from the gate bias and measurement frequency dependences of the equivalent parallel conductance of the Ge surface.

Electrical Characterization Techniques of Dielectric Thin Films Using Metal–Insulator–Metal Structures

In this paper, we describe an electrical characterization technique of dielectric thin films using metal–insulator–metal (MIM) structures and an LCR meter. It is demonstrated theoretically and experimentally that the equivalent parallel conductance and equivalent parallel capacitance of MIM capacitors necessarily show artificial frequency dispersions due to the effects of series resistance, owing to electrode and probing contact resistances. A procedure to extract the true equivalent parallel conductance and capacitance from measured admittance data is presented.

Influence of implantation energy on the electrical properties of ultrathin gate oxides grown on nitrogen implanted Si substrates

Metal–oxide–semiconductor tunnel diodes with gate oxides, in the range of 2.5–3.5 nm, grown either on 25 or 3 keV nitrogen-implanted Si substrates at (0.3 or 1) ×1015 cm−2 dose, respectively, are investigated. The dependence of N2+ ion implant energy on the electrical quality of the growing oxide layers is studied through capacitance, equivalent parallel conductance, and gate current measurements. Superior electrical characteristics in terms of interface state trap density, leakage current, and breakdown fields are found for oxides obtained through 3 keV nitrogen implants. These findings together with the full absence of any extended defect in the silicon substrate make the low-energy nitrogen implantation technique an attractive option for reproducible low-cost growth of nanometer-thick gate oxides.

Elucidation of the switching processes in tetragonal pzt by hysteresis loop and impedance analysis

The switching process in tetragonal PZT films is studied. The ferroelectric capacitors show rectangular P-E hystersis loops with very abrupt switching characteristics. Small signal impedance measurements as function of DC bias voltage reveal an abrupt drop of the parallel capacitance C near the switching field EC, coinciding with a sharp peak of the equivalent parallel conductance G, different from the more gradual variation of C and G with broad peaks near EC as typically observed in materials with MPB composition. This behavior is correlated to strong 180° switching in this tetragonal material. This is further corroborated by the effects of the film orientation and of electrical and stress poling.

Interface trap conductance spectroscopy of a narrow-gap Hg1-xCdxTe (x approximately=0.2) MIS device

The observation of a pronounced double peak structure in the equivalent parallel conductance of a metal-insulator-semiconductor (MIS) device prepared on a Bridgman-grown x approximately=0.2 p-type Hg1-xCdxTe crystal passivated by an anodic oxide layer is reported. The first peak, placed in the depletion part of the conductance-voltage (G-V) curves, has been attributed to the response of single-level interface traps distributed over the semiconductor gap supposing band-bending fluctuations. The second peak, placed at the onset of strong inversion, is due to shunting of the minority carrier flow by the electrons coming from the inverted surface area beyond the gate. An order of magnitude enhancement of the structure measured on capacitance-voltage (C-V) and G-V curves below T approximately=10 K has been attributed to hole freezeout, leading to a substantially slower sample response and to an exponential increase of its series resistance. The tunnelling from acceptor states near the Fermi level to interface traps and/or to light hole states in the valence band becomes a competing mechanism to majority carrier response in the depletion and accumulation regions in that case.

Analytic approach to the a.c. conductance method for rapid characterization of interface states in MOS structures

Nicollian and Goetzberger's well known integral expression for the equivalent parallel conductance due to interface states G p / ω has been given a simple analytical representation which is valid under the condition that interface potential fluctuation parameter σ > 1.5. Previous methods of conductance analysis based upon numerical and/or graphical construction are provided with alternative analytic relations. The earlier parametric numerical relations like ξ p, f w, f D and ln( ξ +/ ξ −) vs σ are described very well by analytic expressions in this paper. A new relation is presented to determine interface state time constant from the width of conductance peak. A new method is presented to determine dependence of σ on interface band bending from G p / ω vs bias measurements at just two frequencies. The expedient method of Nicollian, Goetzberger and Lopez utilises the same two curves to determine distribution of interface state density N ss and capture cross section σ p across the band gap. Therefore using the present new method for σ determination and other analytical relations for N ss and σ p determination, the expediency of their method is greatly enhanced. Complete conductance analysis for rapid characterization of the interface is shown to become now a simple straight forward affair, and the amount of data required is also substantially reduced.

ChemInform Abstract: Surface‐State Properties of n‐CdSe in Sulfide Solutions

Abstractare investigated by the equivalent parallel conductance technique.

Surface-state properties of n-cadmium selenide in sulfide solutions

The equivalent parallel conductance technique was used to study surface-state behavior at the n-CdSe single crystal/aqueous sulfide interface. Surface states were found at -1.1 V versus SCE (approx. 0.6 eV below the conduction band minimum) in solutions containing hydroxide and sulfide. The phase-sensitive photocurrent was affected by these states. Addition of dissolved sulfur to the solution removed the hump in the conductance versus voltage curves caused by these states and the photocurrent behavior is also improved.

The contribution of bulk states to the ac conductance of metal-insulator-semiconductor diodes

Measurements of the density of interface states in metal-insulator-semiconductor diodes by conductance techniques have revealed two resonances in the equivalent parallel conductance. Interface states are responsible for one, but the other is due to bulk states in the silicon crossing the Fermi energy in the depletion region. This latter contribution is found to resonate at a fixed frequency independent of the bias applied to the diode, unlike the interface state response which varies in the normal way. From the maximum in the equivalent parallel conductance we have calculated the density of bulk states to be 1014 cm−3 and identified sodium as the likely impurity responsible.

Charge fluctuations in SiO-2Si interface

On the homogeneous (as indicated by a small scanning mercury probe) regions of an SiO2-Si structure the dependences of MIS conductance on frequency were measured. It was found that the equivalent parallel conductance due to surface states has a narrow peak in the Gt/tuω-ωplot. This result contradicts the generally accepted view of small (50-500 A) surface potential fluctuations in SiO2-Si structures, enabling us to suppose that real MIS structures have separate (more than 10 μm) homogeneous regions approaching the ideal interface model. Therefore the concept of a geometrical spectrum of charge fluctuations has to be revised to emphasize large A components (like a 1/f frequency spectrum of noise).

Photoelectrochemical Characterization of CdSe Thin Film Anodes

Photoelectrochemical characterization of thin films prepared by a chemical solution growth technique was carried out by linear‐sweep voltammetry, current‐voltage measurements under forward and reverse bias, photocurrent‐wavelength measurements, and electrical impedance measurement techniques. The quality of the present junctions for photovoltaic applications was assessed by examining the effect of varying light intensity on current‐voltage behavior. The ideality factors (n) were determined for these junctions by modeling the junction in terms of a Schottky barrier. Values of close to 2 were obtained and were attributed to the dominating influence of recombination‐generation currents (either at the surface or in the depletion region) on the overall photovoltaic characteristics. The presence of a thin, tunnelable layer on the electrode surface was postulated as causing the nonideal current‐voltage behavior particularly in the reverse‐bias regime. Equivalent circuits for the interface were developed using a novel technique for measuring the equivalent parallel conductance and capacitance as a function of signal frequency and applied bias. A method of extracting flatband potentials based on conductance measurements is demonstrated using the thin film/electrolyte interface.

Conductance(G)-Bias(V) Method for Interface States in MUS Structure

A conductance(G)-bias(V) method capable of revealing the interface states characteristics of MOS structure more easily is proposed instead of the conventional conductance(G)-frequency(F)method. The majority carrier density of the semiconductor surface is changed by a gate d.c.bias. Hence, the change of the time constant of the interface state (Nss) is changed by the bias.The G-V method by considering the change of the time constant is developed on the basis of the conventional G-f method by the tunneling model. From the equivalent parallel conductance Gp-V curve measured at 1 MHz, the capture cross-section σ0 and the maximum tunnel distance d are obtained σ0=1.72×10-16 cm-2 and d=3.6Å using a maximum Gp and a ratio of Gp to d.c. bias near the Gpmax. The measurable energy range of Nss is wider than that of the G-f method Nss is approximately constant around 7.6×1011 cm-2·eV-1 near the Gpmax region where the energy range is from 0.15eV to 0.25eV above the top of the valence band in the case of a p-type(0.9Ωcm) MOS sample with steam grown SiO2.

Surface State Generation in MOS Structure by Applying High Field to the SiO2 Film

Effects of high electric fields applied to the gate oxide on MOS devices have been investigated. It is found that conventional MOS devices exhibit a shift of flatband voltage in the negative direction and a decrease of channel conductance as a consequence of the higher field applied (<7×106V/cm) to the gate electrode. These degradations become significant as the applied field is increased regardless of its polarity. They are ascribed to surface state generation at the Si–SiO2 interface and to defect formation in the oxide. The surface state density takes a maximum value, typically 1013/cm2, for an applied field of 8.5×106V/cm at 0.29eV below the conduction band edge. The equivalent parallel conductance vs. gate voltage curve with a gate-controlled diode shows a peak in the weak inversion region in addition to the ordinary peak in the depletion region. The peak in the weak inversion region can be attributed to minority carrier transitions between the surface states and the minority carrier energy band.

The Si-SiO2Interface - Electrical Properties as Determined by the Metal-Insulator-Silicon Conductance Technique

Measurements of the equivalent parallel conductance of metal-insulator-semiconductor (MIS) capacitors are shown to give more detailed and accurate information about interface states than capacitance measurements. Experimental techniques and methods of analysis are described. From the results of the conductance technique, a realistic characterization of the Si–SiO <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> interface is developed. Salient features are: A continuum of states is found across the band gap of the silicon. Capture cross sections for holes and electrons are independent of energy over large portions of the band gap. The surface potential is subject to statistical fluctuations arising from various sources. The dominant contribution in the samples measured arises from a random distribution of surface charge. The fluctuating surface potential causes a dispersion of interface state time constants in the depletion region. In the weak inversion region the dispersion is eliminated by interaction between interface states and the minority carrier band. A single time constant results. From the experimentally established facts, equivalent circuits accurately describing the measurements are constructed.

Polarization in Electrolytic Solutions. Part I. Theory

The theory of ``Conductance in Polarizable Media'' developed by one of the authors is modified in such a way as to be applicable to electrolytic solutions. This is achieved by the introduction of a new set of boundary conditions. In their original form they expressed the fact that the polarizing ions could not carry any current through the boundary. Now it is assumed that the discharge at the electrodes is a rate process of the first order, characterized by a rate constant ξ. In Sec. II the case of an applied ac voltage is treated. The expressions for the equivalent parallel conductance and capacitance of the polarization layer 1/Rp and Cp are derived by the same method, and to the same extent, as in the older theory. If ξ tends to zero, the previous results are obtained (``completely blocked electrode''). If ξ increases, the ``polarization capacitance'' and the ``excess resistance'' both decrease until they vanish for ξ=∞ (``open electrode''). The dependence on frequency remains similar for all finite values of ξ, and is represented in Figs. 1 and 2. Subsequently, in Sec. III, the older theory is improved by a determination of the thickness of the polarization layer. Reduced values of 1/Rp and Cp can be represented as universal functions of one reduced variable, which is proportional to the frequency. The two universal functions are tabulated to some extent in Table I. Finally the theory is extended to the case where several groups of ions of different mobilities are present in the electrolyte.