Equivalent Oxide Thickness Research Articles

High-κ monocrystalline dielectrics for low-power two-dimensional electronics.

The downscaling of complementary metal-oxide-semiconductor technology has produced breakthroughs in electronics, but more extreme scaling has hit a wall of device performance degradation. One key challenge is the development of insulators with high dielectric constant, wide bandgap and high tunnel masses. Here, we show that two-dimensional monocrystalline gadolinium pentoxide, which is devised through combining particle swarm optimization algorithm and theoretical calculations and synthesized via van der Waals epitaxy, could exhibit a high dielectric constant of ~25.5 and a wide bandgap simultaneously. A desirable equivalent oxide thickness down to 1 nm with an ultralow leakage current of ~10-4 A cm-2 even at 5 MV cm-1 is achieved. The molybdenum disulfide transistors gated by gadolinium pentoxide exhibit high on/off ratios over 108 and near-Boltzmann-limit subthreshold swing at an operation voltage of 0.5 V. We also constructed inverter circuits with high gain and nanowatt power consumption. This reliable approach to integrating ultrathin monocrystalline insulators paves the way to future nanoelectronics.

Super High-k Unit-Cell-Thick α-CaCr2O4 Crystals.

High-dielectric-constant (high-k) insulators are indispensable components to integrate semiconductors into metal-oxide-semiconductor field-effect transistors with sub-10 nm channel length, where the equivalent oxide thickness (EOT) of high-k insulator needs to be decreased to subnanometer scale. The traditional insulators, including Al2O3, SiO2, and HfO2, fit well with the existing silicon industry but suffer from serious degeneration of insulating properties, such as large leakage currents caused by high-density borders and interface traps, when their thicknesses are reduced to a few nanometers. Here, we synthesize a high-quality nonlayered ultrathin α-CaCr2O4 crystal down to unit-cell thickness (∼1.2 nm) by an elements slow-supply chemical vapor deposition (CVD) method. The unit-cell-thick α-CaCr2O4 crystals show a super high dielectric constant of 87.34, which is over 20 times higher than that of well-known layered insulator h-BN and corresponds to an EOT below 1 nm. Furthermore, it has a high breaking strength (39 GPa) and excellent stability. This strategy can also be used to fabricate other ultrathin ternary oxides, such as high-k ultrathin FeNb2O6 crystals, demonstrating the universality of the CVD method.

Electrical and UV-sensing performance of N-doped-Ba(Ti,Zr,Mo,Hf,Ta)O3-dielectric and ZnSnO-channel-based flexible thin-film transistors

Flexible thin-film transistors (TFTs) based on N-doped Ba(Ti,Zr,Mo,Hf,Ta)O3 dielectric and ZnSnO channel show high electrical and UV-sensing performance. The optimal N-doped Ba(Ti,Zr,Mo,Hf,Ta)O3 compositions with low equivalent oxide thicknesses (≈2 nm) and high-entropy (configurational entropy ≈ 1.59 R) are efficiently determined from a wide composition space (library). The film library is patterned to 450 metal–insulator-metal stacks, revealing dielectric constants ≈ 262–322 and loss (tan δ) ≈ 0.01–0.30 for the N-doped Ba(Ti,Zr,Mo,Hf,Ta)O3 at 1 kHz. The library is further integrated to 63 TFTs, and the promising ones exhibit the remarkable parameters: current on/off ratio of 108, threshold voltage (VT) of 0.02 V, saturation field-effect mobility of ≈76 cm2⋅V−1⋅s−1, and subthreshold swing of 0.062 V dec−1. The devices also exhibit desirable long-term stability for up to five months and perform reliably with small or negligible changes in VT and drain-source current under various gate-bias stress and temperature conditions. Furthermore, the TFT-based ultraviolet (253 nm) detector demonstrates impressive sensitivity (≈ 2 × 106) and responsibility (≈ 1171.9 A W−1). There is no substantial degradation in electrical or sensing characteristics under various levels of deformation. Charge transport in constructed energy band diagrams is used to elucidate the observed remarkable performance.

Interfacial layer suppression in ZrO2/TiN stack structured capacitors via atomic layer deposition

Controlling the formation of interfacial layers in dynamic random-access memory (DRAM) capacitors is crucial because it affects electrical performance, such as increasing the equivalent oxide thickness. This study investigates the formation of an interfacial layer during atomic layer deposition (ALD) of ZrO2 on TiN electrodes and examines its influence on electrical properties. Utilizing O3 and H2O as oxygen sources, we quantitatively identified notable differences in the formation of the interfacial TiOx layer. Using O3 results in a thicker TiOx layer with fewer impurities, which lowers the leakage current, whereas H2O creates a thinner interfacial layer with higher impurity levels, leading to an increased leakage current. To optimize these effects, we developed a two-step ALD process that combines both oxygen sources, reducing the interfacial layer thickness while maintaining low leakage currents. This approach significantly improved the electrical performance of capacitors. Furthermore, similar results were observed for HfO2/TiN systems, suggesting that our findings are broadly applicable to high-k dielectric materials.

Role of electrostatic doping on the resistance of metal and two-dimensional materials edge contacts

In this theoretical study, we compare electrostatically doped metal-transition metal dichalcogenide (TMD) edge-contacts versus substitutionally doped edge-contacts in terms of their contact resistance. Our approach involves the utilization of electrostatic doping achieved by applying back-gate bias to the metal-TMD edge contacts, where carrier injection is primarily governed by the Schottky barrier at the interface. To analyze these contacts, we employ the Wentzel-Kramers-Brillouin (WKB) approximation to calculate the transmission coefficient and use density functional theory (DFT)-derived band structures. We numerically solve the Poisson equation to capture the electrostatic potential. We also account for the impact of the image force using Green's function for the Poisson equation with boundary conditions appropriate to our specific geometry. Our findings reveal that electrostatically doped TMD edge contacts exhibit higher contact resistance compared to impurity-doped edge contacts at equivalent carrier concentrations. At the same time, we find that, among the electrostatically doped edge contacts, a low-κ back-gate oxide in conjunction with low-κ top oxide is preferable in terms of improvement in contact resistance. For instance, in a metal-TMD edge contact scenario involving a monolayer MoS2 as the channel, SiO2 as the infinitely thick top oxide, and a SiO2 back-gate oxide with an equivalent oxide thickness (EOT) of 1nm, we demonstrate that it is possible to achieve an impressively low contact resistance of 50Ωµm when the back-gate bias exceeds or equals 2 V. Published by the American Physical Society 2024

Monolayer Molybdenum Disulfide Transistors with Scaling Dielectric Equivalent Oxide Thickness

Abstract Monolayer molybdenum disulfide (MoS2) demonstrates potential in transistor ultimate scaling, providing a new paradigm for developing next-generation electronic and optoelectronic devices. To enhance device performance, it is necessary to reduce the equivalent oxide thickness (EOT) of the device gate dielectric. In this work, we have successfully reduced the equivalent oxide thickness of the device to 2.3 nm (corresponding to hafnium oxide with a physical thickness of 7 nm), achieving improved device performance, including lowered threshold voltage, enhanced transconductance, and reduced subthreshold swing to 82 mV/dec, demonstrating the superiority of reduced EOT in enhancing device performance.

Ultraflat single-crystal hexagonal boron nitride for wafer-scale integration of a 2D-compatible high-κ metal gate.

Hexagonal boron nitride (hBN) has emerged as a promising protection layer for dielectric integration in the next-generation large-scale integrated electronics. Although numerous efforts have been devoted to growing single-crystal hBN film, wafer-scale ultraflat hBN has still not been achieved. Here, we report the epitaxial growth of 4 in. ultraflat single-crystal hBN on Cu0.8Ni0.2(111)/sapphire wafers. The strong coupling between hBN and Cu0.8Ni0.2(111) suppresses the formation of wrinkles and ensures the seamless stitching of parallelly aligned hBN domains, resulting in an ultraflat single-crystal hBN film on a wafer scale. Using the ultraflat hBN as a protective layer, we integrate the wafer-scale ultrathin high-κ dielectrics onto two-dimensional (2D) materials with a damage-free interface. The obtained hBN/HfO2 composite dielectric exhibits an ultralow current leakage (2.36 × 10-6 A cm-2) and an ultrathin equivalent oxide thickness of 0.52 nm, which meets the targets of the International Roadmap for Devices and Systems. Our findings pave the way to the synthesis of ultraflat 2D materials and integration of future 2D electronics.

Analysis and EOT Scaling on Top‐ and Double‐Gate 2D CVD‐Grown Monolayer MoS2 FETs

Abstract2D layered semiconductors have attracted considerable attention for beyond‐Si complementary metal‐oxide‐semiconductor (CMOS) technologies. They can be prepared into ultrathin channel materials toward ultrascaled device architectures, including double‐gate field‐effect‐transistors (DGFETs). This work presents an experimental analysis of DGFETs constructed from chemical vapor deposition (CVD)‐grown monolayer (1L) molybdenum disulfide (MoS2) with atomic layer deposition (ALD) of hafnium oxide (HfO2) high‐k gate dielectrics (top and bottom). This extends beyond previous studies of DGFETs based mostly on exfoliated (few‐nm thick) MoS2 flakes, and advances toward large‐area wafer‐scale processing. Here, significant improvements in performance are obtained with DGFETs (i.e., improvements in ON/OFF ratio, ON‐state current, sub‐threshold swing, etc.) compared to single top‐gate FETs. In addition to multi‐gate device architectures (e.g., DGFETs), the scaling of the equivalent oxide thickness (EOT) is crucial toward improved electrostatics required for next‐generation transistors. However, the impact of EOT scaling on the characteristics of CVD‐grown MoS2 DGFETs remains largely unexplored. Thus, this work studies the impact of EOT scaling on subthreshold swing (SS) and gate hysteresis using current–voltage (I–V) measurements with varying sweep rates. The experimental analysis and results elucidate the basic mechanisms responsible for improvements in CVD‐grown 1L‐MoS2 DGFETs compared to standard top‐gate FETs.

DC-free Method to Evaluate Nanoscale Equivalent Oxide Thickness: Dark-Mode Scanning Capacitance Microscopy.

This study developed a DC-free technique that used dark-mode scanning capacitance microscopy (DM-SCM) with a small-area contact electrode to evaluate and image equivalent oxide thicknesses (EOTs). In contrast to the conventional capacitance-voltage (C-V) method, which requires a large-area contact electrode and DC voltage sweeping to provide reliable C-V curves from which the EOT can be determined, the proposed method enabled the evaluation of the EOT to a few nanometers for thermal and high-k oxides. The signal intensity equation defining the voltage modulation efficiency in scanning capacitance microscopy (SCM) indicates that thermal oxide films on silicon can serve as calibration references for the establishment of a linear relationship between the SCM signal ratio and the EOT ratio; the EOT is then determined from this relationship. Experimental results for thermal oxide films demonstrated that the EOT obtained using the DM-SCM approach closely matched the value obtained using the typical C-V method for frequencies ranging from 90 kHz to 1 MHz. The percentage differences in EOT values between the C-V and SCM measurements were smaller than 0.5%. For high-k oxide films, DM-SCM with a DC-free operation may mitigate the effect of DC voltages on evaluations of EOTs. In addition, image operations were performed to obtain EOT images showing the EOT variation induced by DC-stress-induced charge trapping. Compared with the typical C-V method, the proposed DM-SCM approach not only provides a DC-free approach for EOT evaluation, but also offers a valuable opportunity to visualize the EOT distribution before and after the application of DC stress.

Spin coating high‐k multicomponent (Al,Ti,V,Zr,Hf)Ox films with sub‐nm EOT for MOS‐based electronic devices

AbstractThe facile spin coating fabrication of high‐dielectric‐constant (high‐k) multicomponent (Al,Ti,V,Zr,Hf)Ox films with an equivalent oxide thickness of ≈0.95 nm and the investigation of their thermal stability and dielectric and electrical properties of the resulting advanced metal–oxide–semiconductor (MOS)‐based electronic devices are reported in this study. Various heating conditions, including drying following spin coating, annealing after drying, and forming gas annealing, were investigated to optimize the quality of the films and reduce film defects. The favorable film‐based MOS devices exhibited robust capacitance–voltage (C–V) and current–voltage (I–V) characteristics with a remarkable k value of approximately 62 at 1 kHz. The thermal stability of the films was affirmed through a rapid thermal annealing treatment at 900°C for 5 s and observation of nondegraded C–V and I–V curves. The electrical performance of the resulting MOS field‐effect transistors (MOSFETs), including a threshold voltage of 0.4 V, an on/off ratio of 106, a saturated mobility of 40.1 cm2 V−1 s−1, and a subthreshold swing of 66.7 mV dec−1, was obtained. Moreover, hole‐ and electron‐trapping measurements through negative and positive gate bias stress instabilities, respectively, indicate the reliable performance of our MOSFETs. Our results imply that solution‐based processes are promising for fabricating fundamental semiconductor devices.

Stabilization of Morphotropic Phase Boundary in Hafnia via Microwave Low‐Temperature Crystallization Process for Next‐Generation Dynamic Random Access Memory Technology

The morphotropic phase boundary (MPB), which arises from the combination of antiferroelectric and ferroelectric phases, demonstrates the highest dielectric constant (κ) compared to other phases. This emphasizes its potential as a leading contender for dielectric films in future dynamic random access memory (DRAM) capacitors. MPB‐based high‐κ materials using hafnia have shown a trade‐off between equivalent oxide thickness (EOT) and leakage current density (Jleak) when the crystallization temperature increases with scaling the thickness. Herein, a microwave annealing (MWA) method that can achieve low‐temperature crystallization below 350 °C is employed. The purpose of this method is to mitigate the trade‐off relationships and achieve the strict criteria of current DRAM capacitors. These criteria include low EOT (less than 4 Å) and Jleak (less than 10−7 A cm−2 at 0.8 V) characteristics. The MWA is capable of relatively low‐temperature annealing by supplying energy to the films through both thermal energy and dipole vibration energy. As a result, a record‐low EOT of 3.76 Å and a low leakage current characteristic of 4.2 × 10−8 A cm−2 at 0.8 V are achieved concurrently. It is confident that the research can be important in addressing the challenges associated with reducing the size of next‐generation DRAM capacitors.

Superionic fluoride gate dielectrics with low diffusion barrier for two-dimensional electronics.

Exploration of new dielectrics with a large capacitive coupling is an essential topic in modern electronics when conventional dielectrics suffer from the leakage issue near the breakdown limit. Here, to address this looming challenge, we demonstrate that rare-earth metal fluorides with extremely low ion migration barriers can generally exhibit an excellent capacitive coupling over 20 μF cm-2 (with an equivalent oxide thickness of ~0.15 nm and a large effective dielectric constant near 30) and great compatibility with scalable device manufacturing processes. Such a static dielectric capability of superionic fluorides is exemplified by MoS2 transistors exhibiting high on/off current ratios over 108, ultralow subthreshold swing of 65 mV dec-1 and ultralow leakage current density of ~10-6 A cm-2. Therefore, the fluoride-gated logic inverters can achieve notably higher static voltage gain values (surpassing ~167) compared with a conventional dielectric. Furthermore, the application of fluoride gating enables the demonstration of NAND, NOR, AND and OR logic circuits with low static energy consumption. In particular, the superconductor-insulator transition at the clean-limit Bi2Sr2CaCu2O8+δ can also be realized through fluoride gating. Our findings highlight fluoride dielectrics as a pioneering platform for advanced electronic applications and for tailoring emergent electronic states in condensed matter.

Low temperature crystallization of atomic-layer-deposited SrTiO3 films with an extremely low equivalent oxide thickness of sub-0.4 nm

Despite SrTiO3(STO) possessing a high dielectric constant, its application as a capacitor dielectric in dynamic random-access memory(DRAM) capacitors faces challenges due to the high-temperature annealing for crystallization, its compositional inhomogeneity, and the high leakage currents of STO films. To address these issues, we employ atomic layer deposition(ALD) of STO films onto Pt substrates at elevated temperatures(340–380 °C). The use of low-reactivity Pt electrodes effectively mitigates the initial growth of excess Sr, ensuring enhanced compositional uniformity along the film growth direction. Coupled with ALD at high temperatures, this approach facilitates the crystallization of STO films in the as-grown state, further enhancing the crystallinity with increasing film thickness. Subsequent low-temperature post-deposition annealing (PDA) at 400 and 500 °C achieves full crystallization. This process results in a remarkable increase in the dielectric constant, reaching approximately 150. Furthermore, the absence of microcracks after PDA, attributed to the formation of adequately dense films, contributes to substantially improved dielectric properties. Consequently, these STO films exhibit an exceptionally low equivalent oxide thickness of 0.34 nm coupled with an ultralow leakage current of 3.7 × 10−8 A/cm2 at an operation voltage of 0.8 V, promising for advancing DRAM capacitors. This study presents a pathway for the sustainable scaling of DRAMs, addressing challenges in ALD-grown STO films.

Tunable EOT Scaling Down to 0. 55 nm for HfO2-Based Gate-Stacks on Ge Substrate by In Situ H2 Plasma Treatment

Abstract We propose a continuous fabrication method for HfO2-based gate stacks on a Ge bulk p-type metal–oxide–semiconductor capacitor (pMOSCAP) with HfGeOx interfacial layer by H2 plasma treatment through in situ plasma-enhanced atomic layer deposition. The electrical characteristics showed that the proper hydrogen plasma treatment could obtain an aggressively scaled equivalent oxide thickness of approximately 0.55 nm and a relatively low gate leakage current of 8 × 10-4 A/cm2 under PMA 500C.

Channel Potential of Bandgap-Engineered Tunneling Oxide (BE-TOX) in Inhibited 3D NAND Flash Memory Strings

In this study, the channel potential of inhibited strings in 3D NAND flash memory using a bandgap-engineered tunneling oxide (BE-TOX) structure is analyzed. The equivalent oxide thickness (EOT) of the structure using BE-TOX was designed to be the same as the conventional 3D NAND flash memory, and the channel potentials of the down coupling phenomenon (DCP) and natural local self-boosting (NLSB) effect were analyzed. As a result, the BE-TOX structure was confirmed to have a higher channel potential in the DCP and NLSB than the conventional structure, making it relatively effective for program disturbance. The main reason for the difference in the channel potential between the BE-TOX and conventional structures is that adjacent cells have different threshold voltages (Vth). When the same program voltage (VPGM) and program time (TPGM) were applied during the program operation, Vth decreased in the BE-TOX structure, which increased the channel potential when DCP and NLSB occurred. Finally, a simulation was conducted by varying the thicknesses of the oxide and nitride in the BE-TOX structure. Despite the EOT being fixed and the thicknesses of both nitride and oxide being varied, the channel potential was affected.

Recent Experimental Breakthroughs on 2D Transistors: Approaching the Theoretical Limit

AbstractSince Si‐based Moore's law is physically limited, 2D semiconductors are proposed as successors to continue shrinking the transistor size for more Moore electronics. However, limited by experimental technology bottlenecks, the theoretical predicted superiorities of the 2D transistors over the state‐of‐the‐art Si transistors have been lacking concrete evidence for a decade. In this review, recent exciting experimental breakthroughs for 2D transistors are presented, including gate length miniaturization to a sub‐1 nm limit, electrode contact optimization to the resistance quantum limit, high‐quality dielectric fabrication with an equivalent oxide thickness to sub‐0.5 nm, novel architecture form (2D fin field‐effect transistor), and back‐end‐of‐line integration of directly grown 2D materials on Si complementary metal‐oxide‐semiconductor circuits. Remarkably, an ultrashort channel, Ohmic contact, ballistic transport, and ultrathin dielectric layer are simultaneously satisfied in the 2D InSe transistor, and device performances approaching the theoretical limit are observed. The measured key figures of merit of the ideal 2D InSe transistor are comparable to or even surpass those of the Si transistors. Finally, the challenges and outlook on more Moore electronics based on 2D transistors are highlighted.

Integration of Ultrathin Hafnium Oxide with a Clean van der Waals Interface for Two-Dimensional Sandwich Heterostructure Electronics.

Integrating high-κ dielectrics with a small equivalent oxide thickness (EOT) with two-dimensional (2D) semiconductors for low-power consumption van der Waals (vdW) heterostructure electronics remains challenging in meeting both interface quality and dielectric property requirements. Here, we demonstrate the integration of ultrathin amorphous HfOx sandwiched within vdW heterostructures by the selective thermal oxidation of HfSe2 precursors. The self-cleaning process ensures a high-quality interface with a low interface state density of 1011-1012 cm-2 eV-1. The synthesized HfOx displays excellent dielectric properties with an EOT of ∼1.5 nm, i.e., a high κ of ∼16, an ultralow leakage current of 10-6 A/cm2, and an impressively high breakdown field of 9.5 MV/cm. This facilitates low-power consumption vdW heterostructure MoS2 transistors, demonstrating steep switching with a low subthreshold swing of 61 mV/decade. This one-step integration of high-κ dielectrics into vdW sandwich heterostructures holds immense potential for developing low-power consumption 2D electronics while meeting comprehensive dielectric requirements.

Variability and high temperature reliability of graphene field-effect transistors with thin epitaxial CaF2 insulators

Graphene is a promising material for applications as a channel in graphene field-effect transistors (GFETs) which may be used as a building block for optoelectronics, high-frequency devices and sensors. However, these devices require gate insulators which ideally should form atomically flat interfaces with graphene and at the same time contain small densities of traps to maintain high device stability. Previously used amorphous oxides, such as SiO2 and Al2O3, however, typically suffer from oxide dangling bonds at the interface, high surface roughness and numerous border oxide traps. In order to address these challenges, here we use 2 nm thick epitaxial CaF2 as a gate insulator in GFETs. By analyzing device-to-device variability for about 200 devices fabricated in two batches, we find that tens of them show similar gate transfer characteristics. Our statistical analysis of the hysteresis up to 175oC has revealed that while an ambient-sensitive counterclockwise hysteresis can be present in some devices, the dominant mechanism is thermally activated charge trapping by border defects in CaF2 which results in the conventional clockwise hysteresis. We demonstrate that both the hysteresis and bias-temperature instabilities in our GFETs with CaF2 are comparable to similar devices with SiO2 and Al2O3. In particular, we achieve a small hysteresis below 0.01 V for equivalent oxide thickness (EOT) of about 1 nm at the electric fields up to 15 MV cm−1 and sweep times in the kilosecond range. Thus, our results demonstrate that crystalline CaF2 is a promising insulator for highly-stable GFETs.

Transferrable Alumina Membranes as High‐Performance Dielectric for Flexible 2D Materials Devices

Abstract2D materials have shown great promise for novel electronic functionality. A common challenge for 2D materials‐based transistors is forming a high‐performance gate terminal due to the challenges of depositing a dielectric of sufficient quality and controllable thickness. Herein the van‐der‐Waals integration of a free‐standing Al2O3 dielectric membrane is demonstrated as a facile, scalable, and powerful gate dielectric. A process is developed that permits the wet transfer of an amorphous alumina layer with a finely adjustable equivalent oxide thickness (EOT) in the single nanometer range. Electrical characterization demonstrates the high breakdown field and low leakage of the dielectric and integration into 2D materials transistors reveals a high performance. The wafer‐scale uniformity of the dielectric membrane permits the formation of large‐scale flexible devices that exhibit good robustness and long‐term stability.

A machine learning approach for optimizing and accurate prediction of performance parameters for stacked nanosheet transistor

In this article, the possibilities of accurate prediction of wide range of parameters and optimizing the same through machine learning (ML) approach have been demonstrated for the multi stacked nanosheet transistor (NSFET). The machine is trained by the generated data of the tedious calibrated technology computer aided (TCAD) simulations. An innovative strategy is employed that combines ML with device simulations. Numerous devices are simulated with different geometric parameters like height, width, length and equivalent oxide thickness of the channel. The input, output, and CV characteristics are extrapolated from the simulation which is predicted by ML models. The DC, Analog and RF parameters are derived with a domain expertise approach. The device parameters are anticipated with actual values by the ML approach. Random forest regression, linear regression, polynomial regression and decision tree regression are employed for the prediction of the performance parameters. Random forest regression models provide significant R2 score with minimal error percentage. It indicates that TCAD-augmented ML can be considered an alternative to device simulation due to its reduction in computational cost. This work can also be treated as a benchmark for accurate prediction of the NSFET.