Increase In Equivalent Oxide Thickness Research Articles

Trap Reduction through O3 Post‐Deposition Treatment of Y2O3 Thin Films Grown by Atomic Layer Deposition on Ge Substrates

AbstractFor Ge‐based metal‐oxide‐semiconductor field‐effect transistor application, high‐k Y2O3 thin films are deposited on Ge single‐crystal substrate using atomic layer deposition. The primary drawbacks of a metal‐oxide‐semiconductor capacitor with pristine Y2O3 are large hysteresis and high leakage current. Through forming gas annealing (FGA), the leakage current can be reduced by approximately three orders of magnitude, along with the reduction of interface trap density. However, there is still a large hysteresis in the capacitance–voltage curves. O3 post‐deposition annealing (OPA) is used to solve the problem. The formation of the YGeOx interfacial layer through OPA and the reduction of the defect level of the Y2O3 thin film effectively decrease the hysteresis, which also decreases the leakage current. Additionally, the hysteresis is 690 mV when only FGA is performed. However, it is further reduced to 260 mV through OPA. Moreover, the remote oxygen scavenging effect using TiN/Pt electrodes prevents an unintentional increase in equivalent oxide thickness (EOT). The 4.7 nm thick Y2O3 film results in an EOT of 1.77 nm and leakage current density of 2.1 × 10−7 A cm−2 (at flat band voltage—1 V) after the OPA.

Effect of microwave annealing on electrical characteristics of TiN/Al/TiN/HfO2/Si MOS capacitors

In this letter, microwave annealing over a wide range of power (300–2700 W) in nitrogen ambient was performed on TiN/Al/TiN/HfO2/Si metal-oxide-semiconductor capacitors. Capacitors with rapid thermal annealing at 500 °C were also fabricated for comparison at the same wafer temperature measured during microwave annealing at 2700 W. For microwave annealed capacitors, key parameters such as equivalent oxide thickness, interface state density, oxide trapped charge, leakage current density, and breakdown voltage were all improved with increasing microwave annealing power. For the capacitor with rapid thermal annealing at 500 °C, diffusion of Al into TiN and growth of the interfacial oxide layer are detected, leading to the shift in flat-band voltage and increase in equivalent oxide thickness, respectively. The results further indicate that it is more effective to remove the charged traps by microwave annealing than by rapid thermal annealing, and the reduction in leakage current density after microwave annealing corresponds to the reduction in charge traps based on a trap-assisted tunneling model. With no trade-off relationship between the electrical characteristics and no undesired effect such as diffusion of species, microwave annealing demonstrates great potential for the post-metallization annealing process for the high-k/metal gate structure.

Investigation on the negative bias illumination stress-induced instability of amorphous indium-tin-zinc-oxide thin film transistors

The quantitative analysis of mechanism on negative bias illumination stress (NBIS)-induced instability of amorphous indium-tin-zinc-oxide thin-film transistor (TFT) was suggested along with the effect of equivalent oxide thickness (EOT) of gate insulator. The analysis was implemented through combining the experimentally extracted density of subgap states and the device simulation. During NBIS, it was observed that the thicker EOT causes increase in both the shift of threshold voltage and the variation of subthreshold swing as well as the hump-like feature in a transfer curve. We found that the EOT-dependence of NBIS instability can be clearly explicated with the donor creation model, in which a larger amount of valence band tail states is transformed into either the ionized oxygen vacancy VO2+ or peroxide O22− with the increase of EOT. It was also found that the VO2+-related extrinsic factor accounts for 80%–92% of the total donor creation taking place in the valence band tail states while the rest is taken by the O22– related intrinsic factor. The ratio of extrinsic factor compared to the total donor creation also increased with the increase of EOT, which could be explained by more prominent oxygen deficiency. The key founding of our work certainly represents that the established model should be considered very effective for analyzing the instability of the post-indium-gallium-zinc-oxide (IGZO) ZnO-based compound semiconductor TFTs with the mobility, which is much higher than those of a-IGZO TFTs.

Thickness and Post-annealing Effects of the Sputtered La-Capping Layer Inserted between the TiN Gate and Hf-Based Dielectrics

We investigated effects of the sputtered La-capping layer inserted between TiN and Hf-based dielectrics, HfO2 and HfSiO4/HfO2, mainly focusing on effective work function (EWF) and equivalent oxide thickness (EOT) changes by modulation of its thickness and post-metal annealing (PMA). The use of thin La capping up to 5 Å showed a linear flatband voltage (V(FB)) shift of -60 mV/Å, regardless of gate dielectrics. However, with the increase of the La thickness, a slight increase in EOT was observed for HfO2, whereas a negligible change in EOT was shown for the HfSiO4/HfO2 bilayer. It might be ascribed to the facile La oxidation, which acts as an additional oxide layer on both of the gate dielectrics. Meanwhile, high-temperature PMA exhibited slight reduction in V(FB) as well as an EOT increase for both of the Hf-based dielectrics. On the basis of X-ray photoelectron spectroscopy (XPS) results, the reason for the slightly decreased EWF resulted from two competing dipoles formed by movements of oxygen vacancies (V(O)) and La atoms during the PMA. Additionally, oxygen affinity and diffusion of the La-capping layer on both of the gate dielectrics are further discussed in conjunction with thermodynamic analyses, and thereby, schematic energy band diagrams were proposed by taking into account competing dipole layers by VO movement and La diffusion.

Gate-first n-MOSFET with a sub-0.6-nm EOT gate stack

Self-aligned and gate-first TiLaO/La2O3n-MOSFET shows an equivalent oxide thickness (EOT) of 0.57nm.Small EOT can be reached using La silicate to suppress the formation of low-? defective interface.This low-EOT MOSFET exhibits the potential to integrate with current CMOS process. We report a self-aligned and gate-first TiLaO/La2O3n-MOSFET with an equivalent oxide thickness (EOT) of 0.57nm and low threshold voltage (Vt) of 0.3V. The small EOT MOSFET can be reached using La-based interfacial layer with strong bond enthalpy (La-O, 799kJ/mol) to suppress the formation of defect-rich low- interfacial layer and simultaneously block titanium atom inter-diffusion to avoid additional EOT increase. This gate-first low-EOT MOSFET exhibits the potential to integrate with current CMOS process.

EOT of 0.62 nm and High Electron Mobility in La-silicate/Si Structure Based nMOSFETs Achieved by Utilizing Metal-Inserted Poly-Si Stacks and Annealing at High Temperature

This paper reports on the control of the direct-contact La-silicate/Si interface structure with the aim of achieving scaled equivalent oxide thickness (EOT) and small interface state density. The interface state density at the direct-contact La-silicate/Si interface is found to be reduced to <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$\hbox{1.6} \times \hbox{10}^{11}\ \hbox{cm}^{-2}\hbox{eV}^{-1}$</tex></formula> by annealing at 800 <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$^{\circ}\hbox{C}$</tex></formula> for 30 min in forming gas ambient, whereas excess silicate reaction concurrently induced a significant increase in EOT. By utilizing metal-inserted poly-Si (MIPS) stacks and their annealing at high temperature, the increase in EOT is drastically suppressed. At the same time, a superior interfacial property is obtained because the Si layer in the MIPS stacks prevents the excess oxygen diffusion from the atmosphere during the annealing process. As a result, the effective electron mobility of 155 <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$\hbox{cm}^{2}/\hbox{V}\cdot{s}$</tex></formula> at 1 MV/cm and an EOT of 0.62 nm are successfully achieved by utilizing direct-contact La-silicate/Si structure. This result is comparable with the recorded effective electron mobility achieved by utilizing Hf-based oxides/Si structure. This demonstrates the advantage of our proposed method to realize the scaled EOT with a superior interfacial property for state-of-the-art metal–oxide–semiconductor field-effect transistors.

Compensation of oxygen defects in La-silicate gate dielectrics for improving effective mobility in high-k/metal gate MOSFET using oxygen annealing process

Oxygen incorporation for compensation of oxygen defects is investigated with La-silicate dielectrics in directly contacted with the Si substrate. The amount of oxygen is controlled by the temperature of annealing in oxygen atmosphere (oxygen annealing) and the thickness of the gate electrode. The positive shift in flatband voltage ( V FB) by oxygen incorporation is an experimental evidence for defects compensation in La-silicate dielectrics. Optimum oxygen annealing provides the V FB shift toward positive direction without increasing equivalent oxide thickness (EOT). Although the oxygen annealing degrades the interfacial property at La-silicate/Si interface, subsequent forming gas annealing (FGA) can recover the interfacial property. It is experimentally revealed that the positive V FB shift of La-silicate dielectrics is stable even after subsequent FGA. The supplied oxygen in La-silicate is expected to maintain even after reducing process. Movement of Fermi level toward the Si valence band edge caused by oxygen incorporation is successfully observed by XPS. Moreover, no chemical reaction between La-silicate and Si substrate by oxygen annealing are confirmed from TEM observation and analyses of X-ray photoelectron spectra. It is experimentally demonstrated that effective hole mobility can be improved without increase in EOT by combination of oxygen annealing and FGA.

Detrimental Hf penetration into TiN gate electrode and subsequent degradation in dielectric properties of HfSiO high-k film

Hafnium penetration through the TiN gate electrode as thick as 10 nm is detected in the TiN/HfSiO/SiO2 gate stacks after high-temperature annealing by using x-ray photoelectron spectroscopy. The Hf outdiffusion, showing TiN thickness dependence, is revealed to cause permittivity lowering of the pristine HfSiO high-k layer, which accelerates the equivalent oxide thickness increase and degrades the dielectric properties. In contrast, such diffusion is suppressed by adopting metal inserted polycrystalline silicon stack (MIPS) structure. Our further experiments indicate that the SiO2 regrowth during high-temperature annealing, which is hampered in MIPS structure, triggers the adverse Hf diffusion.

Impact of Thermally Induced Structural Changes on the Electrical Properties of TiN/HfLaSiO Gate Stacks

Thermally induced structural changes in TiN/Hf(La)SiO gate stacks were investigated by back-side X-ray photoelectron spectroscopy (XPS) and near edge X-ray absorption fine structure (NEXAFS). A distinct correlation between bottom oxide growth and an increase in equivalent oxide thickness (EOT) was confirmed under high-temperature annealing at over 850 °C regardless of La content. Back-side XPS also revealed that oxygen and nitrogen diffusion occurs, forming partially oxidized TiON layers at a metal/high-k interface under moderate annealing temperatures of approximately 600 °C, and that annealing at over 750 °C leads to the reduction of the oxide phase and produces a thinner inter-layer with a clear Ti–N bond feature. Moreover, with an increase in annealing temperature, a change in the local atomic configuration in the HfLaSiO dielectric layer was identified from oxygen K-edge spectra. This structural change induced by thermal reaction can be considered as a possible cause of the Vth instability of La-incorporated high-k gate stacks. On the basis of these findings on structural changes, the physical origins of the effective work function modulation of the gate stacks are discussed in detail.

Impact of Thermally Induced Structural Changes on the Electrical Properties of TiN/HfLaSiO Gate Stacks

Thermally induced structural changes in TiN/Hf(La)SiO gate stacks were investigated by back-side X-ray photoelectron spectroscopy (XPS) and near edge X-ray absorption fine structure (NEXAFS). A distinct correlation between bottom oxide growth and an increase in equivalent oxide thickness (EOT) was confirmed under high-temperature annealing at over 850 °C regardless of La content. Back-side XPS also revealed that oxygen and nitrogen diffusion occurs, forming partially oxidized TiON layers at a metal/high-k interface under moderate annealing temperatures of approximately 600 °C, and that annealing at over 750 °C leads to the reduction of the oxide phase and produces a thinner inter-layer with a clear Ti–N bond feature. Moreover, with an increase in annealing temperature, a change in the local atomic configuration in the HfLaSiO dielectric layer was identified from oxygen K-edge spectra. This structural change induced by thermal reaction can be considered as a possible cause of the Vth instability of La-incorporated high-k gate stacks. On the basis of these findings on structural changes, the physical origins of the effective work function modulation of the gate stacks are discussed in detail.

The Importance of Moisture Control for EOT Scaling of Hf-Based Dielectrics

The role of moisture in atomic-layer-deposited (ALD) and dielectrics on equivalent oxide thickness (EOT) scaling is investigated in gate-first devices with physical-vapor-deposited TaN gates. By reducing the amount of present in the gate stack, the EOT increase during high-temperature spike annealing is reduced from . This was achieved by a premetallization degas at for . The origin of this improvement lies in the elimination of -related reoxidation of the interfacial . By means of temperature-programmed desorption measurements, it is found that the majority of the is desorbed between 200 and with activation energies between and . Furthermore, the concentration is dependent on the Hf concentration and nitridation. Non-nitrided with adsorbs twice as much as . Correspondingly, a significantly larger EOT increase is observed for with as compared to . In HfSiON, the desorbed concentration is independent of [Hf]. Finally, a strong metal dependency on the EOT regrowth is observed. With ALD TiN, the EOT increase after thermal treatment is found to be independent of the degas condition at .

Improvement of Device Characteristics for TiN Gate p-Type Metal–Insulator–Semiconductor Field-Effect Transistor with Al2O3-Capped HfO2 Dielectrics by Controlling Al2O3 Diffusion Annealing Process

We have investigated the effect of postdeposition annealing (PDA) of Al2O3-capped HfO2 films on the flatband voltage (Vfb) shift and threshold voltage (Vt) variation in TiN gate p-type metal–insulator–semiconductor field-effect transistors (pMISFETs). We found that optimizing the PDA conditions to diffuse Al2O3 into the HfO2 films is a key factor for controlling Vfb, and high-temperature PDA immediately after Al2O3 deposition induces a positive Vfb shift. Additional Vt variation was observed when the PDA temperatures after Al2O3 deposition were 850 and 950 °C. In contrast, a higher temperature PDA at 1050 °C after Al2O3 deposition can suppress Vt variation to almost the same level as that obtained in a HfO2 film without an Al2O3-cap layer, although the equivalent oxide thickness (EOT) increases. We also found that superior device characteristics, such as low Vt, suppression of Vt variation, and suppression of EOT increase, were obtained by performing PDA before Al2O3 deposition.

Theoretical models for work function control (Invited Paper)

We have studied Fermi level pinning (FLP) of Hf-based high- k gate stacks based on thermodynamics based on an O vacancy model. Our study shows that FLP cannot be avoided when the system is under thermal equilibrium. O exposure to aim O vacancy elimination is not effective, since O vacancy elimination condition is equivalent to the Si substrate oxidation which leads to the increase in Equivalent oxide thickness (EOT). We also studied the mechanism of FLP induced by the reduction with H 2 anneal. FLP with H 2 anneal is governed by the O vacancy annihilation reaction by reducing SiO 2 interface layer. Based on these considerations, we propose some recipes for obtaining band-edge-work-function metals.

Electrical Characteristics of Metal/High-k MOS Devices Using Effective Oxygen Control for Sub-1nm EOT

In this study, we have studied the mechanism of equivalent oxide thickness (EOT) increase after annealing using oxygen diffusion model from W gate electrode. It has been revealed that proper thickness W insertion into metal/high-k interface could depress EOT increase after post metallization annealing (PMA) and achieve small CV hysteresis.

Electrical, structural, and chemical properties of HfO2 films formed by electron beam evaporation

High dielectric constant hafnium oxide films were formed by electron beam (e-beam) evaporation on HF last terminated silicon (100) wafers. We report on the influence of low energy argon plasma (∼70 eV) and oxygen flow rate on the electrical, chemical, and structural properties of metal-insulator-silicon structures incorporating these e-beam deposited HfO2 films. The use of the film-densifying low energy argon plasma during the deposition results in an increase in the equivalent oxide thickness (EOT) values. We employ high resolution transmission electron microscopy (HRTEM), x-ray photoelectron spectroscopy (XPS), and medium energy ion scattering experiments to investigate and understand the mechanisms leading to the EOT increase. We demonstrate very good agreement between the interfacial silicon oxide thicknesses derived independently from XPS and HRTEM measurements. We find that the e-beam evaporation technique enabled us to control the SiOx interfacial layer thickness down to ∼6 Å. Very low leakage current density (&amp;lt;10−4 A/cm2) is measured at flatband voltage +1 V into accumulation for an estimated EOT of 10.9±0.1 Å. Based on a combined HRTEM and capacitance-voltage (CV) analysis, employing a quantum-mechanical CV fitting procedure, we determine the dielectric constant (k) of HfO2 films, and associated interfacial SiOx layers, formed under various processing conditions. The k values are found to be 21.2 for HfO2 and 6.3 for the thinnest (∼6 Å) SiOx interfacial layer. The cross-wafer variations in the physical and electrical properties of the HfO2 films are presented.

Modulation of TiSiN effective work function using high-pressure postmetallization annealing in dilute oxygen ambient

To increase the effective work function of a W∕TiSiN metal gate stack without an equivalent oxide thickness (EOT) increase, we developed a process for high-pressure postmetallization annealing in diluted oxygen ambient. Compared with annealing in an atmospheric pressure, oxygen postmetallization annealing (PMA) in a high-pressure ambient (1–20atm) showed further modulation of the effective work function (4.6–4.8eV) without an EOT increase. These differences can be attributed to total amounts of oxygen supplied to gate stack system. Additionally, the origin of EOT increase after the oxygen PMA was attributed to oxidation of the capping metal.

Improved Electrical Properties of ALD $\hbox{Hf}_{x} \hbox{Zr}_{1 - x}\hbox{O}_{2}$ Dielectrics Deposited on Ultrathin PVD Zr Underlayer

The impact of ultrathin metal underlayer on physical and electrical properties of Hf <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> _x </i> Zr <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1-</sub> <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> _x </i> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> (x=~0.4) after high-temperature processing was investigated. An ~5-Aring Zr, ~5-Aring Hf, ~10-Aring Hf metal layer was sputter deposited prior to Hf <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> _x </i> Zr <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1-</sub> <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> _x </i> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> growth. Cross-sectional transmission electron microscopy and secondary ions mass spectrometry analysis confirmed no Zr or Hf silicide formation between the high- <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</i> film and Si substrate even after 1000degC processing. No significant increase in equivalent oxide thickness or gate leakage current is observed on devices with metal underlayer. Furthermore, devices with a 5-Aring-thick Zr underlayer exhibited lower threshold voltage, higher mobility, and improved charge trapping characteristics.

Analysis of Interface States in LaSixOy Metal–Insulator–Semiconductor Structures

Using a comprehensive model to simulate interface state effects on metal–insulator–semiconductor (MIS) device in capacitance–voltage (C–V) behavior, interface properties of LaSixOy gate dielectric MIS structures were analyzed. Under low temperature (400 °C) processing conditions amenable to low (0.6 nm) equivalent oxide thickness (EOT), LaSiO-based MIS capacitors on n- and p-type substrates have a high density localized interface state. The peak densities of this localized state for MIS devices on n- and p-type substrates are (2.0–2.5)×1013 and 2.5×1012 cm-2 eV-1, respectively, lying deep in the Si bandgap (within 0.1 eV of midgap). Positive fixed charge density is derived as in the range of 1013 cm-2 and is found to be distributed close to the interface region. In the case of the p-type MIS capacitor, positive fixed charge and positively charged interface states shift the C–V curve in the negative direction. Interface states in the n-type MOS capacitor capture electrons, compensating for the positive fixed charge and positively charged interface states. Thus less shift of the C–V curve is observed, compared to the p-type case. Interface state and fixed charge densities drastically reduce by raising post annealing temperature, to <1012 cm-2 eV-1 on n-type Si, but with concurrent EOT increase. Forming gas annealing (FGA) is effective for reducing the localized interface state density, but only when the temperature is 600 °C or higher. Results point to a need to minimize defect densities during or immediately after dielectric deposition. The high levels of positive defect states warrant further detailed investigation of the charge trapping characteristics of these dielectrics, as La-containing dielectrics are important for threshold voltage control for metal–oxide–semiconductor field effect transistor (MOSFET) devices.

Thermal stability of rare-earth based ultrathin Lu2O3 for high-k dielectrics

Lu 2 O 3 thin film was deposited on n-type (100) Si substrates using pulsed laser deposition. A k value of 15.95 with an equivalent oxide thickness (EOT) of 1.10nm and a current density of 2.6×10−5A∕cm2 at +1V accumulation bias is achievable for the 4.5nm thick Lu2O3 thin film deposited at room temperature after postdeposition annealing at 600°C in oxygen ambient. Annealing a similar sample at 900°C caused the EOT and leakage current density to increase to 1.68nm and 1×10−4A∕cm2, respectively. High resolution transmission electron microscopy analysis has shown that Lu2O3 film remains amorphous at high temperature annealing at 900°C. An x-ray reflectivity analysis on a separately prepared sample with lower annealing temperature (800°C) suggested a formation of Lu-based silicate layer. It is believed that the formation of low-k silicate layer may have contributed to the observed increase in EOT and the reduction in the k value.

Achieving Conduction Band-Edge Effective Work Functions by $\hbox{La}_{2}\hbox{O}_{3}$ Capping of Hafnium Silicates

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> Conduction band-edge effective work functions (<formula formulatype="inline"><tex>$\phi_{m, {\rm eff}}$</tex> </formula>) are demonstrated with <formula formulatype="inline"><tex>$\hbox{TaC}_{x}$</tex></formula> and TiN by means of <formula formulatype="inline"><tex>$\hbox{La}_{2}\hbox{O}_{3}$</tex></formula> capping of <formula formulatype="inline"><tex>$\hbox{HfSiO}_{x}$</tex></formula> in a gate-first process flow with CMOS-compatible thermal budget. With <formula formulatype="inline"><tex>$\hbox{TaC}_{x}$</tex></formula>, a 10- <formula formulatype="inline"><tex>$\hbox{\bf \AA}$</tex></formula>-thick <formula formulatype="inline"><tex>$ \hbox{La}_{2}\hbox{O}_{3}$</tex></formula> cap results in a <formula formulatype="inline"><tex>$\phi_{m, {\rm eff}}$ </tex></formula> of 3.9 eV with a low equivalent oxide thickness (EOT) increase (1–2 <formula formulatype="inline"><tex>$\hbox{\bf \AA}$</tex></formula>) and unaffected electron mobility. With TiN, non-nitrided <formula formulatype="inline"><tex>$\hbox{La}_{2}\hbox{O}_{3}$</tex></formula> capping results in a smaller <formula formulatype="inline"><tex>$\phi_{m, {\rm eff}}$</tex></formula> reduction at a larger EOT increase, while with post-cap nitridation, the TiN <formula formulatype="inline"><tex>$\phi_{m, {\rm eff}}$</tex></formula> is lower at a smaller EOT increase. Results show that the choice of metal and nitridation conditions have significant effects on <formula formulatype="inline"><tex>$\hbox{La}_{2}\hbox{O}_{3}$</tex></formula> capped stacks. </para>