Equivalent Input Noise Charge Research Articles

An optical fiber-based flexible readout system for micro-pattern gas detectors

This paper presents an optical fiber-based readout system that is intended to provide a general purpose multi-channel readout solution for various Micro-Pattern Gas Detectors (MPGDs). The proposed readout system is composed of several front-end cards (FECs) and a data collection module (DCM). The FEC exploits the capability of an existing 64-channel generic TPC readout ASIC chip, named AGET, to implement 256 channels readout. AGET offers FEC a large flexibility in gain range (4 options from 120 fC to 10 pC), peaking time (16 options from 50 ns to 1 us) and sampling freqency (100 MHz max.). The DCM contains multiple 1 Gbps optical fiber serial link interfaces that allow the system scaling up to 1536 channels with 6 FECs and 1 DCM. Further scaling up is possible through cascading of multiple DCMs, by configuring one DCM as a master while other DCMs in slave mode. This design offers a rapid readout solution for different application senario. Tests indicate that the nonlinearity of each channel is less than 1%, and the equivalent input noise charge is typically around 0.7 fC in RMS (root mean square), with a noise slope of about 0.01 fC/pF. The system level trigger rate limit is about 700 Hz in all channel readout mode. When in hit channel readout mode, supposing that typically 10 percent of channels are fired, trigger rate can go up to about 7 kHz. This system has been tested with Micromegas detector and GEM detector, confirming its capability in MPGD readout. Details of hardware and FPGA firmware design, as well as system performances, are described in the paper.

GASTONE64: A new front-end ASIC for the cylindrical GEM Inner Tracker of KLOE-2 experiment at [formula omitted

GASTONE64 (Gem Amplifier Shaper Tracking ON Events) is a novel 64-channel mixed analog-digital ASIC developed to readout the cylindrical GEM inner tracking detector of the KLOE-2 apparatus at the e+e−DAΦNE collider. It has been designed in the CMOS 0.35μm technology and each analog channel is made of preamplifier, shaper and discriminator. The expected input charge ranges between few fC up to 40fC, the charge sensitivity is 16mV/fC while the equivalent input noise charge (ENC) is 800e−+40e−/pF. The discriminated signals are read-out using a 100MBit/s LVDS serial data link. The power consumption is about 6mW/channel.

Very fast front end ASIC associated with multi-anode PMTs for a scintillating-fibre beam hodoscope

For developing a scintillating-fibre beam monitor, wehave designed a front-end 16-Channel readout chip (version 2) to beassociated with Multi-anode photomultipliers Ma-PMTs (Hamamatsu H8500) in a0.35 μm BiCMOS process. Each channel of the ASIC consists of one inputcurrent conveyor driving separately a current comparator for signal eventdetection and a charge-sensitive amplifier (CSA) for signal chargemeasurement. The ASIC has brought significant improvements compared to itsprevious version: larger input dynamic range (53 dB against 33 dB), lowerpower consumption (11 mW/channel instead of 22 mW/channel under a 3.3-Vsupply), lower noise (4 fC versus 19 fC in Equivalent input Noise Charge, orENC) and a better phase margin for optimizing stability and speed. Thisdedicated chip had been used in a beam test at HIT (Heidelberg Ion-BeamTherapy Center). System testing has shown achievements of 1 mm spatialresolution (size of the scintillating fibers) and a 4 MHz count rate. Themain limitation comes from the Ma-PMTs which saturates at such a frequency.The ASIC operates normally with satisfied performances.

Design of a monolithic CMOS sensor for high efficiency neutron counting

The development of CMOS Pixel Sensors (CPS) for charged particles detection had led to promising applications for dosimetry. Based on our previous studies on the detection of fast and thermal neutrons with a CMOS sensor originally designed for particle tracking in high energy physics, a dedicated integrated CMOS sensor for efficient neutron counting is presented. This sensor has been designed and fabricated in a 0.35μm CMOS process. It is a low noise, low power consumption sensor with a sensitive area of 6.55mm2 and a digital output. The test results indicate that it is suitable for neutron detection, thanks to its equivalent input noise charge of less than 400e−, and a 20kHz detection frequency. In this paper the prototype is presented for both its circuit design and test results.

Development of a Low-Noise Front-End Readout Chip Integrated With a High-Resolution TDC for APD-Based Small-Animal PET

This paper presents the design of a low-noise multi-channel front-end readout chip integrated with a high-resolution TDC. It is foreseen to be used as front-end readout electronics of Avalanche Photo Diodes (APD) dedicated to a small animal Positron Emission Tomography (PET) system. The architecture of the chip is reported. Two prototype chips, a ten-channel front-end chip and a three-channel high-resolution TDC, have been designed in AMS 0.35 μm CMOS technology. A low-noise charge-sensitive amplifier (CSA) and a shaper are integrated in each channel of the front-end chip. The proposed CSA performs a compensation of the 40 nA dark current coming from the detector. An equivalent input noise charge of 275 e- + 10 e-/pF (rms) has been obtained from test. The TDC chip is based on coarse-fine two-level conversion scheme. In the coarse conversion, a 10-bit counter is employed to achieve a wide range. Meanwhile, the time interpolation using an array of delay-locked loops is proposed for fine conversion. The measured time range is 10 μs. The bin size has been achieved from 71 ps to 142 ps with a reference clock from 100 MHz to 50 MHz.

Design and characterization of a multi-channel front-end readout ASIC with low noise and large dynamic input range for APD-based PET imaging

This paper represents the design of a low-noise, wide band multi-channel readout integrated circuit (IC) used as front-end readout electronics of Avalanche Photo Diodes (APD) dedicated to a small animal Positron Emission Tomography (PET) system. The first 10-channel prototype chip (APD_Chip) of the analog parts has been designed and fabricated in a 0.35-μm CMOS process. Every channel of the APD_Chip includes a charge-sensitive preamplifier (CSA), a CR-(RC)2 shaper, and an analog buffer. In each channel, the CSA reads charge signals (10 bits dynamic range) from an APD array having 10 pF of capacitance per pixel. A linearized degenerated differential pair which ensures high linearity in all dynamical range is used as the high feedback resistor for preventing pile up of signals. The designed CSA has the capability of compensating automatically up to 200 nA leakage current from the detector. The CR-(RC)2 shaper filters and shapes the output signal of the CSA. An equivalent input noise charge obtained from test is 275 e? + 10 e?/pF. In this paper the prototype is presented for both its circuits design and its test results.

Design of a Multi-Channel Front-End Readout ASIC With Low Noise and Large Dynamic Input Range for APD-Based PET Imaging

This paper represents the design of a low-noise, wide band multi-channel readout integrated circuit (IC) used as front end readout electronics of avalanche photo diodes (APD) dedicated to a small animal positron emission tomography (PET) system. The first ten-channel prototype chip (APD-Chip) of the analog parts has been designed and fabricated in a 0.35 μm CMOS process. Every channel of the APD_Chip includes a charge-sensitive preamplifier (CSA), a CR-(RC)2 shaper, and an analog buffer. In a channel, the CSA reads charge signals (10 bits dynamic range) from an APD array having 10 pF of capacitance per pixel. A linearized degenerated differential pair which ensures high linearity in all dynamical range is used as the high feedback resistor for preventing pile up of signals. The designed CSA has the capability of compensating automatically up to 200 nA leakage current from the detector. The CR-(RC)2 shaper filters and shapes the output signal of the CSA. An equivalent input noise charge obtained from test is 275 e -+ 10 e-/pF. In this paper the prototype is presented for both its theoretical analysis and its test results.

A charge-sensitive amplifier associated with APD or PMT for 511 keV, photon-pair detection

For positron emission tomography scanners requiring 511 keV two-photon detection, we present a charge-sensitive amplifier (CSA) to be associated with an avalanche photodiode (APD) or photo-multiplier tube (PMT). It is a two-stage structure. The input stage consists of a folded-cascode fully differential circuit and a common-mode feedback (CMFB) circuit. Feedforward technique is implemented to enhance frequency performance. The output stage employs complementary source followers. The amplifier has been designed in a 0.35-μm BiCMOS process with analysis and optimization of noise and speed performances. Testing of fabricated prototypes has given results in good agreement with post-layout simulated ones. The evaluated characteristics of the circuit are: 26 ns peaking time for pulsed stimulus, 2000 electron equivalent input noise charge (ENC) for a detector capacitance up to 80 pF and 136 mW power consumption from a 3.5-V supply.

A low-noise, low stored energy preamplifier for high-voltage radiation detectors

A low-noise preamplifier with very low stored energy has been developed for use with high-voltage radiation detectors. The input will withstand 3.5 kV, has a physical capacitance to ground of 200 pF, and an effective “small signal” capacitance of ∼30 nF. When connected to a high-voltage electrode, the low physical input capacitance to ground limits the stored energy and helps protect the detector system should an accidental discharge occur. The large effective input capacitance minimizes the voltage transient on the high-voltage electrode that occurs during charge collection, thus lowering the charge that is capacitively coupled to surrounding electrodes from this transient. If the surrounding electrodes are part of a position sensing readout, then this coupled charge is distributed uniformly among readout electrodes and is added to the signal charge induced by the motion of charge carriers containing position information. This introduces an error into the position centroid calculation. The preamplifier presented here greatly reduces this effect while keeping stored energy low. Equivalent input noise charge (ENC) is 256 electrons RMS when using a 250 ns unipolar shaping amplifier and no input capacitance. With input capacitances of 18 and 223 pF, the noise increases to 361 and 1766 electrons RMS, respectively.

A functionally reconfigurable detector head for scintimammography

A novel prototype detector for scintimammography is presented. The detector is built according to a modular strategy. Each module is composed of an array of p–i–n diodes, coupled to a CsI(Tl) scintillator and to mixed-mode ASICs with self-triggering, sparsifying, A/D conversion and bidirectional serial data I/O transfer capabilities. The front-end electronics exhibits good performance in terms of equivalent input noise charge (ENC<100 e − rms). Digital signals are routed out so that each module can be attached to a main board with an FPGA for overall detector management. PC-based supervision of the detector is accomplished using a LabVIEW graphical user interface.

SVX4: a new deep-submicron readout IC for the Tevatron collider at Fermilab

SVX4 is the new silicon strip readout IC designed to meet the increased tolerance requirements for Run IIb at the Tevatron collider. Devices have been fabricated, tested, and approved for production. The SVX4 is a technology migration of the SVX3D currently in use by CDF. Whereas SVX3D was fabricated in a 0.8-/spl mu/m radiation-hard process, SVX4 was fabricated in a standard 0.25-/spl mu/m mixed-signal CMOS technology using the radiation tolerant by design transistor topologies devised by the CERN RD49 collaboration. The specific cell layouts include digital cells developed by the ATLAS Pixel group, and full-custom analog blocks. Unlike its predecessors, the new also includes the necessary features required for generic use by both the CDF and D0 experiments at Fermilab. Performance of the IC includes >20 MRad total dose tolerance, and /spl sim/2000 e-rms equivalent input noise charge with 40-pF input capacitance, when sampled at 132-ns period with an 80-ns preamp risetime. At the nominal digitize/readout rate of 106/53 MHz, the 9 mm/spl times/6.3 mm die dissipates /spl sim/2 mW/channel average at 2.5 V. A review of typical operation, details of the conversion process, and performance measurements are covered.

Multichannel mixed-mode IC for digital readout of silicon strip detectors

The design of a mixed mode 64-channel ASIC for digital readout of silicon strip detectors used in X-ray imaging applications is presented. The design is implemented in a 0.8 μm CMOS n-well epi-type substrate technology. The single channel consists of a charge sensitive preamplifier, a shaping amplifier, a discriminator and a pseudo-random 20-bit counter. In addition to the 64-channel core which is responsible for signal processing and data storage, the IC comprises additional blocks like an internal calibration circuit, internal DACs and a command decoder which governs communication of the IC with the external world. Those blocks have been designed keeping in mind testability features and using the chips for building multi-chip modules. The equivalent input noise charge measured at room temperature for a detector capacitance of 2.5 pF and signal integration time of 0.7 μs is 167 e − rms. The average power dissipation is 2.5 mW/channel. The channel-to-channel offset spread referred to the input is only 28 e − rms, while the standard deviation of gain spread is 0.5% of the mean value. The chip occupies area of 2.8×6.5 mm 2.

Summary of thermal, shot and flicker noise in detectors and readout circuits

The techniques for calculating noise in electronic circuits are well known (P. Seller, Nucl. Instr. and Meth. A 408 (1998) 603). These have been used here to tabulate the output noise variance and the Equivalent input Noise Charge (ENC) for time-invariant filter circuits often used for reading out detector systems. This is followed by some comparisons of the performance of different filters.

Readout electronics in large detector matrix for soft X-ray in medical applications

MACARENA is a full custom analog–digital CMOS integrated circuit (IC) designed for single X-ray photon detection for digital mammography. The IC is a complete front-end channel designed to be the main cell that will be used for a modular building of a large array of data acquisition channels. The channel consists of a low noise charge sensitive amplifier (CSA), a shaper, a discriminator and a 13 bit counter-shifter. The main characteristics of the IC are (1)channel power consumption of 80μW; (2)minimum signal discriminated of about 400 electrons; (3)the equivalent input noise charge (E.N.C) at shaper output is 150e+3*Cd[pF] r.m.s; (4)compact design of a 13bit asynchronous ripple counter reconfigurable in to a shift register and (5)single power supply. The front-end was designed to operate, with our specific Si matrix detector, in the photon energy range from 10 to 100keV, the range of medical interest.

A monolithically integrated detector-preamplifier on high-resistivity silicon

A monolithically integrated detector-preamplifier on high-resistivity silicon has been designed, fabricated, and characterized. The detector is a fully depleted p-i-n diode, and the preamplifier is implemented in a depletion-mode PMOS process which is compatible with detector processing. The amplifier is internally compensated, and the measured gain-bandwidth product is 30 MHz with an input-referred noise of 15 nV/ square root Hz in the white-noise regime. Measurements with an Am/sup 241/ radiation source yield an equivalent input noise charge of 800 electrons at 200 ns shaping time for a 1.4 mm/sup 2/ detector with on-chip amplifier in an experimental setup with substantial external pickup.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

An LSI technology fully compatible EAROM cell : Guido Torelli. Alta Freq., LI (6), 345 (November–December 1982)

The design of a mixed mode 64-channel ASIC for digital readout of silicon strip detectors used in X-ray imaging applications is presented. The design is implemented in a 0.8 μm CMOS n-well epi-type substrate technology. The single channel consists of a charge sensitive preamplifier, a shaping amplifier, a discriminator and a pseudo-random 20-bit counter. In addition to the 64-channel core which is responsible for signal processing and data storage, the IC comprises additional blocks like an internal calibration circuit, internal DACs and a command decoder which governs communication of the IC with the external world. Those blocks have been designed keeping in mind testability features and using the chips for building multi-chip modules. The equivalent input noise charge measured at room temperature for a detector capacitance of 2.5 pF and signal integration time of 0.7 μs is 167 e− rms. The average power dissipation is 2.5 mW/channel. The channel-to-channel offset spread referred to the input is only 28 e− rms, while the standard deviation of gain spread is 0.5% of the mean value. The chip occupies area of 2.8×6.5 mm2.

An Integrated Amplifier and Sample-and-Hold Analog Multiplexer Module

The integrated amplifier and sample-and-hold analog multiplexer-ISHAM, is a proportional wire chamber analog readout module. It includes the front-end am plifier, the gated integrator and the sample-and-hold analog multiplexer. A density of 24 channels per module was achieved in a nonstandard multilayer P.C. board. Besides the above mentioned functions, the module provides: the control circuits for the Read-In and the Read-Out of the wire signals, the control circuits for the calibration of the 24 amplifiers, and the neutral trigger information. As an additional feature, the high voltage required by each wire is also supplied. The gain is 5V output voltage @ 20 pC input signal charge. The equivalent input noise charge is 4 × 10-15 C for the channel only and 6 × 10-15 for the entire system. The nonlinearity is better than 0.1% f.s. and the crosstalk is less than 1%. The Z-position resolution achieved is 1%.