Epitaxial Channel Research Articles

Thin channel Ga2O3 MOSFET with 55 GHz fMAX and >100 V breakdown

This Letter reports a highly scaled 90 nm gate length β-Ga2O3 (Ga2O3) T-gate MOSFET with a power gain cutoff frequency (fMAX) of 55 GHz. The 60 nm thin epitaxial Ga2O3 channel layer was grown by molecular beam epitaxy, while the highly doped (n++) source/drain regions were regrown using metal organic chemical vapor deposition. Maximum on current (IDS,MAX) of 160 mA/mm and trans-conductance (gm) around 36 mS/mm were measured at VDS = 10 V for LSD = 1.5 μm device. Transconductance and on current are limited by high channel sheet resistance (Rsheet). Gate/drain breakdown voltage of 125 V was measured for LGD = 1.2 μm. We extracted 27 GHz current gain cutoff frequency (fT) and 55 GHz fMAX for 20 V drain bias for unpassivated devices. While no current collapse was seen initially for both drain and gate lag measurements for 500 ns pulse, moderate current collapse was observed after DC, RF measurements caused by electrical stressing. We calculated a high fT. VBR product of 3.375 THz V, which is comparable to the state-of-the-art GaN HEMTs. This figure of merit suggests that Ga2O3 could be a potential candidate for X-band application.

Design and optimization of stress/strain in GAA nanosheet FETs for improved FOMs at sub-7 nm nodes

Stress/strain engineering techniques are employed to boost the performance of Gate-all-around (GAA) vertically stacked nanosheet field-effect transistors (NSFETs) for 7 nm technology nodes and beyond. In this work, we report on the 3D numerical simulation study of the impacts of source/drain epitaxial and uniaxial strained-SiGe channel stresses on p-type NSFETs. It is shown that the uniaxial strained-SiGe channel improves the drive current by up to 107% due to higher compressive stress while the 3-stack NSFET can achieve an enhancement in drive current even up to 187% using a 30% Ge mole fraction. Furthermore, we compare the multiple stacked channel NSFETs and nanowire FETs (NWFETs) considering different strain techniques. As compared to a 3-stack strained-SiGe NWFET, NSFETs show 27% and 10% enhancements in ION and SS, respectively. Vertically stacked NSFETs are shown to be the best option to improve the hole mobility under biaxial and uniaxial compressive strain rather than NWFETs. We also look at how the Ge mole fraction affects various electrical properties in a uniaxial strained-SiGe channel with shrinking dimensions of scaled NSFETs. It is observed that for a fixed Lg, ION/IOFF ratio, SS and DIBL decrease with the increase in Ge mole fraction.

β-Ga2O3 FinFETs with ultra-low hysteresis by plasma-free metal-assisted chemical etching

In this work, β-Ga2O3 fin field-effect transistors (FinFETs) with metalorganic chemical vapor deposition grown epitaxial Si-doped channel layer on (010) semi-insulating β-Ga2O3 substrates are demonstrated. β-Ga2O3 fin channels with smooth sidewalls are produced by the plasma-free metal-assisted chemical etching (MacEtch) method. A specific on-resistance (Ron,sp) of 6.5 mΩ·cm2 and a 370 V breakdown voltage are achieved. In addition, these MacEtch-formed FinFETs demonstrate DC transfer characteristics with near zero (9.7 mV) hysteresis. The effect of channel orientation on threshold voltage, subthreshold swing, hysteresis, and breakdown voltages is also characterized. The FinFET with channel perpendicular to the [102] direction is found to exhibit the lowest subthreshold swing and hysteresis.

High-Power 4H-SiC MOSFET with an Epitaxial Buried Channel

A method for reducing the on-state resistance of a high-power 4H-SiC metal-oxide-semiconductor field-effect transistor (MOSFET) by forming a buried channel via the growth of epitaxial layers on the surface of the heavily doped p-region is proposed. The features of the carrier transport in the epitaxial buried channel are considered in comparison with that fabricated by conventional technology. A more than threefold decrease in the resistance of the high-power MOSFET is achieved.

Cиловой МДП-транзистор на 4H-SiC с эпитаксиальным заглубленным каналом

Abstract A method for reducing the on-state resistance of a high-power 4 H -SiC metal-oxide-semiconductor field-effect transistor (MOSFET) by forming a buried channel via the growth of epitaxial layers on the surface of the heavily doped p -region is proposed. The features of the carrier transport in the epitaxial buried channel are considered in comparison with that fabricated by conventional technology. A more than threefold decrease in the resistance of the high-power MOSFET is achieved.

Symmetric Ambipolar Thin-Film Transistors and High-Gain CMOS-like Inverters Using Environmentally Friendly Copper Nitride.

Oxide semiconductor thin-film transistors (TFTs) are currently used as the fundamental building blocks in commercial flat-panel displays because of the excellent performance of n-channel TFTs. However, except for a few materials, their p-channel performances have not been acceptable. Although some p-type oxide semiconductors exhibit superior hole transport properties, their TFT performances are greatly deteriorated, which is a major obstacle in the development of complementary metal-oxide-semiconductor (CMOS) circuits. Herein, an ionic nitride semiconductor, copper nitride (Cu3N), composed of environmentally benign elements is shown to exhibit highly symmetric hole and electron transport, indicating its suitability for application in CMOS circuits. We performed a two-step investigation. The first step was to examine the ultimate potential of Cu3N using an electric-double-layer transistor structure with epitaxial Cu3N channels measured at 220 K, which exhibited ambipolar operation with hole and electron mobilities of ∼5 and ∼10 cm2 V-1 s-1, respectively, and a high on/off ratio of ∼105. The second step is to demonstrate the feasibility of TFT circuits with a polycrystalline channel on non-single-crystal (SiO2/Si) substrates. CMOS-like inverters composed of two polycrystalline Cu3N ambipolar TFTs on a SiO2/Si substrate exhibited a high voltage gain of ∼100.

Editors' Choice—2.32 kV Breakdown Voltage Lateral β-Ga2O3 MOSFETs with Source-Connected Field Plate

We report on demonstrating high performance lateral β-Ga2O3 metal-oxide-semiconductor field-effect transistors (MOSFETs) with source-connected field plate (FP) on a thin (150 nm) and highly Si-doped (n = 1.5 × 1018 cm−3) β-Ga2O3 epitaxial channel layer grown by ozone molecular beam epitaxy (MBE) on Fe-doped semi-insulating (010) substrate. For a MOSFET with a gate-drain spacing (Lgd) of 25 μm, the three terminal off-state breakdown voltage (VBR) tested in Fluorinert ambient reaches 2321 V. To the best of our knowledge, this is the first report of lateral β-Ga2O3 MOSFET with high VBR of more than 2 kV and the highest VBR attained among all the Ga2O3 MOSFETs. The breakdown voltages with different Lgd from 5–25 μm ranged from 518–2321V, with a linear trend of increasing breakdown voltage for larger spacing lateral MOSFETs. Combining with high electrical performances and excellent material properties, source-connected FP lateral β-Ga2O3 MOSFET implies its great potential for next generation high-voltage and high-power switching devices applications above 2 kV.

Recessed-Gate Enhancement-Mode $\beta $ -Ga2O3 MOSFETs

We report enhancement-mode $\beta $ -Ga2O3 (BGO) MOSFETs on a Si-doped homoepitaxial channel grown by molecular beam epitaxy. A gate recess process is used to partially remove the epitaxial channel under the 1- $\mu \text{m}$ gated region to fully deplete at ${V}_{\textsf {GS}}= 0$ V. BGO MOSFETs achieve drain current density near 40 mA/mm and ${I}_{ \mathrm{\scriptscriptstyle ON}}/{I}_{ \mathrm{\scriptscriptstyle OFF}}$ ratio ~109 which is the highest reported for homoepitaxial normally-off BGO transistors. At ${V}_{\textsf {GS}}= \textsf {0}$ V, a breakdown voltage of 198 and 505 V is achieved with the source–drain spacing of 3 and $8~\mu \text{m}$ , respectively. The power switching figure of merits for dc conduction and dynamic switch losses meet or exceed the theoretical silicon limit and previously reported depletion-mode BGO transistors.

Analytical model for the potential barrier height in depleted channel formed by P-N junctions

P-N junction plays an important role in some semiconductor devices, such as bipolar junction transistor (BJT), metal- insulator-semiconductor field-effect transistor (MISFET) and junction field-effect transistor (JFET). However, the role of P-N junction in static induction device (SID) is different from other devices. SID is the typical example of semiconductor devices with depleted channel formed by two P-N junctions. Based on that, potential barrier has been formed in the channel, which is different from usual potential barrier in other semiconductor devices. The potential barrier controls electron movements in the parallel direction not in the vertical direction. In other words, the channel current is controlled by the potential barrier height, which is dependent on applied voltages. As a kind of junction devices, SID has been widely used in acoustic frequency, high frequency and microwave fields. Compared with other semiconductor devices, SID features high switching speed, high power, high pressure resistance, and strong anti-radiation which has been considered to be a promising power semiconductor device. The key principle of SID is that potential barrier height is dependent on applied voltages. As a result of that, the potential barrier model of SID has been proposed by Bulucea, but it doesn’t provide the clear analytical expression of potential barrier height with the device structure and applied voltages. Taking into account the defect existed in present potential barrier model of SID, a model of potential barrier in channel based on static induction transistor (SIT) was proposed. SIT as a typical example of SID is a type of power semiconductor device with vacuum-triode-like characteristics. The analytical expression of potential barrier height was deduced based on the analysis of device physics. Moreover, based on the assumed boundary conditions in the channel region and the depleted region bellow the channel region, the analytical expressions of barrier height was calculated by solving the simultaneous electrical potential distribution equations which were obtained by solving the Poison’s equation. The three-dimensional diagram of electrical potential distribution is obtained and it looks like a saddle. The model reflects the interdependency between the potential barrier and the material parameters, structure parameters and biases conditions. Gate-control efficiency of devices is dependent on channel length and channel width and drain-control efficiency is closely related to channel width and epitaxial impurity density. From the analytical expressions of barrier height, the voltage amplification factor can be improved by reducing drain-control efficiency and increasing gate-control efficiency. The two conditions are all dependent on the channel width. In order to verify the analytical expressions of barrier height, the numerical simulation of SIT was made at different conditions. Considering gate voltages, drain voltages, doping concentration in the epitaxial layer, channel length and channel width, the calculated potential barrier height based on the model is in good agreement with the numerical simulation results. The proposed model of potential barrier can be applied to the theoretical analysis of the I-V characteristics and structure characteristics of SID. Building accurate analytical model of potential barrier height can reduce manufacturing costs of semiconductor devices with depleted channel formed by P-N junction and improve device performance.

Spin-Hall Voltage over a Large Length Scale in Bulk Germanium.

We exploit the spin-Hall effect to generate a uniform pure spin current in an epitaxial n-doped Ge channel, and we detect the electrically induced spin accumulation, transverse to the injected charge current density, with polar magneto-optical Kerr microscopy at a low temperature. We show that a large spin density up to 400 μm^{-3} can be achieved at the edges of the 100-μm-wide Ge channel for an applied electric field lower than 5 mV/μm. We find that the spin density linearly decreases toward the center of the Ge bar, due to the large spin diffusion length, and such a decay is much slower than the exponential one observed in III-V semiconductors, allowing very large spin accumulations over a length scale of tens of micrometers. This lays the foundation for multiterminal spintronic devices, where different spin voltages can be exploited as inputs for magnetologic gates on the same Ge platform.

Tunnel FinFET CMOS inverter with very low short-circuit current for ultralow-power Internet of Things application

We have demonstrated the operation of a CMOS inverter consisting of Si tunnel FinFETs. Both p- and n-type tunnel FinFETs are successfully fabricated and operated on the same SOI wafer. The current mismatch between p- and n-type tunnel FETs is compensated by tuning the number of fin channels. Very low short-circuit current and clear voltage input–output characteristics are obtained. The thin epitaxial channel in the tunnel FinFETs effectively increases the drain current and accordingly reduces the drain capacitance, which could help high-performance tunnel FET CMOS inverter operation.

Hanle precession in the presence of energy-dependent coupling between localized states and an epitaxial graphene spin channel

Hanle spin precession measurements are a common method to extract the spin transport properties of graphene. In epitaxial graphene on silicon carbide, these measurements show unexpected behavior, due to presumed localized states in the carbon buffer layer that is present between the channel and the substrate. As a consequence, the Hanle curve narrows in its magnetic field dependence and can show an unconventional shape, which has been experimentally observed and modeled in previous studies. Here, we extend the previously developed model by assuming that the localized states are charge traps, that have a power-law distribution of trapping times. Our simulations show that the energy dependence of these trapping times can be extracted from the temperature evolution of the Hanle curve, which was previously observed in experiments. Our extended model gives better insight into what processes play a role when a spin channel is coupled to localized states and their relation to the experimental observations.

Systematic Investigation of 4H-SiC Trench Properties Dependence on Channel Concentration, Crystallographic Plane, and MOS Interface Treatment

We have systematically investigated the trench properties of 4H-SiC for p-type channel doping level formed by epitaxial growth, crystallographic plane, and MOS interface treatment. Our results show that the channel mobilities on the (1-100), (11-20), (-1100), and (-1-120) planes gradually decreased in the range from 1 × 1016 to 1 × 1017 cm-3 as the epitaxial channel concentration increased. An inevitable tradeoff existed between channel mobility (field-effect mobility, µFE) and threshold voltage (Vth) in trench MOSFETs. Furthermore, the maximum µFE at a channel concentration of 1 × 1017 cm-3 was 95 cm2·V-1·s-1 on the (11-20) plane with wet + hydrogen (H2) annealing, 83 cm2·V-1·s-1 on the (1-100) plane with wet + H2 annealing and 57 cm2·V-1·s-1 on the (1-100) plane with nitric oxide annealing.

Substrate bias effect of epitaxial delta-doped channel MOS transistor for low-power applications

ABSTRACTConventional planar transistor shows shrinking substrate bias effect at scaled technology. On the other hand, epitaxial delta-doped channel (EδDC) transistor shows substantial amount of substrate bias effect even at 16-nm channel length. This paper unveils the physics behind the substrate bias effect of an n-channel EδDC transistor through Technology Computer Aided Design simulation with analytical justifications. The depletion width for an EδDC transistor very weakly depends upon the applied substrate bias, and with scaling down of channel length, the depletion width insignificantly gets widened. The substrate control over the channel is high so that significant amount of substrate depletion charge terminates on the gate, instead of on the source and the drain. The degradation of threshold voltage roll off and drain-induced barrier lowering coefficient with the increase of substrate bias, is less for the EδDC transistor, compared to that of a conventional halo free transistor. The dependence of the substrate bias sensitivity on the thickness of the low-doped epitaxial layer and concentration of the high-doped layer is explored. The effects of reverse substrate bias on leakage power dissipation and intrinsic delay of EδDC and conventional transistors are discussed.

Development of a novel 1200-V-class 4H-SiC implantation-and-epitaxial trench MOSFET with low on-resistance

In this paper, we present a newly developed 1200-V-class 4H-SiC implantation-and-epitaxial trench metal–oxide–semiconductor field-effect transistor (IETMOSFET). It uses high-quality p- and n-epitaxial layers for a channel and a trench current spreading layer (TCSL), respectively. It can enhance both channel mobility and bulk mobility for current spreading by avoiding damage and impurity variations caused by ion implantation. The ion implantation and epitaxial techniques developed for existing ion-implantation-and-epitaxial MOSFETs (IEMOSFETs) are herein utilized to protect the trench bottom and a relatively low-doped epitaxial channel layer with high mobility. By optimizing the geometry of p-base regions under a gate trench structure, we obtain a low specific on-resistance (RONA) of 1.8 mΩ cm2 with a breakdown voltage (BVDSS) above 1200 V.

Reliability of Diode-Integrated SiC Power MOSFET(DioMOS)

Status of the reliability study on silicon carbide (SiC) power MOS transistors is presented. The SiC transistors studied are diode-integrated MOSFETs (DioMOS) in which a highly doped n-type epitaxial channel layer formed underneath the gate oxide acts as a reverse diode and thus an external Schottky barrier diode can be eliminated. The novel MOS device can reduce the total area of SiC leading to potentially lower cost as well as the size of the packaging. After summarizing the issues on reliability of conventional SiC MOS transistors, the improvements by the newly proposed DioMOS with blocking voltage of 1200V are presented. The I–V characteristic of the integrated reverse diode is free from the degradation which is typically observed in conventional pn-junction-based body diode in SiC MOS transistors. The improved quality of the MOS gate in the DioMOS results in very stable threshold voltage within its variation less than 0.1V even after 2000h of serious gate voltage stresses of +25V and −10V at 150°C. High temperature reverse bias test (HTRB) shows very stable off-state and gate leakage current up to 2000h under the drain voltage of 1200V at 150°C. These results indicate that the presented DioMOS can be applied to practical switching systems free from the reliability issues.

Improvement of epitaxial channel quality on heavily arsenic- and boron-doped Si surfaces and impact on performance of tunnel field-effect transistors

We evaluate the impact of tunnel junction quality on the performance of tunnel field-effect transistors (TFETs). The interface between epitaxially grown channel and source surface was used as tunnel junctions. Performing a sequential surface cleaning procedure prior to epitaxial channel growth for heavily arsenic- and boron-doped Si surfaces improved the interface quality both for p- and n-TFETs. Simultaneously, the subthreshold swing (SS) values of the TFETs improved step-by-step with interface quality.

SiC DioMOS with precisely controlled epitaxial channel

Abstract

Study of performance scaling of 22-nm epitaxial delta-doped channel MOS transistor

Epitaxial delta-doped channel (EδDC) profile is a promising approach for extending the scalability of bulk metal oxide semiconductor (MOS) technology for low-power system-on-chip applications. A comparative study between EδDC bulk MOS transistor with gate length Lg = 22 nm and a conventional uniformly doped channel (UDC) bulk MOS transistor, with respect to various digital and analogue performances, is presented. The study has been performed using Silvaco technology computer-aided design device simulator, calibrated with experimental results. This study reveals that at smaller gate length, EδDC transistor outperforms the UDC transistor with respect to various studied performances. The reduced contribution of the lateral electric field in the channel plays the key role in this regard. Further, the carrier mobility in EδDC transistor is higher compared to UDC transistor. For moderate gate and drain bias, the impact ionisation rate of the carriers for EδDC MOS transistor is lower than that of the UDC transistor. In addition, at 22 nm, the performances of a EδDC transistor are competitive to that of an ultra-thin body silicon-on-insulator transistor.

Performance Enhancement of Tunnel Field-Effect Transistors by Synthetic Electric Field Effect

In this letter, we propose a synthetic electric field (SE) effect to enhance the performance of tunnel field-effect transistors (TFETs). The novel SE-TFET architecture utilizes both horizontal and vertical electric fields induced by a gate electrode that is wrapped around an ultrathin epitaxial channel. The drain current of the SE-TFET is increased up to 100 times in comparison with those of conventional TFETs. The subthreshold slope of the SE-TFET also improved, and enhanced to 52 mV/decade by scaling the channel width and channel thickness.