Envelope Tracking Power Amplifier Research Articles

Investigation of Intermodulation Distortion of Envelope Tracking Power Amplifier for Linearity Improvement

An intermodulation distortion of an envelope tracking (ET) power amplifier (PA) is investigated in this paper. For this purpose, the distortion characteristics are simulated based on the inter-connection model between the PA and supply modulator. For the sweet spot tracking ET operation, the fifth-order distortion is the most important one, which is generated by AM–PM nonlinearity. To reduce the distortion, the phase compensation network (PCN) is proposed. The efficiency of the PA is also improved by a properly designed bias circuit. For demonstration purposes, the PA and supply modulator are implemented using an InGaP/GaAs heterojunction bipolar transistor and a 0.18- $\mu$ m CMOS process, respectively. The ET PA is tested at 1.85 GHz using a long-term-evolution signal with 10-MHz bandwidth, a 7.5-dB peak-to-average power ratio, and 16 quadrature amplitude modulation. The ET PA with the proposed PCN and the bias circuit delivers a power-added efficiency of 44.3%, a gain of 23.4 dB, an evolved universal terrestrial radio access adjacent channel leakage ratio of ${-}{\hbox{38.4}}$ dBc, and an error vector magnitude of 1.8% at an average output power of 27 dBm. The multiband characteristics of the proposed ET PA are measured across 1.7–2.0 GHz. These results are achieved without any digitally supported techniques, indicating that the design approach is a promising technique for handset ET PA applications.

Broadband CMOS Stacked RF Power Amplifier Using Reconfigurable Interstage Network for Wideband Envelope Tracking

In this paper, a two-stage broadband CMOS stacked FET RF power amplifier (PA) with a reconfigurable interstage matching network is developed for wideband envelope tracking (ET). The proposed RF PA is designed based on Class-J mode of operation, where the output matching is realized with a two-section low-pass matching network. To overcome the bandwidth (BW) limitation from the high- Q interstage impedance, a reconfigurable matching network is proposed, allowing a triple frequency mode of operation using two RF switches. The proposed RF PA is fabricated in a 0.32- μm silicon-on-insulator CMOS process and shows continuous wave (CW) power-added efficiencies (PAEs) higher than 60% from 0.65 to 1.03 GHz with a peak PAE of 69.2% at 0.85 GHz. The complete ET PA system performance is demonstrated using the envelope amplifier fabricated on the same process. When measured using a 20-MHz BW long-term evolution signal, the overall system PAE of the ET PA is higher than 40% from 0.65 to 0.97 GHz while evolved universal terrestrial radio access adjacent channel leakage ratios are better than -33 dBc across the entire BW after memoryless digital pre-distortion. To our knowledge, this study represents the highest overall system performance in terms of PAE and BW among the published broadband ET PAs, including GaAs HBT and SiGe BiCMOS.

Dual-mode supply modulator for CMOS envelope tracking power amplifier integrated circuit

A dual-mode supply modulator is presented for a complementary metal-oxide semiconductor envelope tracking power amplifier (PA) integrated circuit. The proposed supply modulator, based on a hybrid buck converter, has dual Class-AB buffers and dual switches for the linear and switching amplifiers, respectively. For high average output power levels [or high-power mode (HPM)], the supply modulator is controlled to have full sizes for both the buffer and switch to supply peak envelope voltage and high output current to the PA. The supply modulator is reconfigured to have smaller sized Class-AB buffer and switch for low average output power levels (or low-power mode). The smaller sized buffer and switch are used to reduce the quiescent current of the linear amplifier and to maintain high efficiency of the switching amplifier for a lightly loaded condition. For the 16-QAM LTE uplink signal with a channel bandwidth of 5 MHz, the PA with the proposed supply modulator delivered a power-added efficiency of 46.2% at an average output power of 24 dBm for a high power mode, which shows an improvement of 8.0% compared to the stand-alone PA. For a low power mode, the PA with a reconfigured supply modulator has a power-added efficiency of 12% at an output power of 9 dBm, which is a back-off of 15 dB. This is 1.6 and 7.2% higher than that using the supply modulator for the HPM and for the stand-alone PA at the same output power, respectively. © 2015 Wiley Periodicals, Inc. Microwave Opt Technol Lett 57:1338–1343, 2015

3-D Distributed Memory Polynomial Behavioral Model for Concurrent Dual-Band Envelope Tracking Power Amplifier Linearization

This paper presents a new 3-D behavioral model to compensate for the nonlinear distortion arising in concurrent dual-band (DB) Envelope Tracking (ET) Power Amplifiers (PAs). The advantage of the proposed 3-D distributed memory polynomial (3D-DMP) behavioral model, in comparison to the already published behavioral models used for concurrent dual-band envelope tracking PA linearization, is that it requires a smaller number of coefficients to achieve the same linearity performance, which reduces the overall identification and adaptation computational complexity. The proposed 3D-DMP digital predistorter (DPD) is tested under different ET supply modulation techniques. Moreover, further model order reduction of the 3D-DMP DPD is achieved by applying the principal component analysis (PCA) technique. Experimental results are shown considering a concurrent DB transmission of a WCDMA signal at 1.75 GHz and a 10-MHz bandwidth LTE signal at 2.1 GHz. The performance of the proposed 3D-DMP DPD is evaluated in terms of linearity, drain power efficiency, and computational complexity.

Fully Monolithic BiCMOS Reconfigurable Power Amplifier for Multi-Mode and Multi-Band Applications

A power amplifier (PA) supporting wideband code division multiple access, long-term evolution (LTE), and wireless local area network applications has been implemented in 0.18- $\mu{\hbox{m}}$ SiGe BiCMOS technology. The PA integrates a tunable input matching network, a broadband output matching network, and adaptive bias circuits in a single chip to achieve high linearity and high power in different modulation schemes and operating bands. The three-stage PA adopts a differential-type configuration without using through-silicon-via technology to deliver 4 1.3–42 dB of gain and 28.2–28.6 dBm of 1-dB compression output power with a 20.8–27.6% power-added efficiency (PAE) at 1.85–2.5 GHz. To further validate the usefulness of the proposed PA, the envelope-tracking PA is designed to improve the PAE by 6.5% within the linearity specification of a 24.7-dBm average output power and a $-$ 33-dBc adjacent channel leakage ratio for 2.35-GHz 16 quadrature-amplitude-modulation time-division LTE signal with 20-MHz bandwidth.

Memory models for behavioral modeling and digital predistortion of envelope tracking power amplifiers

New advanced Envelope Tracking (ET) techniques can provide RF (Radio Frequency) transmitters with high-efficiency Power Amplifiers (PAs). On the other hand, system complexity substantially increases, requiring more advanced PA models for the representation and compensation of ET PA distortion effects. In this context, this paper proposes some solutions for behavioral modeling and digital predistortion of ET PAs. The adopted modeling strategy consists in including the modulated supply voltage as an additional independent model variable to define more accurate behavioral models capable of an increased accuracy when applied to model and compensate ET PAs. The new model variable is included in a polynomial model with memory whose nonlinear structure is derived from a binomial power series, whence the name of Memory Binomial Model (MBM). Another modeling approach is subsequently proposed, where the Cann model for static PA AM/AM nonlinearities is extended to model both AM/AM and AM/PM dynamic distortion occurring in ET PAs. The Extended Cann model includes an MBM structure for modeling dynamic AM/PM distortion effects. Both modeling approaches are tested on measured data-sets acquired using an ET measurement set-up including a commercial PA from RFMD and an envelope modulator designed using a commercial IC from Texas Instruments. The measured results showed that the proposed models could obtain a better modeling and predistortion performance when applied to ET PAs, with respect to the Memory Polynomial Model, here considered as a reference to represent the state-of-the-art of PA modeling and digital predistortion.

CMOS Saturated Power Amplifier With Dynamic Auxiliary Circuits for Optimized Envelope Tracking

A CMOS saturated power amplifier (PA) is developed for optimally implementing the envelope-tracking (ET) transmitter. The CMOS saturated PA is used to maximize the efficiency of the ET PA. The dynamic feedback control and the biasing techniques at the gates of the common-gate stage and the common-source of the cascode structure are proposed to improve the dynamic range, linearity and efficiency. The fully-integrated CMOS PA with a supply modulator is fabricated using a 0.18- μm RF CMOS technology. For a long-term evolution signal at 1.85 GHz with a 10-MHz bandwidth and a 16-quadrature amplitude modulation 7.5 dB peak-to-average power ratio, the ET-based CMOS PA module delivers a power-added efficiency of 37.6%, an error vector magnitude of 2.4%, and an an evolved universal terrestrial radio access adjacent channel leakage ratio (ACLRE-UTRA) of -36.8 dBc at an average output power of 26.5 dBm. The proposed auxiliary circuits enable the ET-based CMOS PA to provide the significantly improved performance.

A Hysteretic Two-phase Supply Modulator for Envelope Tracking RF Power Amplifiers

In this paper a two-phase supply modulator suitable for envelope tracking power amplifier is presented. The designed supply modulator has the linear assisted switching architecture. Two-phase architecture is used in order to reduce the output switching ripples. The proposed architecture uses hysteretic control instead of pulse width modulation (PWM) which significantly reduces the circuit complexity. Moreover, fewer number of external R and C elements are used which leads to simpler architecture in comparison with reported two-phase PWM supply modulators. The proposed envelope modulator is evaluated with 0.18 µm CMOS technology. The results show that the designed two-phase modulator improves the output switching noise ripples and consequently enhances the overall linearity of the modulator compared to the single-phase case. The overall efficiency of the two-phase envelope modulator is 72.5% with 80 MHz switching frequency for a one-tone 5 MHz envelope signals at 27.4 dBm output power. The RMS output voltage ripples is less than 7.2 mV in a wide range of input signal amplitude while a SFDR of 50.4dB is achieved.

Dynamic Stack-Controlled CMOS RF Power Amplifier for Wideband Envelope Tracking

In this paper, a dynamic stack-controlled CMOS FET RF power amplifier (PA) is developed to enhance the efficiency of the envelope tracking power amplifier (ET PA) system for low-voltage operation. The power cell used in the two-stage PA is a quadruple-stacked FET structure with dynamic stacking controller to reconfigure the power cell into the quasi-triple or quasi-double stacks according to the magnitude of the input envelope signal. The proposed power cell boosts the peak efficiency in the low V DD region by bypassing the stack entering the triode region and reoptimizing the load impedance so that all the FETs operate under the saturation and the optimum load conditions. A detailed analysis is presented to understand the gain and phase step discontinuities at the stack switching points, and the circuit techniques to equalize the gain and phase between the adjacent stack configurations are developed. The proposed two-stage stack-controlled PA is fabricated with a 0.32-μm silicon-on-insulator (SOI) CMOS process together with the envelope amplifier (EA). Full long-term evolution (LTE) characterization is performed using LTE signals with a peak-to-average power ratio (PAPR) of 6.7 dB and signal bandwidths (BW) of 10 and 20 MHz. With 10-MHz signals, dynamic stacking provides 3.5% power added efficiency (PAE) improvement over the static stack at 25.7 dBm, resulting in 47.5% PAE with 26.6-dB gain. A 20-MHz LTE test shows an overall PAE of 45.9% with an evolved universal terrestrial radio access (E-UTRA) adjacent channel leakage ratio (ACLR) of -33 dBc with memoryless digital predistortion. Even with the lower efficiency of the EA compared with the state-of-the-art results, the measured overall system efficiency with 3.4 V maximum voltage is comparable with those reported using GaAs HBT's with 5 V supplies, which clearly demonstrates the advantages of the proposed dynamic stack control.

Dual-Band Volterra Series Digital Pre-Distortion for Envelope Tracking Power Amplifiers

This letter presents a new dual band Volterra-based model suitable for the linearization of envelope tracking (ET) power amplifiers (PAs) driven concurrently with two widely spaced modulated signals. The model has two modules: a dual-band baseband equivalent Volterra series to compensate for the dynamic nonlinear distortions associated with the PA (assuming a constant drain supply voltage) and a polynomial term added to mitigate the distortions introduced by a dynamic drain supply modulation. The proposed model was successfully applied to linearize a $10~{\rm W}$ and a $45~{\rm W}$ dual band ET PA concurrently driven with different arrangements of two signals modulated according to wideband code division multiple access and long-term evolution standards around $2.0$ and $2.2~{\rm GHz}$ , and $2.1$ and $2.9~{\rm GHz}$ . A measured error vector magnitude of 1.5% and an adjacent channel power ratio better than $-47~{\rm dBc}$ , demonstrated the excellent linearization capacity of the proposed dual-band ET Volterra digital pre-distortion scheme.

Analysis of Envelope-Tracking Power Amplifier Using Mathematical Modeling

This paper describes analysis of an envelope-tracking power amplifier (ET PA) to show its operational behavior. The RF PA is modeled by sweeping the input power and supply voltage. The RF PA model is composed of three 2-D lookup tables including the amplitude-to-amplitude modulation, amplitude-to-phase modulation, and amplitude-to-efficiency modulation. The hybrid switching supply modulator is also modeled using an ideal op-amp, ideal switches, and other assisting blocks. Based on the mathematical models of the RF PA and supply modulator, the ET PA can be analyzed with a fast calculation speed and a good accuracy to find the optimum ET operation point. A power control strategy is presented for the optimal ET operation over a broad output power range. The effect of the delay mismatch on the characteristics of the ET PA is also described to assist the time alignment algorithm. For a 10-MHz long-term evolution signal with a 7.44-dB PAPR, the implemented ET PA at 1.71 GHz delivers a PAE of 44.3%, a gain of 29 dB, an evolved universal terrestrial radio access adjacent channel leakage ratio of -35.1 dBc, and an error vector magnitude of 2.91% at an average output power of 28 dBm.

A CMOS Envelope Tracking Power Amplifier for LTE Mobile Applications

This paper presents an envelope tracking power amplifier using a standard CMOS process for the 3GPP long-term evolution transmitters. An efficiency of the CMOS power amplifier for the modulated signals can be improved using a highly efficient and wideband CMOS bias modulator. The CMOS PA is based on a two-stage differential common-source structure for high gain and large voltage swing. The bias modulator is based on a hybrid buck converter which consists of a linear stage and a switching stage. The dynamic load condition according to the envelope signal level is taken into account for the bias modulator design. By applying the bias modulator to the power amplifier, an overall efficiency of 41.7 % was achieved at an output power of 24 dBm using the 16-QAM uplink LTE signal. It is 5.3 % points higher than that of the power amplifier alone at the same output power and linearity.

CMOS Linear Power Amplifier with Envelope Tracking Operation (Invited Paper)

A differential-cascode CMOS power amplifier (PA) with a supply modulator for envelope tracking (ET) has been implemented by 0.18 μm RF CMOS technology. The loss at the output is minimized by implementing the output transformer on a FR-4 printed circuit board (PCB). The CMOS PA utilizes the 2 nd harmonic short at the input to enhance the linearity. The measurement was done by the 10MHz bandwidth 16QAM 6.88 dB peak-to-average power ratio long-term evolution (LTE) signal at 1.85 GHz. The ET operation of the CMOS PA with the supply modulator enhances the power-added efficiency (PAE) by 2.5, to 10% over the stand-alone CMOS PA for the LTE signal. The ET PA achieves a PAE of 36.5% and an ACLRE-UTRA of ?32.7 dBc at an average output power of 27 dBm.

A new GaN-based high-speed and high-power switching circuit for envelope-tracking modulators

In this paper, we report a new high-speed and high-power switching circuit based on GaN HEMT's. The elementary switching cell, composed of two GaN HEMT's and two resistors, acts like a power threshold comparator with high-output voltage. Theoretical analysis of static and dynamic circuit operation points out the dependence of efficiency and switching speed to the main circuit elements. Four switching cells are then combined together thanks to SiC Schottky diodes to design a multi-level power switch that can be used as a power supply modulator for envelope tracking power amplifiers. The designed four-level supply modulator, based on Nitronex GaN HEMT's, exhibits more than 75% of efficiency for an envelope signal up to 4 MHz, a switching frequency of 20 MHz and output voltages in the range of 12–30 V.

Sequential Digital Predistortion for Two-stage Envelope Tracking Power Amplifier

To improve the efficiency of the main power amplifier, the envelope tracking technique is widely used. However, due to the reduced gain of the main amplifier by the envelope tracking, the driving power of the drive amplifier requires to be larger and the amplifier should be optimized accordingly for an efficiency operation. In this letter, a two stage envelope tracking power amplifier is studied for the purpose. The envelope tracking technique is applied to both the drive and main power amplifiers to improve efficiency of the drive amplifier, which is usually operated at a low efficiency. The experimental results show that the efficiency of the total system is improved by 2.1% while the efficiency of the drive amplifier is increased by 8%. In addition, to overcome a serious non-linearity due to the dual envelope tracking operation, a new sequential digital predistortion architecture is proposed and using this architecture, the linearity specification of the long term evolution signal has been successfully satisfied.

High-Efficiency Silicon-Based Envelope-Tracking Power Amplifier Design With Envelope Shaping for Broadband Wireless Applications

This paper presents a highly efficient silicon-based envelope-tracking power amplifier (ET-PA) for broadband wireless applications. A pseudo-differential power amplifier (PA) is designed using two integrated SiGe power cells fabricated in a 0.35- μm SiGe BiCMOS technology with through-silicon-via (TSV). In the continuous-wave (CW) measurement, the PA achieves a saturated output power (POUT) of around 2 W with power-added efficiency (PAE) above 65% across the bandwidth of 0.7-1.0 GHz. To optimize the ET-PA system performance, several envelope shaping methods such as dc shifting, envelope scaling, envelope clipping, and envelope attenuation at back-off have been investigated carefully. A highly efficient monolithic CMOS envelope modulator (EM) integrated circuit (IC) is designed in a 0.35- μm bipolar-CMOS-DMOS (BCD) process to mate with our SiGe PA. With the LTE 16 QAM 5/10/20-MHz input signals, our ET-PA system achieves around 28 dBm linear POUT, passing the stringent LTE linearity specs such as the spectrum emission mask with an average composite system PAE of 42.3%/41.1%/40.2%, respectively. No predistortion is applied in this work.

Minimum-Energy Power and Rate Control for Fair Scheduling in the Cellular Downlink under Flow Level Delay Constraint

In this paper, we study the energy-delay trade-off in the downlink of a proportional-fair cellular system with inter-cell interference and fading, while incorporating the efficiency characteristics of realistic amplifiers(PA). We study the potential for energy saving by lowering the transmission power level at different user locations in a cell at the cost of additional flow level delay. We identify the transmission power levels at different locations so that the energy consumption at the base station is minimized and the flow level delay is controlled. We formulate the energy minimization problem in a game theoretic framework and prove the convergence of the best response iteration algorithm. The energy saving potential is found to depend on the network load and the efficiency characteristics of the PAs. There is a significant potential for energy saving when the network operates under low to medium loads and efficient PAs are utilized. For example, with envelope tracking PA, around 90% of energy can be saved by introducing small additional flow level delay when the network load is less than 75%. Motivated by the fact that the network load keeps varying throughout the day, we take a daily traffic model and demonstrate the potential for energy saving by this scheme.

On the Signal Probability Distribution Conscious Characterization of GaN Devices for Optimum Envelope Tracking PA Design

This letter presents a signal probability distribution function conscious characterization technique, suitable for the optimization of envelope tracking (ET) power amplifiers. The method and its validation rely on pulsed harmonic load-pull measurements. The analytical treatment permitted to understand the impact of the peak-to-average power ratio on the load termination, and the experimental characterization revealed the sensitivity of the ET performance with respect to the load termination. The technique was applied to a GaN HEMT device at the carrier frequency of 870 MHz.

Push the Envelope: Design Concepts for Envelope-Tracking Power Amplifiers

As mobile communication systems evolve to handle higher data rates, their modulation schemes only become more complicated, generating signals with large bandwidth and high peak-to-averagepower ratio (PAPR). To amplify such signals with high efficiency, the power amplifier (PA) should have high efficiency not only at the peak power level but also at low power, especially over the maximum power generation region. To realize these PA characteristics, the drain bias voltage of the transistor can be modulated on the basis of the input envelope power to minimize the dc supply power. Thus, the drain bias voltage should follow the envelope of the modulated signal, and this is called envelope tracking (ET). Usually, the envelope is shaped to realize the optimum performance from the ET PA. The PA is biased close to class B, and the dc current is automatically adjusted to the power level. The resulting PA has high efficiency for all power levels, comparable to the maximum efficiency of the PA at high power. In practice, the efficiency is degraded somewhat at low voltage because of the knee effect, lower transconductance, and mismatch effect for different drain bias voltages.

A Dual Power-Mode Multi-Band Power Amplifier With Envelope Tracking for Handset Applications

This paper presents a dual power-mode and multi-band power amplifier (PA) for handset applications that improves the efficiency in low-power regions. This PA operates in two modes through path control by a shunt switched capacitor. The proposed control method provides efficient mode control without any efficiency degrading and bandwidth (BW) limiting. The proposed PA, in conjunction with a boosted supply modulator for envelope tracking (ET) operation not only in the high-power mode, but also in the low-power mode, delivers good performance at all average output power levels. The linearity is improved by ET through a proper envelope-shaping method. For demonstrative purposes, the PA and supply modulator are implemented using an InGaP/GaAs heterojunction bipolar transistor and AIGaAs/InGaAs enhancement/depletion-mode pseudomorphic high electron-mobility transistor process and a 0.18- $\mu$ m CMOS process, respectively. The ET PA is tested across the range of 1.7–2.0 GHz using a long-term evolution signal with 16 quadrature amplitude modulation, a 7.5-dB peak-to-average power ratio, and 10-MHz BW. The proposed dual power-mode multi-band ET PA delivers good performance for high- and low-power modes, indicating that the architecture is promising for handset PA applications.