Envelope Tracking Power Amplifier Research Articles

A Review of Hybrid Supply Modulators in CMOS Technologies for Envelope Tracking PAs

This paper reviews trends, architectures, and recent developments in CMOS-based supply modulators (SM) used for envelope-tracking power amplifiers (ET-PAs). This review details the most commonly used hybrid supply modulator (HSM) architecture in CMOS, and discusses its performance requirements and design challenges. The importance of efficiency, speed, linearity, and output power in HSM design is delineated and different methods that focus on maximizing these performance parameters are presented. Finally, the design challenges of envelope tracking systems are discussed, and an overview of device technologies for implementing SM and ET-PAs is given.

FPGA Implementation of a Linearization System for Wideband Envelope Tracking Power Amplifiers

This article focuses on the implementation of a linearization system for envelope tracking (ET) power amplifiers (PAs) in field-programmable gate array (FPGA). The ET PA linearization system includes a slew-rate reduction envelope generator, a RF leakage cancellation system in the supply envelope path and a baseband <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$I - Q$ </tex-math></inline-formula> digital predistorter (DPD). This work targets the implementation of an ET PA linearization system on a radio frequency system-on-chip (RFSoC) device running under a demanding baseband sampling frequency of 614.4 MHz, which allows handling communication signals with up to 200 MHz bandwidth, considering a DPD bandwidth expansion by <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$3\times $ </tex-math></inline-formula> . The detail of the FPGA implementation is presented to illustrate the trade-off between hardware resources and linearization performance, i.e., adjacent channel power ratio (ACPR) and error vector magnitude (EVM), under different bit configurations for the arithmetic. The power consumption is also evaluated since it is another relevant performance indicator to be considered in the FPGA implementation of the linearization system.

Digital Linearization of Wideband Envelope Tracking Power Amplifiers for Mobile Terminals

This article presents a low-complexity linearization method to compensate for multisource nonlinear distortion in wideband envelope tracking (ET) power amplifiers (PAs) for 5G new radio (NR) mobile terminals. The proposed linearization approach consists in an envelope leakage cancellation (ELC) system operating in the dynamic supply path and a 2-D digital predistortion (2-D-DPD) linearizer acting on the baseband complex modulated signal. In a first step, an envelope generalized memory polynomial (EGMP) behavioral model is proposed to compensate for the unwanted radio frequency (RF) leakage that appears at the output of ET modulator (ETM). Then, a baseband 2-D-DPD linearizer based on a slow envelope-dependent generalized memory polynomial (SED-GMP) behavioral model is used to further enhance the linearization performance. The proposed method is validated on a system-on-chip (SoC) ET PA board for mobile applications. The reported experimental results show how the proposed digital linearization approach can mitigate the linearity and efficiency trade-off in ET PAs. Consequently, the out-of-band linearity requirement of −36 dBc of adjacent channel power ratio (ACPR) is met for 5G-NR test signals with bandwidths ranging from 60 to 200 MHz at 2.55 GHz (band B41), with an overall ET PA power efficiency ranging from 10.1% and up to 16.5%, depending on the signal bandwidth.

Residual RNN Models With Pruning for Digital Predistortion of RF Power Amplifiers

The paper presents several novel residual recurrent neural network (RNN) models for digital predistortion of radio-frequency power amplifiers. Then, unstructured and structured neural network (NN) pruning algorithms are proposed to reduce the per-sample computational complexity and the required memory, without compromising their modeling performance. The mathematical equations of the complexity and the memory are derived to analyze the hardware cost and design low cost models. An experimental platform is developed to measure the modeling performance in terms of adjacent channel leakage ratio (ACLR), normalized mean square error, error vector magnitude (EVM) and bit error rate. The platform uses an envelope tracking PA excited by 80 MHz IEEE 802.11ac signals. Compared with the state-of-the-art RNN model in (Sun <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">et al.</i> , 2019), the proposed models reduce the per-sample complexity and required memory by <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$94\hbox{--}99$</tex-math></inline-formula> %, they also improve the ACLR and EVM by at least 3 dB and 1 dB at 0.45 dB and 3.15 dB gain compression, respectively. Furthermore, an observation path with time alignment is used to remove the transmit latency in the state-of-the-art approach. At 3.15 dB gain compression, the proposed models outperform the state-of-the-art feedforward and convolutional NN models by at least 1.3 dB in EVM, outperform the general memory polynomial model by at least 3.3 dB in EVM. The above evidences indicate that the proposed RNN models can be implemented with relatively low hardware cost and achieve the best EVM in high power efficiency scenario.

Agnostic Envelope Linearization of Dynamically Supplied Power Amplifiers for Mobile Terminals.

This paper presents an envelope linearization technique to compensate for the nonlinear distortion of envelope tracking (ET) power amplifiers (PAs) for 5G new radio (NR) mobile terminals. The proposed envelope optimization (EOPT) method is agnostic of the nonlinear distortion generated in the envelope supply path and can compensate for the nonlinear distortion at the ET PA output without the need to monitor the output at the envelope tracking modulator (ETM). The linearization system in the envelope path is based on the envelope generalized memory polynomial (EGMP) behavioral model. Since the ETM output is not available, an iterative nonlinear least squares solution inspired in the deep deterministic policy gradient (DDPG) algorithm is proposed to extract the coefficients of the EGMP model. The EOPT method is validated on a system-on-chip (SoC) ET PA board designed for mobile terminal applications. Experimental results show the suitability of the proposed method to guarantee the linearity requirements (i.e., adjacent channel power ratio below −36 dBc) with 16.8% of power efficiency when operating the ET PA with 5G new radio test signals of 60 MHz bandwidth operating at 2.55 GHz (band 7). The linearization performance of the proposed EOPT method is comparable to the envelope leakage cancellation (ELC) approach (but saving the need for an analog to digital converter to monitor the ETM output), and can outperform a conventional I-Q digital predistorter based on the generalized memory polynomial (GMP) behavioral model.

High‐accuracy filtering‐based envelope generation and digital predistortion for wideband envelope tracking power amplifier

A high-accuracy filtering-based envelope generation technique for wideband envelope tracking power amplifiers (ET PAs) is proposed to improve PA efficiency with limited envelope bandwidth. It is achieved by optimizing the envelope generation block by employing three generalized rectification functions. The proposed envelope can be obtained by finding the proper coefficients in these generalized rectification functions. Furthermore, the digital predistortion can be employed to compensate for the nonlinearity and memory effect introduced by the proposed envelope. Experiments have been carried out on an ET system that is operated with the center frequency of 3.5 GHz, which have shown that the proposed technique can improve the PA efficiency by more than 2.2% with only 1.2× the modulated bandwidth compared to the state-of-the-art methods. The normalized mean square error can achieve −44.8 dB, and the adjacent channel leakage ratio can achieve better than −52 dBc. The proposed technique can improve the PA efficiency with limited envelope bandwidth compared to the state-of-the-art techniques, and the PA supplied by the proposed envelope can be linearized well, while it may cost more resources to find the proper coefficients of these three generalized rectification functions.

Research on Power Amplifier Based on Envelope Tracking Technology

With the development of mobile communication technology, the envelope bandwidth and power peak-to-average ratio of radio frequency signals are gradually increased. However, the power consumption requirements of electronic equipment are difficult to meet by traditional constant voltage power amplifiers. The mode of dynamic voltage supply is adopted by the envelope tracking power amplifier, which can make a good balance between the linearity and efficiency of the power amplifier system. The fundamental of envelope tracking power amplifier is shown in the article. Transistor model is selected to design the power amplifier, ADS and other tool software are used for simulation. The feasibility of envelope tracking technology is verified in improving the efficiency of power amplifier.

A 40 MHz Bandwidth, 91% Peak Efficiency, 2.5 W Output Power Supply Modulator With Dual-Mode Sigma–Delta Control and Adaptive Biasing Amplifier for Multistandard Communications

The envelope tracking (ET) design methodology is routinely adopted to improve the efficiency of radio frequency power amplifiers (PAs). One shortcoming of state-of-the-art ET PAs is that their supply modulators are usually designed and optimized for a single communications standard. They are either incompatible in modern communication devices where multiple communications standards are used, and/or the efficiency unoptimized when the devices operate in standards other than the designed standard. To circumvent this shortcoming, a novel supply modulator for multistandard communications is proposed. The proposed design embodies a proposed dual-mode Sigma–Delta control block and an adaptive biasing Class AB amplifier, which allows the supply modulator self-adjusting its operation and optimizing the efficiency according to the application. A prototype supply modulator IC is designed and fabricated using a 180 nm CMOS process. Based on measurements, the proposed supply modulator features the highest static efficiency of 91% and the highest 3 dB backoff static and dynamic efficiency compared to the state-of-the-art supply modulators. When tracking 40 MHz LTE-A envelope signals, the prototype supply modulator achieves a high efficiency of 85% at 1.8 W output power, and the efficiency remains high >80% for a wide range of output power, from 0.5 to 1.8 W.

An Open Loop Digitally Controlled Hybrid Supply Modulator Achieving High Efficiency for Envelope Tracking With Baseband up to 200-MHz

Envelope tracking (ET) is an effective way to improve the efficiency of power amplifier (PA) for 5G communication systems. To understand the restriction of the hybrid supply modulator (HSM) for ultra-wide band ET applications, an extended power loss model and a Short Time Fourier Transform (STFT) methodology are put forward to be the fundamental guide of the control methodology. An average voltage alignment (AVA) algorithm is proposed, which aligns the current waveforms by using pre-cached envelope signals to reduce the power loss due to the mismatch. Furthermore, a digital low pass filter (LPF) is integrated in the AVA controller, aiming at eliminating the necessity of very high-speed switches in HSM, which reduces the difficulty of hardware facility. The prototype chip is fabricated with a standard 0.18 μm CMOS technology and fulfilled with the discrete components on the PCB to verify the methodology and the system. Measurement results show that the proposed method extends the tracking bandwidth up to 200-MHz, and achieves 20% efficiency increment with the maximum 20 MHz switching frequency decrement comparing to the normal hysteresis comparison logic. A GaAs PA is introduced to measure the system linearity, and the ACPR of ET PA reaches -32 dBc. The proposed strategy successfully push the HSM ET application to hundreds of MHz compared with the previous level of 10-MHz.

Flexible bandwidth reduction technique for envelope tracking using low‐pass finite impulse response filters

In this Letter, low-pass finite impulse response filters are proposed to flexibly reduce the envelope bandwidth (BW) requirements for envelope tracking (ET) supply modulators. A second-order power ET (PET) approach is used as a comparative study, and a `design zone' for shaping function coefficients is identified for the first time. Proposed 20 and 10 MHz low-pass filters (LPFs) are used to reduce the effective envelope BW in response to a 20 MHz long-term evolution signal applied to a 10 W power amplifier (PA). Experimental results verify that in comparison with PET, the proposed LPF method has the benefit of allowing arbitrary BW reduction and is compatible with the use of customised shaping functions. It is also shown that significant memory effects can be introduced when the effective envelope BW is reduced to less than the RF BW. To investigate the linearisability of the ET PA, the linearity before and after digital pre-distortion is also measured.

Analysis and improvement of PSRR in an envelope‐tracking power amplifier using a common‐drain amplifier topology

A common-drain power amplifier (PA) for envelope tracking systems is presented. In envelope tracking, the main PA operates mostly in compression and the power supply rejection ratio (PSRR) is not high. Furthermore, the output noise of the supply modulator can be mixed with the RF signal and generates out-of-band emissions. In this article, instead of using a common-source topology, the PSRR of the envelope tracking PA is inherently improved by utilizing a common-drain topology. A comprehensive analysis shows that the common-drain topology is less sensitive to the supply noise, as compared to the conventional common-source topology. The proposed common-drain PA is implemented using a discrete LDMOS PD20010-E RF transistor. Measurement results show that the PSRR of the proposed common-drain PA is improved by up to 7 dB as compared to that of the common-source PA. For a two-tone input with 10 MHz bandwidth at the center frequency of 700 MHz, the power added efficiency (PAE) and IM3 of the envelope tracking common-drain PA are 20% and − 28 dBc, respectively, at an average output power of 33.4 dBm. The amplifier also shows a 12.4 dB power gain. Moreover, by utilizing the envelope tracking, the PAE is improved by more than 5%.

Modulated rapid load pull system for the emulation of envelope tracking power amplifiers

This Letter presents a novel characterisation system that is able to fully emulate a complete envelope tracking power amplifier (ET-PA) environment, with modulated impedance synthesis and dynamic supply voltage generation while using industry-standard modulated signals and digital pre-distortion. The system is used to characterise a 10 W GaN device and provide impedance control over the signal and distortion bandwidths, in response to a 10 MHz long-term evolution signal. A National Instruments PXI-based measurement system is utilised to apply tracking signals to a bespoke supply modulator and successfully improve the average power added efficiency by ~18 percentage points. Three different shaping functions are implemented, and their efficiency and linearity performance evaluated. In addition, digital pre-distortion (DPD) is used to linearise the PA while operating with the three different tracking trajectories. Experimental results demonstrate that when applying shaping functions, a trade-off needs to be made between efficiency and linearity. Even though a constant gain shaping function provides lower efficiency, it achieves good raw linearity performance without DPD, which is a good option if local linearisation is not available. This novel system is a useful tool in the design of ET-PAs, to more completely investigate the performance of the device.

Envelope emulation

Researchers from the UK present a novel characterisation system that is capable of emulating a complete envelope tracking power amplifier (ET-PA) environment around a microwave power transistor. The system achieves this by using modulated impedance synthesis and a dynamic supply voltage generation, as well as industry-standard modulated signals and digital pre-distortion. The authors believe that the system will be of use to designers of ET-PAs, allowing more complete investigation of the performance of ET-PAs in realistic modulated and load impedance conditions. As communication systems evolve to transmit ever-larger volumes of data, including the ongoing roll-out of 5G worldwide, we will need to develop more advanced modulation schemes to satisfy the rampant growth and to improve spectral efficiency. Whilst new modulation schemes offer higher data throughput levels, they are characterised by high peak-to-average power ratios (PAPRs). Power amplifiers (PA) are the major power consumer in mobile communication systems, and thus several power amplifier architectures have been proposed to improve average PA efficiency, including the Doherty PA and envelope tracking (ET). Authors (right to left) Sattam Alsahali, Alexander Alex,Dr. Jonathan Lees and Dr. Peng Chen. Set-up of the present work. Average PAE for 28 V fixed bias (blue solid contours) and for ET (green dotted contours). ET works by rapidly changing the supply voltage of the PA in response to the input signal, providing low supply voltage for low powers and vice versa. Whilst ET presents itself as a strong candidate for a wide range of applications due to its potential to support both multimode and multiband operations, the design of the ET-PA presents an array of challenges relating to optimisation of and interaction between involved sub-systems, in particular the radiofrequency (RF) potential of the ET-PA. Characterising the performance of a radiofrequency power amplifier (RFPA) and optimising its performance as early as possible within the ET environment is highly desirable. Load-pull, the colloquial term for the process of systematically varying impedance presented to a device under test, is a robust approach commonly utilised at the beginning of the design phase of an RFPA to characterise the device's performance at fundamental and harmonic frequencies, typically in terms of output power, efficiency, gain and linearity. The work presented by Alsahali et al. is the first work that combines a fast, modulated load-pull system (known as the Mesuro RAPID system) and digital pre-distortion, producing a powerful ET characterisation bench. Achieving this ET characterisation bench wasn't easy, the team had to combine and synchronise a number of different systems. In particular, the efficiency measurement and the time alignment between the RF signal and the tracking signal were especially challenging to characterise. Despite the challenges, the team's Letter shows that they ultimately succeeded in pulling together myriad subsystems to produce a highly useful package. The authors hope that their proposed system will be useful for the future design of ET-PAs by providing a powerful emulation tool. This first example only allows for fundamental load pull, in order to fully investigate the potential of the new measurement architecture, the ability to incorporate harmonics, specifically the 2nd and 3rd harmonics (significant in realising highly efficient PA modes of operation), will be highly beneficial. In addition, it was found that the modulation bandwidth of the Mesuro RAPID load-pull system is limited to 40 MHz. A 5G system will require at least 100 MHz to fully characterise the nonlinearity of RFPAs, which requires at least five times the modulation bandwidth. The group has already begun working on these bandwidth enhancements - watch this (ever expanding) space.

Analysis of Gain Variation With Changing Supply Voltages in GaN HEMTs for Envelope Tracking Power Amplifiers

Envelope tracking (ET) is a promising power amplifier (PA) architecture for current and future communications systems, which uses dynamic modulation of the supply voltage to provide high efficiency and potentially very wide bandwidth over a large dynamic range of output power. However, the dynamic nature of the supply voltage can lead to a problematic variation in transistor gain, particularly in GaN HEMTs. This paper describes and analyzes this behavior and the detrimental effect it can have on ET PAs. Contributing factors and origins of gain variation are described in detail along with how, for the first time, meaningful comparisons can be made between different devices. Using these guidelines, gain variation is shown to be a widespread issue effecting most GaN HEMTs presented in literature. To allow an analysis of the intrinsic device behavior, an extended transistor model is developed that takes the effect of gate and source field plates into account. This model is refined using measurement data and used to demonstrate the fact that the parasitic gate–drain capacitance ( $C_{\textrm {GD}}$ ) is the main contributor to the small-signal gain variation—a significant part of the overall gain variation. Based on this knowledge, possible strategies to reduce gain variation at the transistor technology level are proposed, allowing the optimization of GaN HEMTs specifically for ET PAs. One identified strategy involves reducing the length of the gate field plate and is shown to be a viable approach to reduce the gain variation in GaN HEMTs, albeit at an increased RF/dc dispersion.

Analytical Design Solution for Optimal Matching of Hybrid Continuous Mode Power Amplifiers Suitable for a High-Efficiency Envelope Tracking Operation

An analytical method to design a power amplifier (PA) with an optimized power added efficiency (PAE) trajectory for envelope tracking (ET) architecture is proposed. To obtain feasible matching solutions for high-efficiency performance of the PA in the dynamic supply operation, hybrid continuous modes (HCM) architecture is introduced. The design space for load impedances of the HCM PAs with nonlinear capacitance is deduced mathematically using the device’s embedding transfer network, without the necessity of using load-pull. The proposed design strategy is verified with the implementation of a GaN PA operating over the frequency range of 1.9 GHz to 2.2 GHz with PAE between 67.8% and 72.4% in the 6.7 dB back-off power region of the ET mode. The ET experimental system was set up to evaluate the application of the PA circuit. Measurement results show that the ET PA at 2.1 GHz reaches the efficiency of 61%, 54%, 44% and an error vector magnitude (EVM) of 0.32%, 0.60%, 0.67% at an average output power of 34.4 dBm, 34.2 dBm, 34.1 dBm for 6.7 dB peak-to-average power ratios (PAPR) signals with 5 MHz, 10 MHz, and 20 MHz bandwidths, respectively. Additionally, tested by a 20 MHz bandwidth 16 quadrature amplitude modulation (QAM) signal, 41.8% to 49.2% efficiency of ET PA is achieved at an average output power of 33.5 dBm to 35.1 dBm from 1.9 GHz to 2.2 GHz.

Analysis of Systematic Losses in Hybrid Envelope Tracking Modulators

This paper presents a comprehensive analysis of the intrinsic losses in hybrid envelope tracking power supply modulators used in envelope tracking power amplifier systems. The losses are computed entirely symbolically in terms of system parameters and a single design parameter. Resulting formulations are used to provide design insight into optimum biasing to minimize losses in a hybrid configuration, and establish the theoretical upper bound of achievable efficiency. To illustrate the value of this analysis, a Rayleigh distributed waveform is used to evaluate the performance of the hybrid modulator to describe OFDM and other complex modulation schemes. This paper demonstrates that the common convention of biasing the linear converter’s output stage to have zero average current is generally suboptimal from a loss perspective, and establishes how efficiency can be improved without modifying the underlying circuit topology. These findings are validated with a series of simulations modeling a hybrid modulator implemented in a 180-nm CMOS process. This paper derives for the first time, the intrinsic theoretical losses in the hybrid envelope modulator configuration.

A 2.5-W 40-MHz-Bandwidth Hybrid Supply Modulator With 91% Peak Efficiency, 3-V Output Swing, and 4-mV Output Ripple at 3.6-V Supply

We describe a supply modulator comprising a proposed delay-based hysteresis controller, proposed wideband class-AB amplifier, and class-D amplifier for an envelope tracking (ET) power amplifier (PA). We investigate the power dissipation and optimization method of the supply modulator for wideband applications taking into consideration the propagation delay, and show that a controller with zero threshold current not only improves the bandwidth of the supply modulator but also reduces its power dissipation. Based on our investigations, we propose a delay-based hysteresis controller embodying a novel high-speed current comparator whose reference current (threshold current) is zero, thereby achieving higher power-efficiency and simpler hardware. We further propose a class-AB amplifier, which features a high bandwidth and accurately controlled quiescent current. The proposed supply modulator features simultaneously the wide bandwidth (40 MHz), high output power (2.5 W), high peak efficiency (91%), high output voltage swing (3 V), and low output ripple noise (4 mVrms) at 3.6-V supply. The ET PA embodying our proposed supply modulator achieves a high power-efficiency of 41.4% at 28.5-dBm peak output power and 34.4% at 3-dB backoff—a significant >1.6× improvement over the radio frequency PA without the supply modulator.

Linearity and Noise Improvements of Driver-Stage Envelope-Injection Power Amplifier With Amplitude and Phase Shaping Functions for 5G New Radio Application

The driver-stage envelope-injection power amplifier (EIPA) consisting of the wideband linear amplifier with the envelope amplitude and phase shaping functions is proposed. This SiGe BiCMOS EIPA is implemented without the switch amplifier and the off-chip inductor used in the conventional envelope tracking circuit. To improve the in-band distortion and the out-of-band intermodulation of power amplifier, the envelope amplitude and phase shaping functions of the driver-stage EIPA are investigated to equally generate the two-tone fundamental terms and symmetrically minimize the third-order intermodulations (IM3s) by using the three-tone harmonic balance analysis. The maximum linear output power of the driver-stage EIPA with the corresponding envelope amplitude and phase shaping functions is 23.5 dBm for -30-dBc third-order intermodulation distortion (IMD3) specification. The 2.35-GHz 256-quadrature amplitude modulation Time-Division Duplexing signal with the 50-MHz bandwidth is applied to validate the usefulness of the driver-stage EIPA for 5G New Radio (NR) applications. Compared to the conventional envelope tracking PA and the dc-supply PA, the measured results show that the out-of-band noise of the proposed driver-stage EIPA is significantly reduced and the maximum average output power is increased from 21 dBm to 23.5 dBm at the -30-dBc adjacent channel leakage ratio (ACLR) specification and the ACLR and error vector magnitude are improved by 5 dB and 1.3 % at 23.5-dBm average output power, respectively.

Partial Least Squares Identification of Multi Look-Up Table Digital Predistorters for Concurrent Dual-Band Envelope Tracking Power Amplifiers

This paper presents a technique to estimate the coefficients of a multiple-look-up table (LUT) digital predistortion (DPD) architecture based on the partial least-squares (PLS) regression method. The proposed 3-D distributed memory LUT architecture is suitable for efficient FPGA implementation and compensates for the distortion arising in concurrent dual-band envelope tracking power amplifiers. On the one hand, a new variant of the orthogonal matching pursuit algorithm is proposed to properly select only the best LUTs of the DPD function in the forward path, and thus reduce the number of required coefficients. On the other hand, the PLS regression method is proposed to address both the regularization problem of the coefficient estimation and, at the same time, reducing the number of coefficients to be estimated in the DPD feedback identification path. Moreover, by exploiting the orthogonality of the PLS transformed matrix, the computational complexity of the parameters’ identification can be significantly simplified. Experimental results will prove how it is possible to reduce the DPD complexity (i.e., the number of coefficients) in both the forward and feedback paths while meeting the targeted linearity levels.

Hysteresis nonlinearity modeling and linearization approach for Envelope Tracking Power Amplifiers in wireless systems

Novel Dual-Input Single-Output (DISO) behavioral modeling and linearization techniques for Envelope Tracking Power Amplifiers (ET PAs) in wireless application are presented in this paper. The proposed modeling approach applies the Hammerstein structure for the Amplitude-to-Phase (AM/PM) conversion. An extension of the Saleh AM/PM model is also proposed to model the static nonlinearity in the ET PA AM/PM conversion. This paper presents a new linearization technique for ET PAs by inverting the proposed ET PA model and using it as a Digital Predistortion (DPD). The measurement results show that both the proposed model and DPD can clearly outperform both the original Saleh model and the DPD based on the Saleh model inversion. Compared to the state-of-the-art behavioral models for ET PAs, the proposed model and DPD can offer an improved complexity-accuracy trade-off thanks to the lower number of coefficients.