Entire Chips Research Articles

Breakthrough curvilinear ILT enabled by multi-beam mask writing

Background: Multi-beam mask writers have been one of the most significant additions to the semiconductor manufacturing equipment arsenal in over a decade. The ability of multi-beam mask writers to write masks with a constant write time regardless of mask shapes or complexity has made them an eagerly anticipated advancement to help write curvilinear mask shapes for both today’s advanced 193i nodes and for extreme ultra-violet (EUV) lithography in the future. Perhaps the most obvious application for these new pixel-based mask writers is the production of curvilinear inverse lithography technology (ILT) masks. ILT has been seen as a promising solution to many of the challenges of advanced-node lithography, whether optical or EUV. However, the runtimes and mask writing times associated with this computational technique have limited its practical application. Until recently, it had been used for critical “hotspots” on chips, but had not been used for entire chips. Aim: The introduction of multi-beam mask writing, along with the advent of graphics processing unit (GPU)-accelerated computing for mask and wafer, have enabled the introduction of a new approach to full-chip ILT using these new technologies. The goal was to produce full-chip, curvilinear ILT within the traditional turnaround times of mask shops. Approach: The solution to the runtime problem for ILT has been particularly vexing, as the traditional approach to runtime improvement—partitioning and stitching—has failed to produce satisfactory results, either in terms of runtime or in terms of quality. In 2019, D2S introduced an entirely new, stitchless approach, systematically designed for ILT, multi-beam mask writers, and GPU acceleration, that makes full-chip ILT a practical reality in production for the first time. Results: We present this new ILT approach, first introduced using a multi-beam mask writer to create the complex curvilinear mask shapes. We also review findings that targeting curvilinear mask shapes creates masks that are more resilient to manufacturing variation. Finally, we review the results of this new, stitchless full-chip curvilinear ILT as applied to memory chip making. We show mask making and wafer print results, including pattern fidelity and process window, to demonstrate the actual benefit of such technologies—a doubling in the wafer process window—for semiconductor manufacturing.

Optimizing Collector-Emitter Saturation Voltage at 3000 V Insulated Gate Bipolar Transistors Using Laser Thermal Annealing

In this work, two thermal annealing processes (furnace and laser annealing) are adopted to obtain 3000 V breakdown voltage in insulated gate bipolar transistors (IGBTs) for propulsion control system of electric vehicles. In furnace annealing process (450 °C for 30 min), the parameter of Vce(sat) is 5.5–6.5 V once measuring at Ic = 2.0 A with EDS(electrical die sorting) analyser. However, annealing process was performed using a laser equipment to lower the Vce(sat). After back side grinding and back side implant, the sample wafer undergoes laser annealing process. From various annealing conditions it was found that the Vce(sat) was 1.6–1.7 V when measuring at collector current (Ic) of 2.0 A after annealing at pulse with of 1100 nm, 3-overlap and 3.5 J/cm2. From these results, it is found that the Vce(sat) is lower as increasing laser energy density and overlapping and the well-distributed Vce(sat) values over the entire chips appear as widening the laser pulse.

Intel and the Tale of Rebates: The (More) Economic Approach to the Rescue!

In what should have been an exemplary case and a plea of an enforcement untamed and far away from the Chicago approach, the EU commission ruled, in 2009, that Intel, holding approximately a 70% share in the market for computer chips, in the period 2002-2007 abused its market power by putting in place essentially two types of conduct: (i) the first one consisting of the application of rebates to five major OEMs provided they were supplied by Intel for almost their entire chips requirements. In particular, Intel allegedly structured its price policy in order to assure that, if those manufacturers sourced their chips’ supplies also from other competing manufacturers, they would have lost in toto, or to a considerable extent, their right to obtain a rebate on the vast majority of their previous orders, therefore encouraging them to stock up exclusively from Intel itself; (ii) the second one consisting in offering payments to OEMs in order to induce them to delay, cancel or restrict the marketing of products based on the rival’s chipsets. The second act of this narrative dates 2014, when the General Court, in endorsing the Commission's ruling, showed an unexpected upsurge of formalistic stiffening and created a kind of sub-category within by object restrictions, which, irrespective of the (still feasible, but practically unworkable) proof of their objective justification in terms of efficiencies or rather benefits to consumers, would have been considered per se capable of producing exclusionary effects vis a vis competitors. The General Court was also lapidary in intimating that there was no need to apply quantitative economic methods as to verify the existence of an infringement. The ECJ, preceded by AG Wahl,did not agree. For the first time it appears to take into real consideration the chance that, despite the silence of the relevant provisions, conduct that somehow rings of abuse may turn out to be objectively justified or even “redeemed” by efficiency advantages, to the ultimate benefit of consumers; the judgment makes it clear that formalistic taxonomies do not obtain any longer and cannot be resorted to as a tool for preserving “the way we were”. Starting all over again is never easy; but it is better than passively submitting to an unsustainable heritage.

Intel and the Tale of Rebates: The (More) Economic Approach to the Rescue!

In what should have been an exemplary case and a plea of an enforcement untamed and far away from the Chicago approach, the EU commission ruled, in 2009, that Intel, holding approximately a 70% share in the market for computer chips, in the period 2002-2007 abused its market power by putting in place essentially two types of conduct: (i) the first one consisting of the application of rebates to five major OEMs provided they were supplied by Intel for almost their entire chips requirements. In particular, Intel allegedly structured its price policy in order to assure that, if those manufacturers sourced their chips’ supplies also from other competing manufacturers, they would have lost in toto, or to a considerable extent, their right to obtain a rebate on the vast majority of their previous orders, therefore encouraging them to stock up exclusively from Intel itself; (ii) the second one consisting in offering payments to OEMs in order to induce them to delay, cancel or restrict the marketing of products based on the rival’s chipsets. The second act of this narrative dates 2014, when the General Court, in endorsing the Commission's ruling, showed an unexpected upsurge of formalistic stiffening and created a kind of sub-category within by object restrictions, which, irrespective of the (still feasible, but practically unworkable) proof of their objective justification in terms of efficiencies or rather benefits to consumers, would have been considered per se capable of producing exclusionary effects vis a vis competitors. The General Court was also lapidary in intimating that there was no need to apply quantitative economic methods as to verify the existence of an infringement. The ECJ, preceded by AG Wahl,did not agree. For the first time it appears to take into real consideration the chance that, despite the silence of the relevant provisions, conduct that somehow rings of abuse may turn out to be objectively justified or even “redeemed” by efficiency advantages, to the ultimate benefit of consumers; the judgment makes it clear that formalistic taxonomies do not obtain any longer and cannot be resorted to as a tool for preserving “the way we were”. Starting all over again is never easy; but it is better than passively submitting to an unsustainable heritage.

Ablative Pyrolysis of Wood Chips: Effect of Operating Conditions

AbstractWe pyrolyzed entire wood chips (5×15 mm) in a new ablative reactor with the goal to evaluate the possibility to minimize grinding costs before pyrolysis. The effects of the operating parameters on the product yields and composition were investigated. Our results revealed that the bio‐oil yield in the ablative reactor was favored at a moderate pyrolysis temperature of 500 °C, low initial thickness of the wood chips layer (≤5 mm), low applied pressure on the wood chips (≤0.5 bar), and with the rotation of the bowl (≥100 rpm). The temperature profile of the wood chips indicated that the ablative pyrolysis of thick layers is limited strongly by heat transfer rates. The maximum bio‐oil yield obtained was approximately 60 wt %. The bio‐oil elemental composition was determined mostly by its water content and that of char was affected primarily by the temperature. The knowledge of how operating conditions affect the ablative process can be used in the design of continuous mobile pyrolysis units in the future.

Integrated Circuit Cooling Using Heterogeneous Micropin-Fin Arrays for Nonuniform Power Maps

As microelectronic system density continues to increase, cooling with conventional technologies continues to become more challenging and is often a limiter of performance and efficiency. The challenge arises due to both large heat fluxes generated across entire chips and packages, and localized hotspots with even higher heat flux. In this paper, nonuniform micropin-fin heat sinks are investigated for the cooling of integrated circuits with nonuniform power maps. Four heterogeneous micropin-fin samples were fabricated and tested in single-phase experiments with deionized water to investigate the effectiveness of local micropin-fin clustering for the cooling of hotspots. Cylindrical and hydrofoil micropin-fins were tested, as well as two types of heterogeneous arrays: those with pin-fins clustered directly over the hotspot and those with the high density cluster spanning the entire width of the channel to prevent flow bypass around the cluster. Samples were tested with a uniform nominal heat flux of 250 W/cm2 as well as a hotspot heat flux of 500 W/cm2. Local micropin-fin clustering was found to be an effective method of reducing local thermal resistance with a modest pressure drop penalty.

Pyrolysis of whole wood chips and rods in a novel ablative reactor

The ability to carry out pyrolysis of entire wood chips and rods instead of small particles would be of great value for mobile pyrolysis units, because of the large possible savings in grinding costs (7–9% of total process costs). With this goal in mind, we designed and constructed a novel lab-scale ablative reactor for fast pyrolysis of entire wood chips and even wood rods, converting those directly into a high yield of bio-oil for the first time. The bio-oil yield from fast pyrolysis of wood chips (10×20mm) was as high as 60wt.%, similar to that from wood crumbles (2×2mm). Additionally, the yield and composition of bio-oil from ablative pyrolysis were in the same range as those obtained from a fluidized bed reactor using <1mm particles, with the small differences (slightly lower yield and HHV, and higher water content) attributed to the longer vapor residence times in the ablative reactor, which promote secondary reactions. We modeled the heat transfer characteristics of this semi-batch system, and comparison with experimental measurements confirmed that radiation from the hot components does not significantly decompose the wood prior to direct contact with the hot metallic surface in ablative pyrolysis. The findings of this work have the potential to lead to new developments for small-scale, mobile pyrolysis units for the disposal of forest residues.

Edge-Controlled Mechanical Failure of Si and SiC Semiconductor Chips†

Silicon (Si) and silicon carbide (SiC) semiconductor chips are subjected to thermal gradients during service, have coefficient of thermal expansion mismatches with the constituents they are attached to, and are therefore subjected to thermomechanical tensile stresses that can initiate their fracture. Because of inherent brittleness, their probabilistic (Weibull) tensile failure strength was examined to understand sustainable tensile stresses and any exhibition of strength-size-scaling. Failure stress testing of entire (10-mm-square) chips was conducted using uniaxial flexure (3-point-bending) and biaxial flexure (anticlastic bending). The advantage of the anticlastic bend test is all eight primary edges are subjected to identical sinusoidal stress distribution so tensile failure stress is concurrently sensitive to edge-state quality, surface-state quality, crystallographic orientation, and any strength anisotropies of any of those. Tensile stress tolerance of both Si and SiC chips was limited by extrinsic strength-limiting flaws located at their edges and on lapped surfaces too in the case of the Si. Both materials exhibited strength-size scaling; namely, a larger chip is likely to fail at a lower tensile stress. The anticlastic bend test method was effective for evaluating edge failure stress provided surface-type strength-limiting flaws were not dominant. Edge-strength anisotropy (i.e., crystallographic orientation dependence) was observed with both the Si and SiC chips. Surface-strength anisotropy also occurred with Si chips because one side was lapped and the other polished. Lastly, the SiC chips failed at much higher tensile stresses than Si chips; however, that strength difference could be a ramification of differences in edge-slicing quality and not necessarily from intrinsic material differences.

What is post-silicon debug?

Due to the complexity of modern IC designs and increasingly sophisticated manufacturing technologies, some of the steps in the design and optimization of ICs result in errors. A prime example of a design error is the Pentium IV FDIV bug --- a miscalculation when dividing certain rarely-occurring numbers, --- which resulted in the costly recalls of millions of CPUs in mid-1990s. Only rare errors escape extensive simulation used to verify designs, but they may jeopardize mission-critical applications and lead to class-action lawsuits. Some computer viruses escalate and exploit subtle hardware errors. Intel's response to the FDIV bug was to invest heavily in formal verification, so as to catch even the bugs that evade simulation. While very successful, this effort has always been limited to individual on-chip modules rather than entire chips. If bugs arising from the interaction between modules are not caught by extensive simulation, they show up in manufactured chips.

What is post-silicon debug?

Due to the complexity of modern IC designs and increasingly sophisticated manufacturing technologies, some of the steps in the design and optimization of ICs result in errors. A prime example of a design error is the Pentium IV FDIV bug --- a miscalculation when dividing certain rarely-occurring numbers, --- which resulted in the costly recalls of millions of CPUs in mid-1990s. Only rare errors escape extensive simulation used to verify designs, but they may jeopardize mission-critical applications and lead to class-action lawsuits. Some computer viruses escalate and exploit subtle hardware errors. Intel's response to the FDIV bug was to invest heavily in formal verification, so as to catch even the bugs that evade simulation. While very successful, this effort has always been limited to individual on-chip modules rather than entire chips. If bugs arising from the interaction between modules are not caught by extensive simulation, they show up in manufactured chips.

In Brief

Baruch Blumberg, winner of the 1976 Nobel Prize for Physiology or Medicine and director of NASA’s Astrobiology Institute, was appointed as senior adviser to NASA Administrator Daniel S. Goldin in October. In this capacity, Blumberg will help NASA’s newly created Office of Biological and Physical Research to develop an interdisciplinary research program that will bring together physics, chemistry, biology, and engineering. He will also continue as director of the institute. Robert H. Romer, editor of the American Journal of Physics since 1 June 1988, will be retiring on 30 June both as editor and as a professor of physics at Amherst College. Following his retirement, he plans to go “back to the lab,” he says. Jan Tobochnik, a professor of physics and computer science at Kalamazoo College, will take over the editorship on 1 July.This year’s Feynman Prize in Nanotechnology (Theoretical) and Feynman Prize in Nanotechnology (Experimental) were awarded this past November at the eighth Foresight Conference on Molecular Nanotechnology in Bethesda, Maryland, in recognition of “major advances in the ability to build useful devices and structures with atomic precision,” according to the Foresight Institute, which sponsors the prize. The theoretical prize went to Uzi Landman, Regents and Institute Professor of Physics and Fuller E. Callaway Chair at the Georgia Institute of Technology, for “his pioneering work in computational materials science for nanostructures. Such computer modeling provides deep insights into the nature and properties of matter at the nanoscale, and is essential in predicting what could be built at the molecular level, reducing time spent on expensive ‘wet’ lab experiments.” The experimental prize went to the multidisciplinary team of R. Stanley Williams, director of the Quantum Science Research Laboratory at HP Labs in Palo Alto, California; Philip Kuekes, a senior scientist in the Quantum Science Research Laboratory; and James Heath, professor of chemistry and biochemistry at UCLA. They were cited for “building a molecular switch, a major step toward their long-term goal of building entire memory chips that are just a hundred nanometers wide, smaller than a bacterium.”© 2001 American Institute of Physics.

Sequential test generation and synthesis for testability at the register-transfer and logic levels

The problem of test generation for nonscan sequential VLSI circuits is addressed. A novel method of test generation that efficiently generates test sequences for stuck-at faults in the logic circuit by exploiting register-transfer-level (RTL) design information is presented. The approach is targeted at circuits with highly connected state transition graphs (STGs) as in data paths, but explicit use is not made of the STG. The efficacy of the method stems from the use of the RTL description and good heuristics. The authors have successfully generated tests for entire chips with large numbers of latches within reasonable amounts of CPU time and have obtained maximum fault coverage. The algorithms require significantly smaller times than other test generators. A synthesis procedure that produces an optimized, fully testable logic implementation of a sequential circuit from a RTL description of the sequential circuit is also described. Datapath-controller circuits as well as digital signal processors whose STGs are very large, can be synthesized. The problem of synthesis of sequential logic for testability is also addressed. >

Registration techniques on warpage wafer for eb direct writing

AbstractIn the manufacture of integrated circuits by electron‐beam direct writing technique, the pattern shift caused by wafer warpage has been corrected by placing the reference mark on entire chips on the wafer and registration has been made for each chip. In the model experiment proposed in this paper, the number of registrations can be reduced significantly if model points are defined on the wafer. The pattern shift can be estimated for the entire wafer surface by the cubic interpolation method using model points and registration results.A high‐voltage, high‐current MOSFET has been realized as a new type of power transistor. Major problems in the development were how to increase the breakdown voltage and how to reduce the on‐resistance. The latter arises from the series resistance in the gate offset region, which is employed to obtain a high breakdown voltage. A structure with a “field‐plate” overhanging the gate electrode is proposed to reduce the series resistance and to increase the breakdown voltage. A one‐dimensional analysis of this structure is given.Important consequences of the field‐plate are that the ion‐implemented region underneath it is pinched‐off and that the pinch‐off voltage can be kept low even at ion‐implementation dosage high enough to reduce the series resistance. Both p‐channel and n‐channel power MOSFET's have been fabricated. Maximum current of 10 A, a drain breakdown voltage of 200 V, and a transconductance of 1 S have been obtained.A theoretical consideration has been given to the performance comparison between the MOSFET and bipolar transistor as power devices based on their operation principles. It is shown that the MOSFET has good prospects in high‐power, high‐speed applications due to its inherent thermal stability and better switching characteristics, but there is still room for technological improvement in its transconductance and on‐resistance.