Enhancement-mode High Electron Mobility Transistors Research Articles

High performance 12 GHz enhancement-mode pseudomorphic HEMT prepared by He plus reactive ion etching

An enhancement-mode pseudomorphic high electron mobility transistor using optimum reactive ion etching (RIE) technology without damaging 2-D channel has been developed, at the first time. By using the optimum RIE recipe, the selectivity between GaAs and AlGaAs is more than 150. In addition, the maximum transconductance of the device with the dimension of 300 μm×0.4 μm reaches 235 ms/mm at V ds=1.4 V. Furthermore, at 12 GHz, the output power and gain can achieve 17.9 dBm and 14.03 dB respectively. Operating at 12 GHz, the noise figure at V ds=4 V is down to 0.65 dB which is comparable to low noise depletion-mode device.

Enhancement-Mode InGaAs/InAlAs/InP High Electon Mobility Transistor with 0.1 µm Gate

We present state-of-the-art performance of 0.1 µm gate enhancement-mode (E-mode) InGaAs/InAlAs/InP high electron mobility transistors (HEMTs) fabricated on 3-inch wafers in a production environment. The E-mode HEMTs have transconductance of 1180 mS/mm, cutoff frequency of 210 GHz, and less than 1 mA/mm Idss (drain current at a gate bias of zero volts), measured at a drain bias of 1 V. The device characteristics make the E-mode HEMTs suitable candidates for ultra-high-speed analog and digital applications. Enhancement-mode HEMT devices and low noise amplifiers utilizing E-mode HEMTs, which were fabricated on 3-inch wafers in TRW's InP production line, demonstrated excellent repeatability, performance, yield, and uniformity.

InP-based enhancement-mode pseudomorphic HEMT with strained In/sub 0.45/Al/sub 0.55/As barrier and In/sub 0.75/Ga/sub 0.25/As channel layers

Using strained aluminum-rich In/sub 0.45/Al/sub 0.55/As as Schottky contact materials to enhance the barrier height and indium-rich In/sub 0.75/Ga/sub 0.25/As as channel material to enhance the channel performance, we have developed InP-based enhancement-mode pseudomorphic InAlAs/InGaAs high electron mobility transistors (E-PHEMT's) with threshold voltage of about 170 mv. A maximum extrinsic transconductance of 675 mS/mm and output conductance of 15 mS/mm are measured respectively at room temperature for 1 μm-gate-length devices, with an associated maximum drain current density of 420 mA/mm at gate voltage of 0.9 V. The devices also show excellent rf performance with cutoff frequency of 55 GHz and maximum oscillation frequency of 62 GHz. To the best of the authors' knowledge, this is the first time that InP-based E-PHEMT's with strained InAlAs barrier layer have been demonstrated.

Highly Stable Device Characteristics of InP-Based Enhancement-Mode High Electron Mobility Transistors with Two-Step-Recessed Gates

High-performance 0.1-µm-gate InP-based enhancement-mode high electron mobility transistors (E-HEMTs) were fabricated using two-step-recessed-gate technology, where the gate recess etching is first carried out by wet-chemical etching to removed n+-cap layers and then by Ar plasma etching to remove the InP etch stopper layer. Etching selectivies for both steps are sufficient not to degrade the uniformity of the device characteristics. The main advantage over the conventional approach for E-HEMTs, Pt-based-gate technology, is the fact that the stability of the threshold voltage is improved by means of a refractory gate metal, WSiN. The change in the threshold voltage is only 50 mV after 160-h bias and thermal stress at 195°C.

Enhancement-mode high electron mobility transistors (E-HEMTs) lattice-matched to InP

The fabrication and characterization of high-speed enhancement-mode InAlAs/InGaAs/InP high electron mobility transistors (E-HEMTs) have been performed. The E-HEMT devices were made using a buried-Pt gate technology. Following a Pt/Ti/Pt/Au gate metal deposition, the devices were annealed in a nitrogen ambient, causing the bottom Pt layer to sink toward the channel. This penetration results in a positive shift in threshold voltage. The dc and RF performance of the devices has been investigated before and after the gate annealing process. In addition, the effect of the Pt penetration was investigated by fabricating two sets of devices, one with 25 nm of Pt as the bottom layer and the other with a 5.0 nm bottom Pt layer. E-HEMTs were fabricated with gate lengths ranging from 0.3 to 1.0 /spl mu/m. A maximum extrinsic transconductance (g/sub mext/) of 701 mS/mm and a threshold voltage (V/sub T/) of 167 mV was measured for 0.3 /spl mu/m gate length E-HEMTs. In addition, these same devices demonstrated excellent subthreshold characteristics as well as large off-state breakdown voltages of 12.5 V. A unity current-gain cutoff frequency (f/sub t/) of 116 GHz was measured as well as a maximum frequency of oscillation (f/sub max/) of 229 GHz for 0.3 /spl mu/m gate-length E-HEMTs.

Millimetre Wave Signal Generation Using Monolithic HEMTTechnologies

We have designed, processed and tested monolithic 40GHz frequency doublers and amplifiers using enhancement and depletion HEMT processes. The passive parts included microstrip, coplanar waveguide and lumped component circuits. The on-chip measured output power of frequency doublers at 40GHz was p2 dBm and the conversion loss was 2–5 dB. The EHEMT doublers operated at low input power level from a single DC supply and the CPW passive parts enabled economical design. The integrated system of depletion PHEMT doubler and amplifier chips enclosed in hermetic packages delivered p10 dBm output power at 38GHz frequency band. This is the first time that the application of enhancement mode HEMTs in frequency doublers is reported and compared to the performance with depletion mode HEMTs. We have proven that EHEMT and DHEMT frequency multiplier circuits are efficient solutions for local oscillator use in modern millimetre wave systems.

Fabrication and characterization of an InAlAs/InGaAs/InP ring oscillator using integrated enhancement- and depletion-mode high-electron mobility transistors

The fabrication and characterization of an 11-stage ring oscillator utilizing integrated enhancement- and depletion-mode (E/D-mode) high-electron mobility transistors (HEMT's) in the lattice-matched InAlAs/InGaAs/InGaAs material system is demonstrated. The 0.5-μm gate length depletion-mode HEMT's (D-HEMT's) used in the circuit exhibit a threshold voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> ) of -365 mV with a standard deviation of 19 mV, while the enhancement-mode HEMT's (E-HEMT's) with identical gate length display a V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> of 195 mV with a standard deviation of only 9 mV. The unity current gain cutoff frequency (f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> ) for both devices is 70 GHz. The extremely high uniformity of the threshold voltages of these devices allowed for the implementation of a ring oscillator utilizing direct coupled FET logic (DCFL). At a supply voltage of 0.4 V, a room temperature propagation delay time (/spl tau//sub pd/) of 22.4 ps/stage, and a corresponding power dissipation of 120 μW/stage is measured, yielding a power delay product (PDP) of 2.65 fJ/stage. To the best of the authors knowledge, this is the first demonstration of a circuit employing E/D-HEMT technology in the lattice-matched InP-based material system.

High performance enhancement mode high electronmobility transistors (E-HEMTs) lattice matched to InP

The fabrication of 1.0 /spl mu/m gate length enhancement mode high electron mobility transistors (E-HEMTs) in the lattice matched InAlAs/InGaAs/InP material system is reported. Typical device DC characteristics include a threshold voltage of 275 mV, transconductance of 650 mS/mm, output conductance of 7.0 mS/mm, and an off-state breakdown voltage of 16 V. The devices exhibited excellent RF performance with an f/sub t/ of 35 GHz and an f/sub max/ of 80 GHz. For the first time, a process for E-HEMTs lattice matched to InP suitable for circuit applications is presented.

High-performance InP-based enhancement-mode HEMTs using non-alloyed ohmic contacts and Pt-based buried-gate technologies

High performance InP-based InAlAs/InGaAs enhancement-mode HEMT's are demonstrated using two improved approaches to device structure design and fabrication, i.e., nonalloyed ohmic contacts and Pt-based buried-gate technologies, to reduce the source resistance (R/sub S/). With specially designed cap layer structures, nonalloyed ohmic contacts to the device channel were obtained providing contact resistance as low as 0.067 /spl Omega//spl middot/mm. Furthermore, in device fabrication, a Pt-based buried-gate approach is used in which depletion-mode HEMTs are first intentionally fabricated, and then, the Pt-based gate metal is annealed at 250/spl deg/C, causing the Pt-InAlAs reaction to take place under the gate electrode so that Pt sinks into InAlAs and depletes the channel. As a result, the depletion-mode HEMTs are changed to enhancement-mode, while the channel region between the source and gate electrodes remain undepleted, and therefore, the small R/sub S/ of 0.2 /spl Omega//spl middot/mm can be maintained. Excellent maximum transconductance of 1170 mS/mm was obtained for a 0.5-/spl mu/m-gate device. A maximum current-gain cutoff frequency f/sub T/ of 41.2 GHz and maximum unilateral power-gain cutoff frequency f/sub max/ of 61 GHz were demonstrated for a 0.6-/spl mu/m-gate enhancement-mode HEMT.

Improved source resistance in InP-based enhancement-modeHEMTs for high speed digital applications

A new approach to reducing the source resistance in InP-based InAlAs-InGaAs enhancement-mode HEMTs is developed using Pt-based buried-gate technology. Source resistance as small as 0.2 Omega mm is obtained, which results in an excellent transconductance of 1170 mS/mm for a 0.5 mu m long gate enhancement-mode HEMT.

A 45 K-gate HEMT array with 35-ps DCFL and 50-ps BDCFL gates

A 45 K-gate emitter-coupled-logic (ECL)-compatible array with unbuffered and buffered direct-coupled FET-logic (DCFL and BDCFL) gates has been developed using 0.6- mu m-gate high-electron-mobility transistors (HEMTs) and four-level gold-based interconnects. The high-speed DCFL gates and more functional BDCFL gates are used to replace ECL macros efficiently. The basic cell, equivalent to four three-input NOR gates, consists of 12 enhancement-mode (E-mode) HEMTs, four depletion mode (D-mode) HEMTs, and two source-follower buffers. The basic gate delay times are 35 ps for 0.24-mW unbuffered DCFL gates and 50 ps for 0.38-mW BDCFL gates. The gate array chip is 9.8*9.8 mm and contains 45600 gates. The chip dissipates 11 W in 80% gate use. Silylated polymethyl silsequioxane (PMSS), which has a low dielectric constant of 3, is used for the interlayer dielectrics to reduce wiring delay.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Pseudomorphic n-InGaP/InGaAs/GaAs grown by MOVPE for HEMT LSIs

InGaP/InGaAs/GaAs heterostructures were grown by atmospheric pressure MOVPE. Excellent uniformity was obtained for doping concentration, thickness, and composition of the epitaxial layers by rotating the substrate and cooling the inner tube. The optimum gas switching sequence for achieving sufficient mobility and sheet carrier concentration was found. Enhancement-mode and depletion-mode HEMTs were fabricated using the very thin InGaP layer as an etching stopper layer. These are essential for the fabrication of HEMT LSI circuits. The discrete devices do not exhibit I–V collapse at low temperature. Short channel effects are negligible for gate lengths as small as 0.15 μm, owing to good carrier confinement in the pseudomorphic quantum well channel and a high aspect ratio under the thin n-InGaP layer. These advantages make InGaP/InGaAs/GaAs heterostructures well suited to HEMT LSIs applications.

High mobility electrons in selectively doped GaAs/n-AlGaAs heterostructures grown by MBE and their application to high-speed devices

Quasi-two-dimensional electron gas accumulating at the heterojunction interface in selectively doped GaAs/n-Al x Ga 1- x As ( x ≈ 0.3) grown by MBE was found to show extremely high mobilities of 8030 cm 2/V ·s at 300 K, 117,000 cm 2/V ·s at 77 K, and 244,000 cm 2/V ·s at 5 K. The mobility attained at 5 K is higher than any reported so far for MBE-grown semiconductor materials. Enhancement-mode high electron mobility transistors (E-HEMTs) have been fabricated from the heterostructures. An E-HEMT with a large gate ( L G = 350 μm) showed a field effect mobility as high as 59,000 cm 2/V ·s at 77 K. Furthermore, an E-HEMT with a small gate ( L G = 2 μm) exhibited transconductance as high as 193 mS/mm at room temperature and 409 mS/mm at 77 K; the latter is, to our knowledge, the highest transconductance ever reported for field effect transistors.

The present status of modulation-doped and insulated-gate field-effect transistors in III–V semiconductors

A review of recent and current work on modulation-doped and insulated-gate field-effect transistors is presented. Deep depletion-mode GaAs IGFETs have achieved satisfactory microwave performance, while inversion-mode devices are not feasible at present. Other materials such as InP and InGaAsP have advantages for inversion-mode IGFETs. High electron mobility transistors (HEMT) have realized field-effect control of the high mobility electrons in modulationdoped GaAs/ n- Al x G 1/ t- x As single heterojunction structures. Mobility variation with carrier concentration and undoped Al x Ga 1− x As spacer thickness is briefly discussed. Logic performance obtained with enhancement-mode HEMTs is also presented.