Enhancement-mode High Electron Mobility Transistors Research Articles

Performance improvement of enhancement-mode GaN-based HEMT power devices by employing a vertical gate structure and composite interlayers*

In this work, p-n junction vertical gate (JVG) and polarization junction vertical gate (PVG) structures are for the first time proposed to improve the performance of GaN-based enhancement-mode (E-mode) high electron mobility transistor (HEMT) devices. Compared with the control group featuring the vertical gate structure, a highly improved threshold voltage (V th) and breakdown voltage (BV) are achieved with the assistance of the extended depletion regions formed by inserting single or composite interlayers. The structure dimensions and physical parameters for device interlayers are optimized by TCAD simulation to adjust the spatial electric field distribution and hence improve the device off-state characteristics. The optimal JVG-HEMT device can reach a V th of 3.4 V, a low on-state resistance (R on) of 0.64 mΩ cm2, and a BV of 1245 V, while the PVG-HEMT device exhibits a V th of 3.7 V, an R on of 0.65 mΩ cm2, and a BV of 1184 V, which could be further boosted when an additional field plate design is employed. Thus, the figure-of-merit value of JVG- and PVG-HEMT devices rise to 2.4 and 2.2 GW cm−2, respectively, much higher than that for the VG-HEMT control group (1.0 GW cm−2). This work provides a novel technical approach to realize higher-performance E-mode HEMTs.

Modeling of Enhancement Mode HEMT with Π-Gate Optimization for High Power Applications

This paper presents technology computer-aided design (TCAD) modeling of an enhancement-mode aluminum gallium nitride (AlGaN)/gallium nitride (GaN) high electron mobility transistor (HEMT) with extensive π-gate optimization for high-power and radio frequency (RF) applications. Effects of the gate voltages on threshold (Vth), transconductance (gm), breakdown voltage (VBR), cutoff frequency (fT), maximum frequency of oscillation (fmax) and minimum noise figure (NFmin) are systematically investigated with different gate structures (π–Shaped p-GaN MISHEMT, π–Shaped p-GaN HEMT, π–Gate HEMT). A comparative study demonstrates that π–Gate with additional p-GaN and insulating layer makes the device effectively operate in the enhancement mode having a threshold voltage (Vth) = 1.72 V with a breakdown voltage (VBR) = 341 V, exhibiting better gate control with maximum transconductance (gm,max) of 0.321 S/mm. In addition, the proposed device architecture with an optimized gate structure maintains a balance between a positive device threshold and a high breakdown voltage and achieves a better noise immunity with the minimum noise figure of 0.64 dB while operating at 10 GHz with a cutoff frequency (fT) of 33.4 GHz, and a maximum stable operating frequency (fmax) of 82.3 GHz. Moreover, the device achieved an outstanding Vth, gm,max, VBR, fT, fmax and NFmin making it suitable for high-power, high-speed electronics, and low-noise amplifiers.

Evaluation of advanced wide bandgap Semiconductor-based DC-DC converter for solar power tower tracker application

This paper studies and evaluates the advanced wide bandgap (WBG) semiconductor switches in DC drives system applied to a solar power tracker. Namely, Silicon Carbide (SiC)-based MOSFETs and Gallium Nitride (GaN)-based enhancement-mode high-electron-mobility transistors (E-HEMTs) are developed and implemented as a class E DC/DC converter while supplying a DC motor as a part of the Solar Power Tower (SPT) heliostat unit and tested under different loading conditions. Besides, a MATLAB simulation is presented to demonstrate the effectiveness of the drive system considering both indoor and outdoor to accomplish the harsh weather conditions in the Kingdom of Saudi Arabia. A SiC-based Class-E DC-DC converter has been designed, implemented, tested, and evaluated. In addition, a GAN-based DC-DC converter has been tested and evaluated in a complete DC drive system. For the sake of comparison, an identical Silicon- based class-E DC-DC converter is designed and implemented to be compared with the proposed WBG-based converters. The results demonstrate that the proposed technique for SPT drive reduces switching losses and increases the drive system efficiency without affecting the operating drive performance. It was also observed that the WBG converter is more efficient and suitable for high-temperature environments with less switching losses by 15% under an operating frequency of 20 kHz.

Cascaded Rectifiers for Energy Harvesting With a Wide Dynamic Power Range

This work presents a novel RF energy harvesting system at 2.45 GHz, operating over a wide dynamic RF range (44 dB), starting from ultra-low power. It consists of three rectification branches, each one optimized for a selected power interval, between <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$- 20\,\,\div \,\,+$ </tex-math></inline-formula> 24 dBm. Through an automatic distribution network, the incident RF power is routed to the most efficient rectification branch, with no need for external control circuits. The first branch is optimized for low-power conditions, in the range <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$- 20\,\,\div \,\,0$ </tex-math></inline-formula> dBm, and the second and third branches for 0 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\div $ </tex-math></inline-formula> 9 dBm and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$9~\div ~24$ </tex-math></inline-formula> dBm, respectively. For branch decoupling, an original strategy, based on the concurrent nonlinear design of power-dependent matching networks and self-powered switches, is used. To maximize each rectifier performance, Enhancement-mode High Electron Mobility transistors (HEMT) are adopted by means of the self-biasing mechanism. In this way, for any possible incoming RF power, only the most suitable rectifier path is active and the maximum RF-to-dc conversion efficiency is preserved. The system has been fabricated and tested demonstrating a conversion efficiency higher than 30% from −13 dBm to 24 dBm, with the lowest and highest measured dc output voltage of 0.1 and 13 V, respectively.

Enhancement-Mode HEMT Performance and Mitigating Delay Through Double-Heterojunction With Connect Channel Utilization for Trap Effect Reduction

Enhancement-Mode HEMT Performance and Mitigating Delay Through Double-Heterojunction With Connect Channel Utilization for Trap Effect Reduction

TCAD-based design and verification of the components of a 200 V GaN-IC platform

This paper describes the TCAD-based design and verification of the different components of a 200 V GaN-on-SOI integrated circuits (ICs) platform developed on 200 mm substrates. This platform comprises of depletion-mode (d-mode) MIS-HEMTs, and Gated-Edge-Termination Schottky barrier diodes (GET-SBDs) monolithically integrated in an enhancement-mode (e-mode) HEMT technology baseline. A variety of low-voltage analog/logic devices and passive components further supports the GaN ICs platform. Device simulations have been verified using measured low voltage test structures. Verification of simulations with the measurements results in calibration of sheet resistance (Rsh) in the gate and access region, threshold voltage (Vth), drain current (Ids), ON-resistance (RON), gate current (Ig) for HEMT structures, and turn-on voltage (VT) and forward voltage drop (VF) for GET-SBD structure.

High Performance Flip-Structure Enhancement-Mode HEMT with Face-to-Face Double Gates

A novel double gates flip-structure enhancement-mode (E-mode) high electron mobility transistor with step field plate (DFF HEMT) is proposed. It features face-to-face double gates, including a top trench MIS gate with a step field plate and a bottom planar MIS gate, which is shorted together. In the on-state, the double gates not only can restore the 2DEG by the higher electric potential, but also can form the electron accumulation layers, and thus increase the saturation output current and reduce the on-resistance. The face-to-face double gates together deplete the 2DEG by using the work function difference to realize E-mode, instead of by etching the AlGaN layer under the gate for the conventional MIS gate E-mode HEMT. The double-gate structure not only avoids etch damage, but also maintains both high threshold voltage and low on-resistance. Meanwhile, the step gate field plate modulates E-field distribution to increase the BV. In order to easily fabricate, the trench gate with step field plate must be located on the top of device, forming the flip-structure. The flip-structure is also beneficial to decrease the leakage current in the substrate. The simulated Vth, BV and Id of the DFF HEMT are 0.8 V, 465 V and 494 mA/mm, respectively. The FOM of the DFF HEMT is 79.8% and 444.2% higher than those of the conventional MIS-FP HEMT and MIS HEMT.

Interplay Between γ–Ray Irradiation and 3DEG for Dosimeter Applications

This work investigates the cumulative dose ⁶⁰Co gamma (<inline-formula> <tex-math notation="LaTeX">$\gamma$ </tex-math></inline-formula>) &#x2013; ray irradiation effects on enhancement mode HEMT devices inheriting 3D &#x2013; Electron and Hole Gases for dosimeter applications. The devices are irradiated through a ⁶⁰Co source and demonstrate the enhancement in the drain current metrics. To elucidate, the said devices were irradiated through different mechanisms and the Compton effect was investigated through contour plots via TCAD simulations. The degradation of Schottky Gate contact and insulator charging affects the 2D &#x2013; Hole Gas at the GaN cap and thereby affects the bottleneck at the 3DEG sheet. This significantly affects the OFF &#x2013; state leakage components of the said device and can therefore be exploited for potential use in sensing and dosimeter applications. The leakage components can be exploited further to improve the linearity of the dosimeter by considering different grading profiles of the AlGaN layer. In this regard, a workflow for optimizing the sensitivity and linearity of the dosimeter through different graded profiles is also presented. Amongst all, gaussian graded profiles have been identified as the best &#x2013; case scenario considering the sensitivity and exhibiting a linear operation.

Parallel connected GaN E‐HEMT VSI‐based servo drives for PMSMs

The operation of parallel-connected servo drives has the advantages of increasing the torque (hence the power) capacity, reliability, redundancy and modularity. However, smaller discrepancies of the system clocks of the independent microcontrollers, asynchronous pulse width modulation (PWM) carrier signals and hardware differences can make the output voltages of the parallel modules non-identical, which results in circulating currents. These circulating currents limit the parallel operation, introduce additional power dissipation, cause unbalanced power distribution and degrade the control performance. To eliminate the circulating currents separated DC supplies, coupled inductors (CIs), PWM techniques, modified control techniques etc. are proposed in the literature. In this study, a fault-tolerant parallel-connected gallium nitride enhancement-mode high electron mobility transistor voltage source inverter-based servo drive scheme that eliminates the need for CIs and separate DC supplies and also enables the use of a standard proportional-integral current control and a standard space vector PWM approach is proposed and tested. To evaluate the performances of the proposed scheme, up to six servo drives (limit-6 × 7 Arms) are connected in parallel and tested under various conditions with a 24 V permanent magnet synchronous motor (nominal-61.9 Arms). The results show that the parallel operation not only increases the torque capacity of the system but also increases modularity, flexibility, reliability and also redundancy.

Single Event Burnout Hardening of Enhancement Mode HEMTs With Double Field Plates

Single event burnout (SEB) of enhancement mode GaN high-electron mobility transistors (HEMTs) under heavy ion irradiation is systematically studied based on simulations in this work. Susceptibility to SEB of different particle incidence environments is investigated to determine the device's sensitive position. Under these conditions, the mechanism of SEB in enhancement mode HEMTs is mainly associated with the charge congestion and subsequent continuous impact ionization. A hardened HEMT structure with the gate and drain double field plates is proposed correspondingly. Apart from better output characteristics and almost 25% improvement of breakdown voltage, the hardened structure also demonstrates better tolerance of SEB. This hardened structure can modify the electric field in the high field region so that charge accumulation is reduced significantly, thus effectively decreasing the possibility of SEB's occurrence. With a vertical heavy ion strike of 63.8 MeV ·cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /mg linear energy transfer (LET), SEB threshold voltage of the conventional structure HEMT is 160 V, while that of the hardened structure HEMT is much higher, reaching 249 V. Besides, the hardened device exhibits better SEB tolerance than the conventional device even at different higher LET conditions. Furthermore, the contribution to SEB tolerance of each field plate is also discussed.

Influence of the carrier behaviors in p-GaN gate on the threshold voltage instability in the normally off high electron mobility transistor

Threshold voltage (VTH) instability has been studied in the as-fabricated p-GaN gated enhancement-mode high electron mobility transistors (p-GaN E-HEMTs) under a positive gate stress. A negative VTH shift (ΔVTH) obtained by dynamic measurement has been observed more severely when compared to the static one. The VTH deviation is attributed to the complicated influence of carrier transport behaviors in the p-GaN gate. The impacts of hole accumulation, trapping, and consumption on the VTH instability and drain current variation can be effectively distinguished according to the transfer characteristics obtained from the pulse I–V measurement. Moreover, the density of hole traps in the p-GaN gate is estimated to be around ∼2 × 1011 cm−2 by the capacitance–voltage measurement, and the energy level is calculated to be around EV + 0.62 eV by fitting the recovery curve of gate current after positive gate bias. This study focusing on the in-depth influence of different carrier behaviors on the gate performance can help with the understanding and further improvement of the dynamic instability and reliability of the GaN-based HEMTs.

Removal of GaN film over AlGaN with inductively coupled BCl3/Ar atomic layer etch

Atomic layer etching (ALE) of thin film GaN (0001) is reported in detail using sequential surface modification by BCl3 adsorption and removal of the modified surface layer by low energy Ar plasma exposure in a reactive ion etching system. The estimated etching rate of GaN is ∼ 0.74 nm/cycle. The GaN is removed from the surface of AlGaN after 135 cycles. To study the mechanism of the etching, the detailed characterization and analyses are carried out, including scanning electron microscope (SEM), x-ray photoelectron spectroscopy (XPS), and atomic force microscope (AFM). It is found that in the presence of GaCl x after surface modification by BCl3, the GaCl x disappears after having exposed to low energy Ar plasma, which effectively exhibits the mechanism of atomic layer etch. This technique enables a uniform and reproducible fabrication process for enhancement-mode high electron mobility transistors with a p-GaN gate.

Comprehensive GaN-on-Si power device platform: epitaxy, device, reliability and application

In this paper, we discuss possible solutions to overcome the critical issues for GaN-on-Si power device popularization including cost competitiveness to Si power MOSFETs, system level reliability verification, and electromagnetic interference (EMI) mitigation at high switching frequency without compromising the switching loss. Both an advanced epitaxy technology and a comprehensive power device technology platform of 200 mm GaN-on-Si high electron mobility transistors (HEMTs) for mass production are presented. A novel strain engineering is reported to realize enhancement-mode HEMTs with ultralow specific on-resistance. The Si based Joint Electron Device Engineering Council reliability test, Dynamic High Temperature Operating Life, and switching accelerated lifetime test were carried out to evaluate the device reliability and lifetime. It is proved that our GaN device is robust and stable in power conversion applications. A balancing technique to mitigate EMI of the high switching frequency GaN power converter is demonstrated.

Investigation of Normally-Off p-GaN/AlGaN/GaN HEMTs Using a Self-Terminating Etching Technique with Multi-Finger Architecture Modulation for High Power Application.

Normally-off p-gallium nitride (GaN) high electron mobility transistor (HEMT) devices with multi-finger layout were successfully fabricated by use of a self-terminating etching technique with Cl2/BCl3/SF6-mixed gas plasma. This etching technique features accurate etching depth control and low surface plasma damage. Several devices with different gate widths and number of fingers were fabricated to investigate the effect on output current density. We then realized a high current enhancement-mode p-GaN HEMT device with a total gate width of 60 mm that exhibits a threshold voltage of 2.2 V and high drain current of 6.7 A.

New investigation of an E-mode metal-insulator-semiconductor AlInN/AlN/GaN HEMT with an Au-T-gate

In a high electron mobility transistor (HEMT), the density of the two-dimensional electron gas (2DEG) channel is modulated by the application of a bias to a Schottky metal gate. These devices are depletion mode (D-mode), which means that a negative bias must be applied to the gate to deplete the electron channel and turn. The most challenging aspect in the present research activity on based-GaN devices is the development of a reliable way to achieve an enhancement-mode (E-mode) HEMT. Enhancement-mode GaN HEMTs would offer a simplified circuitry by eliminating the negative power supply. In this work, the aim is to investigate the different techniques which can influence the threshold voltage and shift it to a positive value. A novel E-mode metal-insulator-semiconductor (MIS) AlInN/GaN HEMT with an Au-T-gate has been investigated. The impacts of window-recess and deep-recess have been discussed, it was found that for dp=28 nm and wn=1.8 μm the threshold voltage achieves 0.7 V and the transconductance (Gm) peak value of 523 mS at Vgs=3.5 V. The drain current characteristic has been demonstrated.

Packaging and high-temperature characterization of a 650 V, 150 A eGaN HEMT

Among the salient features of gallium nitride (GaN) power semiconductor devices is their high-temperature capability. However, commercial GaN devices, such as the high-electron-mobility transistors (HEMTs), are limited to 125 °C junction-temperature operation because of their packaging. To explore the high-temperature capability of GaN power devices, a commercial 650 V, 150 A enhancement-mode GaN HEMT chip was packaged by silver-sintering die-bonding on direct-bond-copper substrate and encapsulation in a high-temperature polymer enclosure filled with nitrogen. Static characteristics of the packaged GaN device were measured at temperatures up to 250 °C. The threshold voltage of the transistor at 250 °C decreased to around 0.9 V, about 30% lower than that at room temperature. At temperatures beyond 150 °C, the saturation current fell sharply below the rated current, resulting in a rapid rise in the on-resistance versus current. At 250 °C, the saturation current decreased rapidly to around 67 A, <45% of the rated current. The reverse leakage also increased sharply at temperatures beyond 150 °C. Although the packaged device was operational at 250 °C, one would need to significantly lower the expectations for its performance and address the challenges of packaging and thermal management if it were to be used in a high-temperature power converter.

High-Performance AlGaN/GaN Enhancement-Mode High Electron Mobility Transistor by Two-Step Gate Recess and Electroless-Plating Approaches

In this work, an AlGaN/GaN enhancement-mode high electron mobility transistor (HEMT) with two-step gate recess and electroless plating (EP) approaches is reported. Scanning electron microscopy and atomic force microscopy surface analysis are used to analysis the related properties of the EP-gate structure. A positive threshold voltage Vthof 0.68 V is obtained for the enhancement-mode EP-HEMT. In addition, a traditional HEMT based on thermal-evaporation gate is compared for the demonstration of the studied EP-HEMT with the improved performance, such as a higher maximum drain saturation current of 228.9 mA/mm, a higher maximum transconductance of 107.2 mS/mm, a lower gate leakage current of 1.2 × 10–7 mA/mm, and a higher ON/OFF drain current ratio of 4.57 × 105.

Analysis and Characterization of Normally-Off Gallium Nitride High Electron Mobility Transistors

High electron mobility transistor (HEMT) based on gallium nitride (GaN) is one of the most promising candidates for the future generation of high frequencies and high-power electronic applications. This research work aims at designing and characterization of enhancement-mode or normally-off GaN HEMT. The impact of variations in gate length, mole concentration, barrier variations and other important design parameters on the performance of normally-off GaN HEMT is thoroughly investigated. An increase in the gate length causes a decrease in the drain current and transconductance, while an increase in drain current and transconductance can be achieved by increasing the concentration of aluminium (Al). For Al mole fractions of 23%, 25%, and 27%, within Al gallium nitride (AlGaN) barrier, the GaN HEMT devices provide a maximum drain current of 347, 408 and 474 mA/μm and a transconductance of 19, 20.2, 21.5 mS/μm, respectively. Whereas, for Al mole fraction of 10% and 15%, within AlGaN buffer, these devices are observed to provide a drain current of 329 and 283 mA/μm, respectively. Furthermore, for a gate length of 2.4, 3.4, and 4.4 μm, the device is observed to exhibit a maximum drain current of 272, 235, and 221 mA/μm and the transconductance of 16.2, 14, and 12.3 mS/μm, respectively. It is established that a maximum drain current of 997 mA/μm can be achieved with an Al concentration of 23%, and the device exhibits a steady drain current with enhanced transconductance. These observations demonstrate tremendous potential for two-dimensional electron gas (2DEG) for securing of the normally-off mode operation. A suitable setting of gate length and other design parameters is critical in preserving the normally-off mode operation while also enhancing the critical performance parameters at the same time. Due to the normally-on depletion-mode nature of GaN HEMT, it is usually not considered as suitable for high power levels, frequencies, and temperature. In such settings, a negative bias is required to enter the blocking condition; however, in the before-mentioned normally-off devices, the negative bias can be avoided and the channel can be depleted without applying a negative bias.

Tri-gate GaN junction HEMT

This work presents a tri-gate GaN junction high-electron-mobility transistor (JHEMT) concept in which the p–n junction wraps around the AlGaN/GaN fins in the gate region. This tri-gate JHEMT differs from all existing GaN FinFETs and tri-gate HEMTs, as they employ a Schottky or a metal-insulator-semiconductor (MIS) gate stack. A tri-gate GaN JHEMT is fabricated using p-type NiO with the gate metal forming an Ohmic contact to NiO. The device shows minimal hysteresis and a subthreshold slope of 63 ± 2 mV/decade with an on-off current ratio of 108. Compared to the tri-gate MISHEMTs fabricated on the same wafer, the tri-gate JHEMTs exhibit higher threshold voltage (VTH) and achieve positive VTH without the need for additional AlGaN recess. In addition, this tri-gate JHEMT with a fin width of 60 nm achieves a breakdown voltage (BV) &amp;gt; 1500 V (defined at the drain current of 1 μA/mm at zero gate bias) and maintains the high BV with the fin length scaled down to 200 nm. In comparison, the tri-gate MISHEMTs with narrower and longer fins show punch-through at high voltages. Moreover, when compared to planar enhancement mode HEMTs, tri-gate JHEMTs show significantly lower channel sheet resistance in the gate region. These results illustrate a stronger channel depletion and electrostatic control in the junction tri-gate compared to the MIS tri-gate and suggest great promise of the tri-gate GaN JHEMTs for both high-voltage power and low-voltage power/digital applications.

200°C/5 MHz GaN‐based gate driver circuits with 1 nF/4.7 Ω RC load for high‐temperature high‐frequency all‐GaN IC applications

A GaN-based gate driver circuits have been successfully designed and fabricated using a commercially available 6-inch GaN-on-Si platform. The driver circuits consist of three-stage direct-coupled FET logic (DCFL) inverters featuring monolithically integrated depletion-mode (D-mode) and enhancement-mode (E-mode) high electron mobility transistors (HEMTs). At room temperature (RT), at a supply voltage of 4 V the single-stage DCFL fabricated on the same die exhibits a large gate swing (3.84 V) and large noise margins (logic-low noise margin (NML) of 1.55 V and logic-high noise margin (NMH) of 2.18 V), both of which are desirable for all-GaN IC applications. Meanwhile, the gate driver circuits were characterised up to 200°C on a PCB with a capacitance load of 1 nF in series with 4.7 Ω resistance to resemble the load condition. At 200°C, the gate driver circuits function well even at 5 MHz operation frequency. The turn on/off propagation delay and rise/fall time of the gate driver circuits are 5/40 and 22/18 ns, respectively. As far as the authors’ knowledge, this is the highest reported operation frequency for GaN-based gate driver circuits under such high temperature, making it very promising for high-temperature high-frequency all-GaN integrated circuit (IC) applications.