Energy Efficient Spiking Neural Network Research Articles

All-Ferroelectric Spiking Neural Networks via Morphotropic Phase Boundary Neurons.

Artificial neurons and synapses are crucial for efficiently implementing spiking neural networks (SNNs) in hardware. The distinct functional requirements of artificial neurons and synapses present significant challenges in the implementation of area- and energy-efficient SNNs. This study reports an all-ferroelectric SNN system through co-optimization of material properties and device configurations using wafer-scale atomic layer deposition. For the first time, a double-gate (DG) morphotropic phase boundary-based thin-film transistor (MPBTFT) is utilized for a leaky integrate-and-fire (LIF) neuron. The DG MPBTFT-based LIF neuron eliminates the need for capacitors and reset circuits, thereby enhancing area and energy efficiency. The DG configuration demonstrates various neuronal functions with high reliability. Co-optimizing materials and devices significantly enhance the performance and functional versatility of artificial neurons and synapses. Meticulous material engineering facilitates the seamless co-integration of DG MPBTFT-based neurons, ferroelectric thin-film transistor (TFT)-based synapses, and normal TFTs on a single wafer. All-ferroelectric SNN systems achieved a high classification accuracy of 94.9%, thereby highlighting the potential of DG MPBTFT-based LIF neurons for advanced neuromorphic computing.

A superconducting synapse exhibiting spike-timing dependent plasticity

The recent success of artificial intelligence (AI) systems has been accompanied by a rapid increase in the computational resources needed to successfully train them. This rate of increase threatens the future development of AI systems as they are presently configured. Unsupervised learning, where systems are trained online instead of through offline computation, offers a possible way forward. Here, we present the design of a synaptic circuit made from superconducting electronics capable of spike-timing dependent plasticity (STDP), a form of unsupervised learning. The synapse is constructed from three sub-circuits, each responsible for a part of the synaptic action. We demonstrate the operation of the synapse through numerical simulation and show that it reproduces the hallmark behaviors of STDP. Combined with existing superconducting neuromorphic components like neurons and axons, this synaptic structure could help form a fast, powerful, and energy-efficient Spiking Neural Network.

An Area- and Energy-Efficient Spiking Neural Network With Spike-Time-Dependent Plasticity Realized With SRAM Processing-in-Memory Macro and On-Chip Unsupervised Learning.

In this article, we present a spiking neural network (SNN) based on both SRAM processing-in-memory (PIM) macro and on-chip unsupervised learning with Spike-Time-Dependent Plasticity (STDP). Co-design of algorithm and hardware for hardware-friendly SNN and efficient STDP-based learning methodology is used to improve area and energy efficiency. The proposed macro utilizes charge sharing of capacitors to perform fully parallel Reconfigurable Multi-bit PIM Multiply-Accumulate (RMPMA) operations. A thermometer-coded Programmable High-precision PIM Threshold Generator (PHPTG) is designed to achieve low differential non-linearity (DNL) and high linearity. In the macro, each column of PIM cells and a comparator act as a neuron to accumulate membrane potential and fire spikes. A simplified Winner Takes All (WTA) mechanism is used in the proposed hardware-friendly architecture. By combining the hardware-friendly STDP algorithm as well as the parallel Word Lines (WLs) and Processing Bit Lines (PBLs), we realize unsupervised learning and recognize the Modified National Institute of Standards and Technology (MNIST) dataset. The chip for the hardware implementation was fabricated with a 55 nm CMOS process. The measurement shows that the chip achieves a learning efficiency of 0.47 nJ/pixel, with a learning energy efficiency of 70.38 TOPS/W. This work paves a pathway for the on-chip learning algorithm in PIM with lower power consumption and fewer hardware resources.

A Spiking Neural Network with Adaptive Graph Convolution and LSTM for EEG-Based Brain-Computer Interfaces.

Electroencephalography (EEG) signals classification is essential for the brain-computer interface (BCI). Recently, energy-efficient spiking neural networks (SNNs) have shown great potential in EEG analysis due to their ability to capture the complex dynamic properties of biological neurons while also processing stimulus information through precisely timed spike trains. However, most existing methods do not effectively mine the specific spatial topology of EEG channels and temporal dependencies of the encoded EEG spikes. Moreover, most are designed for specific BCI tasks and lack some generality. Hence, this study presents a novel SNN model with the customized spike-based adaptive graph convolution and long short-term memory (LSTM), termed SGLNet, for EEG-based BCIs. Specifically, we first adopt a learnable spike encoder to convert the raw EEG signals into spike trains. Then, we tailor the concepts of the multi-head adaptive graph convolution to SNN so that it can make good use of the intrinsic spatial topology information among distinct EEG channels. Finally, we design the spike-based LSTM units to further capture the temporal dependencies of the spikes. We evaluate our proposed model on two publicly available datasets from two representative fields of BCI, notably emotion recognition, and motor imagery decoding. The empirical evaluations demonstrate that SGLNet consistently outperforms existing state-of-the-art EEG classification algorithms. This work provides a new perspective for exploring high-performance SNNs for future BCIs with rich spatiotemporal dynamics.

A Cost-Efficient High-Speed VLSI Architecture for Spiking Convolutional Neural Network Inference Using Time-Step Binary Spike Maps.

Neuromorphic hardware systems have been gaining ever-increasing focus in many embedded applications as they use a brain-inspired, energy-efficient spiking neural network (SNN) model that closely mimics the human cortex mechanism by communicating and processing sensory information via spatiotemporally sparse spikes. In this paper, we fully leverage the characteristics of spiking convolution neural network (SCNN), and propose a scalable, cost-efficient, and high-speed VLSI architecture to accelerate deep SCNN inference for real-time low-cost embedded scenarios. We leverage the snapshot of binary spike maps at each time-step, to decompose the SCNN operations into a series of regular and simple time-step CNN-like processing to reduce hardware resource consumption. Moreover, our hardware architecture achieves high throughput by employing a pixel stream processing mechanism and fine-grained data pipelines. Our Zynq-7045 FPGA prototype reached a high processing speed of 1250 frames/s and high recognition accuracies on the MNIST and Fashion-MNIST image datasets, demonstrating the plausibility of our SCNN hardware architecture for many embedded applications.

Energy efficient spiking neural network processing using approximate arithmetic units and variable precision weights

Spiking neural networks (SNNs) have been getting more research attention in recent years as the way they process information is suitable for building neuromorphic systems effectively. However, realizing SNNs on hardware is computationally expensive. To improve their efficiency for hardware implementation, a field-programmable gate array (FPGA) based SNN accelerator architecture is proposed and implemented using approximate arithmetic units. To identify the minimal required bit-width for approximate computation without any performance loss, a variable precision method is utilized to represent weights of the SNN. Unlike the conventional reduced precision method applied to all weights uniformly, the proposed variable precision method allows different bit-widths to represent weights and provide the feasibility of maximizing truncation effort for each weight. Four SNNs adopting different network configurations and training datasets are established to compare the performance of proposed accelerator architecture using the variable precision method with the proposed one using the conventional reduced precision method. Based on the experimental results, more than 40% of the weights require less bit-width when applying the variable precision method instead of the reduced precision method. With the variable precision method, the proposed architecture achieves 28% fewer ALUTs and 29% less power consumption than the proposed one using the reduced precision method.

RANC: Reconfigurable Architecture for Neuromorphic Computing

Neuromorphic architectures have been introduced as platforms for energy efficient spiking neural network execution. The massive parallelism offered by these architectures has also triggered interest from non-machine learning application domains. In order to lift the barriers to entry for hardware designers and application developers we present RANC: a Reconfigurable Architecture for Neuromorphic Computing, an open-source highly flexible ecosystem that enables rapid experimentation with neuromorphic architectures in both software via C++ simulation and hardware via FPGA emulation. We present the utility of the RANC ecosystem by showing its ability to recreate behavior of the IBM's TrueNorth and validate with direct comparison to IBM's Compass simulation environment and published literature. RANC allows optimizing architectures based on application insights as well as prototyping future neuromorphic architectures that can support new classes of applications entirely. We demonstrate the highly parameterized and configurable nature of RANC by studying the impact of architectural changes on improving application mapping efficiency with quantitative analysis based on Alveo U250 FPGA. We present post routing resource usage and throughput analysis across implementations of Synthetic Aperture Radar classification and Vector Matrix Multiplication applications, and demonstrate a neuromorphic architecture that scales to emulating 259K distinct neurons and 73.3M distinct synapses.

Approximate Digital Leaky Integrate-and-fire Neurons for Energy Efficient Spiking Neural Networks

Inherent error resilience in neuromorphic computing allows remarkable power and energy savings by exploiting approximate computing. This paper presents approximate digital leaky integrate-and-fire (LIF) neurons that leverage the approximate adders for energy efficient spiking neural networks (SNNs). Various approximate adder architectures were assessed and adopted in designing a digital LIF neuron. To demonstrate the performance of the approximate LIF neurons, a two-layer SNN with more than 1,000 digital neurons were used with the approximate adders. The results showed that the approximation errors of the lower-part OR adder (LOA) and optimized lower-part constant OR adder (OLOCA) do not affect the neuron’s spiking activities of the network significantly. In addition, they showed good power and energy efficiency. The results suggest that the LOA and OLOCA are more suitable for SNNs to achieve power- and energyefficient neuromorphic computing than the other approximate adders.

A Low-Power Actor-Critic Framework Based on Memristive Spiking Neural Network

Traditional deep reinforcement learning (DRL) algorithms consume much energy. Energy-efficient spiking neural networks (SNNs) are promising technologies to bulid a low-power reinforcement learning architecture. In this paper, an actor-critic framework based on memrisitive SNN is proposed. To convey and process information in SNN, spike encoding and decoding systems are created. Then, an improved learning algorithm based on spike-timing-dependent plasticity (STDP) learning rule is designed to combine actor-critic method with SNN. Moreover, this learning algorithm is also hardware-friendly. Besides, memristive synapse is designed to accelerate this learning algorithm. Finally, a continuous control problem is applied to illustrate the effectiveness of the proposed framework. The results show the proposed framework is prior to traditional methods.

A Sub-35 pW Axon-Hillock artificial neuron circuit

Artificial Intelligence (AI) applications are developing at a high rate, facing soon a tremendous energy challenge. In this context, the original Axon-Hillock (AH) Artificial Neuron (AN) has been optimized to achieve ultra-low power (ULP) consumption. The membrane capacitance was taken out, and in order to drastically reduce its power consumption, the (feedback) capacitance is lowered to 5 fF, the transistors gate width is reduced to 120 nm and the supply voltage is decreased to as low as 200 mV. Designed and fabricated using 65 nm CMOS Technology, the refined AH neuron features a standby power of 11 pW, and when excited, a power consumption that does not exceed 30 pW for a firing frequency of 15.6 kHz. Its energy efficiency per spike is lower than 2 fJ/spike when the DC power is included (around 1 fJ/spike excluding the DC power), for an area of 31 µm2. These performance confer to this ULP AH neuron a high potential for future development of highly energy efficient Spiking Neural Networks, required to design future neuroprocessors embedded in various applications (smart visual sensors for autonomous vehicles, robotics).

Deep neural networks with weighted spikes

Abstract Spiking neural networks are being regarded as one of the promising alternative techniques to overcome the high energy costs of artificial neural networks. It is supported by many researches showing that a deep convolutional neural network can be converted into a spiking neural network with near zero accuracy loss. However, the advantage on energy consumption of spiking neural networks comes at a cost of long classification latency due to the use of Poisson-distributed spike trains (rate coding), especially in deep networks. In this paper, we propose to use weighted spikes, which can greatly reduce the latency by assigning a different weight to a spike depending on which time phase it belongs. Experimental results on MNIST, SVHN, CIFAR-10, and CIFAR-100 show that the proposed spiking neural networks with weighted spikes achieve significant reduction in classification latency and number of spikes, which leads to faster and more energy-efficient spiking neural networks than the conventional spiking neural networks with rate coding. We also show that one of the state-of-the-art networks the deep residual network can be converted into spiking neural network without accuracy loss.