Energy-efficient Information Processing Research Articles

Design and Demonstration of an Adiabatic-Quantum-Flux-Parametron Field-Programmable Gate Array Using Josephson-CMOS Hybrid Memories

Adiabatic quantum-flux-parametron (AQFP) logic is a promising technology for future energy-efficient high-performance information processing systems. Its static power is zero because of ac flux bias, and its dynamic power is considerably reduced, thanks to the adiabatic switching of the junctions. The lack of high-density memories in the AQFP logic, however, makes it challenging to realize large-scale information processing systems with the use of pure AQFP circuits. We have been developing a Josephson-CMOS hybrid memory to overcome the memory bottleneck in AQFP digital systems. By utilizing the high sensitivity of the AQFP gate, the output current from CMOS memories can be significantly decreased resulting in the reduction of the power consumption. In this article, we designed and fabricated a low-power area-efficient AQFP-CMOS hybrid field-programmable gate array (FPGA), where a CMOS memory is utilized as a rewritable read-only memory to control the AQFP circuits. The AQFP circuit for the AQFP-CMOS hybrid FPGA is composed of logic blocks, switch blocks, and connection blocks, which are clocked by four-phase excitation currents. The AQFP-CMOS hybrid FPGA is fabricated by using the AIST 10 kA/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> Nb high-speed standard process and the Rohm 0.18 μm CMOS process. The area and power consumption of the two-by-two AQFP logic-cell system are estimated to be approximately 6.56 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and 12.4 nW at 5 GHz operations, respectively. The power consumption of the CMOS memory was estimated to be 1.02 μW assuming the CMOS source voltage of 3 mV. We demonstrated the operation of the AQFP-CMOS hybrid FPGA at low speed by combining the AQFP logic and the CMOS memory.

Human action recognition with a large-scale brain-inspired photonic computer

The recognition of human actions in video streams is a challenging task in computer vision, with cardinal applications in e.g. brain-computer interface and surveillance. Deep learning has shown remarkable results recently, but can be found hard to use in practice, as its training requires large datasets and special purpose, energy-consuming hardware. In this work, we propose a scalable photonic neuro-inspired architecture based on the reservoir computing paradigm, capable of recognising video-based human actions with state-of-the-art accuracy. Our experimental optical setup comprises off-the-shelf components, and implements a large parallel recurrent neural network that is easy to train and can be scaled up to hundreds of thousands of nodes. This work paves the way towards simply reconfigurable and energy-efficient photonic information processing systems for real-time video processing.

Energy Efficient Temporal Spatial Information Processing Circuits Based on STDP and Spike Iteration

In this brief, we propose a novel energy-efficient temporal-spatial information processing circuit that serves as the signal pre-processing interface for spiking neural networks. In order to transform sensory information into a highly efficient neural-like spike train, an iteration encoding scheme based temporal-spatial inter-spike interval (ISI) encoder is designed and analyzed. Moreover, a decoder is designed with the spike-timing-dependent plasticity (STDP) principle, which performs well in information recovery. The prototype of the proposed ISI encoder is presented, with a 3-interval encoder through the standard 180nm CMOS technology. The proposed ISI encoder could operate in $1{MHz}$ sampling frequency, and it occupies merely $0.647{m}{m}^{2}$ die area while consuming as low as $1.63{uW}$ /neuron power. A multi-level ISI decoder with spike width adaptation is also designed and evaluated through the CIFAR10 image dataset.

Miniaturization of adiabatic quantum-flux-parametron circuits by adopting offset buffers

Adiabatic quantum-flux-parametron (AQFP) logic is one of the most promising superconductor logic families as a candidate to achieve future energy-efficient high-performance information processing systems. The static power of AQFP logic is zero because of ac flux bias, and the switching energy is ∼zJ at 5 GHz due to adiabatic switching. In this study, we propose a design method using offset buffers to reduce the dimension of AQFP circuits; in particular, we focus on the reduction in the horizontal dimension (which is parallel to excitation current) because in AQFP circuits the horizontal dimension tends to be greater than the vertical dimension (which is perpendicular to excitation current). Offset buffers are buffers with offset input signals. The use of offset buffers enables us to eliminate constant cells (which generate constant 0 s and 1 s) from some logic gates, so that the horizontal dimension of logic gates such as AND and OR gates can be significantly reduced. We designed AND and OR gates with offset buffers, and demonstrated them with wide operating margins. Then, we designed and demonstrated a 4–16 decoder using the AND gate with an offset buffer. We found that the horizontal dimension and area of a 4–16 decoder can be reduced by 33% and 26%, respectively, via the use of offset buffers.

Triplon band splitting and topologically protected edge states in the dimerized antiferromagnet

Search for topological materials has been actively promoted in the field of condensed matter physics for their potential application in energy-efficient information transmission and processing. Recent studies have revealed that topologically invariant states, such as edge states in topological insulators, can emerge not only in a fermionic electron system but also in a bosonic system, enabling nondissipative propagation of quasiparticles. Here we report the topologically nontrivial triplon bands measured by inelastic neutron scattering on the spin-1/2 two-dimensional dimerized antiferromagnet Ba2CuSi2O6Cl2. The excitation spectrum exhibits two triplon bands that are clearly separated by a band gap due to a small alternation in interdimer exchange interaction, consistent with a refined crystal structure. By analytically modeling the triplon dispersion, we show that Ba2CuSi2O6Cl2 is the first bosonic realization of the coupled Su-Schrieffer-Heeger model, where the presence of topologically protected edge states is prompted by a bipartite nature of the lattice.

Transition Metal Dichalcogenide-Based Field-Effect Transistors for Analog/Mixed- Signal Applications

Transition metal dichalcogenides (TMDs), such as MoS2, MoSe2, MoTe2, WS2, WSe2, etc., have been considered as the most promising candidates for energy-efficient information processing at ultrascaled devices due to their decent energy gap of around 1–2 eV and single-atomic thickness. Even though there are many efforts to explore their performance for digital applications, their performance considerations for analog/mixed-signal applications are still unexplored. In this regard, we have assessed the analog/RF performance of TMD-based field-effect transistors (TMD-FETs) and investigated their benefits over graphene-FET and black phosphorous-FETs. The performance analysis is done by an in-house developed code, which involves the self-consistent solutions of 2-D Poisson’s equation and nonequilibrium Green’s function (NEGF) formalism. The results show that MoS2-FET can offer high intrinsic gain with the intrinsic cutoff frequency and maximum oscillation frequency in terahertz range. However, the significant degradation in high-frequency performance of MoS2-FET is observed in the presence of external resistances and parasitic capacitances. The cutoff frequency has found a few hundreds of gigahertz range in the presence of all parasitic conditions. It has also found that, among TMD-FETs, WSe2-FET could be a promising candidate for analog/RF integrated circuits with a higher drive current, intrinsic gain, cutoff frequency, and maximum oscillation frequency.

Spatially Arranged Sparse Recurrent Neural Networks for Energy Efficient Associative Memory.

The development of hardware neural networks, including neuromorphic hardware, has been accelerated over the past few years. However, it is challenging to operate very large-scale neural networks with low-power hardware devices, partly due to signal transmissions through a massive number of interconnections. Our aim is to deal with the issue of communication cost from an algorithmic viewpoint and study learning algorithms for energy-efficient information processing. Here, we consider two approaches to finding spatially arranged sparse recurrent neural networks with the high cost-performance ratio for associative memory. In the first approach following classical methods, we focus on sparse modular network structures inspired by biological brain networks and examine their storage capacity under an iterative learning rule. We show that incorporating long-range intermodule connections into purely modular networks can enhance the cost-performance ratio. In the second approach, we formulate for the first time an optimization problem where the network sparsity is maximized under the constraints imposed by a pattern embedding condition. We show that there is a tradeoff between the interconnection cost and the computational performance in the optimized networks. We demonstrate that the optimized networks can achieve a better cost-performance ratio compared with those considered in the first approach. We show the effectiveness of the optimization approach mainly using binary patterns and apply it also to gray-scale image restoration. Our results suggest that the presented approaches are useful in seeking more sparse and less costly connectivity of neural networks for the enhancement of energy efficiency in hardware neural networks.

Nanomagnetic Particle-Based Information Processing

Understanding the physics of spintronic devices in the 3-nm size range can pave the way to next-generation energy-efficient information processing devices. To build a spin computer, a layer of 3-nm CoFe 2 O 4 nanoparticles was sandwiched as a central layer into the standard spin-transfer torque magnetic tunneling junction (STT-MTJ) stack. With further focused ion beam (FIB) trimming, a dual-layer junction consisting of one or more nanoparticles separating two CoFeB ferromagnetic layers was turned into a two-terminal spintronic device. The measured room-temperature electron transport through the device showed a staircase effect reminiscent of a single electron transport, which in addition depended on the relative orientations of the magnetic states of the ferromagnetic layers and the high-anisotropy ferrimagnetic nanoparticle. Besides having the staircase steps, the V-I curve indicated switching of the nanoparticles magnetization through the STT effect at currents of above 0.05 uA. The magnetoresistance (MR) curve of this device with the magnetic field applied perpendicular to the junction had an anomalous oscillatory field dependence in a relatively low field range of below 100 Oe.

Tailoring coupling between light and spin waves with dual photonic–magnonic resonant layered structures

We report on judiciously designed stratified periodic structures of magnetic dielectric materials with a localized defect layer, which are able to concurrently confine light and spin waves in the same ultra-small defect region for a long time period, thus resulting in enhanced photon–magnon interaction and large dynamic optical frequency shift. Our results for a specific realization of such a one-dimensional, so-called photomagnonic, crystal magnetized at saturation perpendicular to the interfaces, obtained by means of rigorous calculations using scattering-matrix techniques, show that the inherently weak coupling between visible/near-infrared light and GHz-frequency spin waves can be greatly increased leading to strong modulation of the optical field through multi-magnon exchange mechanisms. Such novel multifunctional composite materials offer a promising platform for tailoring light–spin-wave coupling in view of fast and energy-efficient spin-optical information processing applications.

Thermally Tunable Hybrid Photonic Architecture for Nonlinear Optical Circuits

Integrated photonic systems are a leading solution for fast and energy-efficient information processing. We develop a thermally tunable hybrid photonic platform for implementation of coherent optical networks applicable to dedicated computing and machine learning. The hybrid architecture comprises gallium arsenide (GaAs) photonic crystal cavities, silicon nitride (SiNx) grating couplers and waveguides, and chromium (Cr) microheaters on an integrated photonic chip. We utilize the band-edge nonlinearity in GaAs photonic crystal cavity for switching at 6 ps time scale. The cavities are evanescently connected to a common bus waveguide, separating the computation and communication layers. To synchronize the operating frequency, we design metal microheaters that locally, continuously, and reversibly tune photonic crystal cavities to a common resonance. We demonstrate 7 nm tunability range with no significant quality factor deterioration. By coupling the free-space light to the photonic chip, we demonstrate the ...

Cross-layer efforts for energy-efficient computing: towards peta operations per second per watt

As Moore’s law based device scaling and accompanying performance scaling trends are slowing down, there is increasing interest in new technologies and computational models for fast and more energy-efficient information processing. Meanwhile, there is growing evidence that, with respect to traditional Boolean circuits and von Neumann processors, it will be challenging for beyond-CMOS devices to compete with the CMOS technology. Exploiting unique characteristics of emerging devices, especially in the context of alternative circuit and architectural paradigms, has the potential to offer orders of magnitude improvement in terms of power, performance, and capability. To take full advantage of beyond-CMOS devices, cross-layer efforts spanning from devices to circuits to architectures to algorithms are indispensable. This study examines energy-efficient neural network accelerators for embedded applications in this context. Several deep neural network accelerator designs based on cross-layer efforts spanning from alternative device technologies, circuit styles, to architectures are highlighted. Application-level benchmarking studies are presented. The discussions demonstrate that cross-layer efforts indeed can lead to orders of magnitude gain towards achieving extreme-scale energy-efficient processing.

Topological Magnon Modes in Patterned Ferrimagnetic Insulator Thin Films.

Manipulation of magnons opens an attractive direction in the future energy-efficient information processing devices. Such quasi-particles can transfer and process information free from the troublesome Ohmic loss in conventional electronic devices. Here, we propose to realize topologically protected magnon modes using the interface between the patterned ferrimagnetic insulator thin films of different configurations without the Dzyaloshinskii-Moriya interaction. The interface thus behaves like a perfect waveguide to conduct the magnon modes lying in the band gap. These modes are immune to backscattering even in sharply bent tracks, robust against the disorders, and maintain a high degree of coherence during propagation. We design a magnonic Mach-Zehnder interferometer, which realizes a continuous change of magnon signal with varying external magnetic field or driving frequency. Our results pave a new way for realizing topologically protected magnon waveguide and finally achieving a scalable low-dissipation spintronic devices and even the magnonic integrated circuit.

Quantum control of topological defects in magnetic systems

Energy-efficient classical information processing and storage based on topological defects in magnetic systems have been studied over past decade. In this work, we introduce a class of macroscopic quantum devices in which a quantum state is stored in a topological defect of a magnetic insulator. We propose non-invasive methods to coherently control and readout the quantum state using ac magnetic fields and magnetic force microscopy, respectively. This macroscopic quantum spintronic device realizes the magnetic analog of the three-level rf-SQUID qubit and is built fully out of electrical insulators with no mobile electrons, thus eliminating decoherence due to the coupling of the quantum variable to an electronic continuum and energy dissipation due to Joule heating. For a domain wall sizes of $10-100$~nm and reasonable material parameters, we estimate qubit operating temperatures in the range of $0.1-1$~K, a decoherence time of about $0.01-1$~$\mu$s, and the number of Rabi flops within the coherence time scale in the range of $10^{2}-10^{4}$.

The Weird, the Small, and the Uncontrollable: Redefining the Frontiers of Computing

Several potential avenues exist for redefining the frontiers of computing through nontraditional paradigms. Although none of these paradigms is currently competitive with CMOS-based technology, they have the potential for cheaper, faster, more robust, and more energy-efficient information processing.

A learnable parallel processing architecture towards unity of memory and computing.

Developing energy-efficient parallel information processing systems beyond von Neumann architecture is a long-standing goal of modern information technologies. The widely used von Neumann computer architecture separates memory and computing units, which leads to energy-hungry data movement when computers work. In order to meet the need of efficient information processing for the data-driven applications such as big data and Internet of Things, an energy-efficient processing architecture beyond von Neumann is critical for the information society. Here we show a non-von Neumann architecture built of resistive switching (RS) devices named “iMemComp”, where memory and logic are unified with single-type devices. Leveraging nonvolatile nature and structural parallelism of crossbar RS arrays, we have equipped “iMemComp” with capabilities of computing in parallel and learning user-defined logic functions for large-scale information processing tasks. Such architecture eliminates the energy-hungry data movement in von Neumann computers. Compared with contemporary silicon technology, adder circuits based on “iMemComp” can improve the speed by 76.8% and the power dissipation by 60.3%, together with a 700 times aggressive reduction in the circuit area.

Innovative energy resourceful merged layer technique (MLT) of node deployment to enhance the lifetime of wireless sensor networks

A wireless sensor network (WSN) is consisting of anthology of large number of small sensor nodes which are deployed in a defined area to observe the surroundings parameters. Since, energy consumption is significant challenge in WSN. As sensor nodes are equipped with battery which has limited energy. Energy efficient information processing is most importance for many routing protocols were proposed to increase the lifetime of WSN. In order to improve the lifetime of WSN, the proposed MLT routing protocol has implemented where the sensor nodes are randomly deployed in the field. The merged layer node deployment pattern of the sensor nodes system operation maximizes the working time of full coverage in a given WSN. MLT provides energy-balancing while selecting cluster head (CH) for each round. The cluster head selection mechanism is essential and has same procedure like Low Energy Adaptive Clustering Hierarchy (LEACH) in MLT protocol. The main idea of this paper is combine two layers of sensor nodes which are belonging to the same set but in different group to improve the lifetime of WSN. MATLAB simulations are performed to analyze and compare the performance of MLT with LEACH protocol. The obtained simulation output has enhanced results and superfluous lifetime compared to other protocols.

A hybrid CPU-FPGA system for high throughput (10Gb/s) streaming document classification

Processing large volumes of information in real time requires large amounts of computational power, which consumes a significant amount of energy. With the rise in the amount of data produced, energy-efficient high-performance information processing systems are becoming a necessity. We present a hybrid CPU-FPGA system for high-throughput classification of streams of textual documents (e.g. emails or web pages). The current system parses the document stream using a multicore CPU and performs classification on the parsed stream using Field-Programmable Gate Arrays (FPGAs). As an example, we demonstrate a Naive Bayes classifier on the TREC Aquaint dataset. Our current solution can classify 10Gb/s internet traffic in real time. Our aim is to increase the throughput to 100Gb/s by incorporating the parser into the FPGA design.

Dual pillar spin torque nano-oscillator

We present a Dual Pillar Spin Torque Nano Oscillator (DP-STNO) suitable for energy efficient information processing. The proposed DP-STNO consists of a low resistance Giant Magneto-Resistance path that allows ultra-low voltage biasing of the oscillating ferromagnetic-free-layer, and a high resistance Tunneling Magneto-Resistance path that provides amplified RF-signal and facilitates easy sensing mechanism. The free-layers of multiple DP-STNOs can be coupled through dipolar-fields to accomplish complex signal processing tasks, like edge-extraction from an image, with high energy efficiency.

Multiple purpose spin transfer torque operated devices

We summarize our recent work on a non-volatile logic building block required for energy-efficient information processing systems. A sequential logic device, in particular, an alternative non-volatile magnetic flip-flop has been introduced. Its properties are investigated and its extension to a very dense shift register is demonstrated. We show that the flip-flop structure inherently exhibits oscillations and discuss its spin torque nano-oscillator properties.

Analysis Study Of Time Synchronization Protocols In Wireless Sensor Networks

One of the main pervasive problems Wireless Sensor Networks(WSN) encounter is to maintain flawless communication sharing and cooperative processingbetweensensors via radio links to ensure a reliable treatment of information. Many applications based on these WSNs consider local clocks at each sensor node that need to be synchronized to a common notion of time. In this context, the majority of previous researches were focused on the study of protocols, and algorithms that address these issues in order to resolve synchronization problems. Previous fforts and empirical studies in wireless sensor network (WSN) proposed several solutions (algorithms). The focus of this this paperis to examine and evaluate the most important synchronization algorithms based on thepositionsof variousquantitative and qualitative synchronization protocolsfor energy-efficient information processing and routing in WSNs.