Energy-efficient Architecture Research Articles

Optimizing support vector regression using grey wolf optimizer for enhancing energy efficiency and building prototype architecture

Optimizing support vector regression using grey wolf optimizer for enhancing energy efficiency and building prototype architecture

Edge Computing: Opportunities and Challenges

Edge computing has emerged as an innovative paradigm, promising to reshape the landscape of computational processing by bringing data closer to the source of generation, namely Internet of Things (IoT) devices. As the proliferation of IoT devices surges, so does the need for efficient, low-latency processing. Edge computing addresses these demands by decentralizing computational tasks, optimizing bandwidth, and ensuring rapid data processing. This paper delves into the nuances of edge computing, highlighting its distinct advantages, particularly in latency reduction and bandwidth conservation. However, with these opportunities come challenges, notably in the domain of security. Through a systematic review and simulation-based experimentation, this research affirms the transformative potential of edge computing, while also underscoring the need for robust security frameworks. The study concludes with a forward-looking perspective, emphasizing areas of future research including security enhancements, integration with 5G technology, energy-efficient architectures, and cross-domain applications.

Historical development of passive optical network (PON): a review

Abstract Communication networks are forced to transition to optical access networks in order to boost the information rate of transmission due to huge utilization of internet. Passive optical networks (PONs) are a highly developed and promising technology that offers low cost design, high bandwidth, and information rate for both residential and commercial use. PON uses the passive components incorporating couplers, splitters, as well as combiners. Compared to modern access networks, PON features bidirectional capabilities, cost-effectiveness, high resource efficiency, transparency, privacy, flexibility, along with upgradeability. Due to these ever increasing demands for high bandwidth, high capacity, and long reach communication for next generation networks, next generation passive optical networks (NG-PONs) are optimum choice. It provides cost-effective, energy efficient network architecture and can be realized in integrated wired/wireless network scenarios for fronthaul/backhaul data transmissions. This paper reviews the standardization process of PON that led to the development of the NG-PON. The detail literature review of various technologies related to PON and NG-PON has been conducted. Potential drawbacks of NG-PON as well as the advantages and disadvantages of various strategies are also discussed besides the future scope. Meanwhile it offers long haul high bandwidth hybrid scenarios. The futuristic PON networks may be realized for high undersea, satellite, and beyond sixth generation (6G) networks.

Electrohydraulic musculoskeletal robotic leg for agile, adaptive, yet energy-efficient locomotion

Robotic locomotion in unstructured terrain demands an agile, adaptive, and energy-efficient architecture. To traverse such terrains, legged robots use rigid electromagnetic motors and sensorized drivetrains to adapt to the environment actively. These systems struggle to compete with animals that excel through their agile and effortless motion in natural environments. We propose a bio-inspired musculoskeletal leg architecture driven by antagonistic pairs of electrohydraulic artificial muscles. Our leg is mounted on a boom arm and can adaptively hop on varying terrain in an energy-efficient yet agile manner. It can also detect obstacles through capacitive self-sensing. The leg performs powerful and agile gait motions beyond 5 Hz and high jumps up to 40 % of the leg height. Our leg’s tunable stiffness and inherent adaptability allow it to hop over grass, sand, gravel, pebbles, and large rocks using only open-loop force control. The electrohydraulic leg features a low cost of transport (0.73), and while squatting, it consumes only a fraction of the energy (1.2 %) compared to its conventional electromagnetic counterpart. Its agile, adaptive, and energy-efficient properties would open a roadmap toward a new class of musculoskeletal robots for versatile locomotion and operation in unstructured natural environments.

A Extensive Review of Recent Technologies and Trends in Low-Power VLSI Design

The demand for energy-efficient electronic devices has driven significant advancements in low-power Very-Large-Scale Integration (VLSI) design. This paper presents a Extensive review of the recent technologies and trends that have emerged to address the challenges associated with power utilization in VLSI circuits. The review covers a broad spectrum of innovations, including advanced transistor technologies such as FinFETs, Gate-All-Around (GAA) FETs, and Silicon-on-Insulator (SOI), which offer improved power efficiency. It also explores cutting-edge power enhance techniques like Dynamic Voltage and Frequency Scaling (DVFS), power gating, and Multi-Threshold CMOS (MTCMOS), highlighting their impact on reducing both dynamic and leakage power. Further, the paper examines energy-efficient architectures, including Near-Threshold Computing (NTC), approximate computing, and asynchronous circuits, which promise substantial power savings. The fusing of machine learning and AI in power optimization and the development of advanced Electronic Design Automation tools are also discussed as emerging trends. Finally, the paper considers future directions, including the potential of 3D Integrated Circuits (3D ICs), quantum and neuromorphic computing, and post-CMOS technologies, to revolutionize low-power VLSI design. This review provides a critical exploration of the actual state of the art and offers comprehensions into the future trajectory of low-power VLSI, making it a valuable resource for researchers and practitioners in the field.

An Investigation on Handling IoT Big Data with RBSEE Architecture

Internet of Things (IoT) devices have resulted in an unprecedented surge in data generation, presenting both opportunities and challenges in data management and analytics. This paper investigates the feasibility and effectiveness of utilizing the RBSEE (Resource-Based Storage, Edge Computing, and Elasticity) architecture for handling IoT Big Data. Firstly, the paper elucidates the fundamental concepts of IoT and Big Data, highlighting the unique characteristics and challenges associated with managing large volumes of heterogeneous data streams generated by IoT devices. Subsequently, it introduces the RBSEE architecture, which integrates resource-based storage, edge computing, and elasticity to address the scalability, latency, and resource constraints inherent in IoT environments. The architecture's ability to distribute data storage and processing tasks across edge devices and cloud infrastructure while dynamically adapting to fluctuating workloads makes it particularly suitable for handling IoT Big Data. In any typical IoT ecosystem, real-time and instantaneous handling of request and dataset is pivotal and a fundamental property. This aims to propose energy efficient distributed system architecture for persuasive, privacy-preserved and real time handling of data generated from IoT devices.

Levy flight based momentum search and Circle Rock Hyrax swarm optimization algorithms for energy effective clustering and optimal routing in wireless body area networks

In recent years, the connectivity of a new dimension has been brought to Wireless Body Area Networks (WBANs) through the concept of the Wearable Internet of Things (WIoT). WIoT offers valuable functionalities like data collection, analysis, and transmission for real-time health monitoring services. However, WBANs are characterized by a large number of battery-powered sensor nodes, making them resource-constrained. While keeping standard WSN abilities, WBAN's significant obstacles are data communication, social mobility, high interference in dense deployment, latency, and energy consumption of sensor nodes. As a result, the implementation and design of an application require dependable data transfer and an energy-efficient architecture. It proved critical to have as little delay as possible while delivering correct data. To overcome these issues, this study developed a novel energy-efficient clustered and optimized routing scheme in WBAN. Due to its effective scalability, this work employs an Improved Self-Executing Active Cross-Propagated (ISAC) clustering approach to form clusters in Wireless Body Area Networks (WBANs). Subsequently, the selection of the best Cluster Heads (CHs) is facilitated by the Levy Flight-based Momentum Search Algorithm (LFMSA). The Circle Rock Hyrax Swarm Optimization (CRH) algorithm is then utilized for energy-efficient routing. In determining the CH in each cluster, consideration is given to both residual energy and connectivity. The proposed framework minimizes the number of transmissions and overall transmission distance, optimizing inter and intra-cluster transmission distances. Additionally, the framework ensures energy-efficient packet delivery from CHs to the sink node. Performance comparisons, conducted using various statistical measures and simulated on the NS-2 platform, demonstrate that the proposed framework outperforms existing routing protocols and clustering methodologies. In comparison to previous methodologies, the proposed framework consistently achieves superior results.

Next-generation electronic devices: Innovations in integrated circuits, sensors, and computing architectures

This paper delves into the forefront of electronic engineering, showcasing the evolution of integrated circuits (ICs), sensor technology advancements, and the latest enhancements in microprocessors and microcontrollers. It underscores the significant strides made towards miniaturization, energy efficiency, and the integration of high-performance computing (HPC) within these devices. Through detailed examination, the paper highlights three pivotal areas: the revolutionary fabrication techniques enabling nanometer-scale ICs; the emergence of nano-sensing devices, wireless sensor networks (WSNs), and flexible sensors transforming the landscape of environmental monitoring and healthcare; and the development of energy-efficient architectures and security enhancements in microprocessors and microcontrollers. Employing quantitative analyses and mathematical models, the paper provides insights into the technological breakthroughs driving these advancements, including dynamic voltage and frequency scaling (DVFS), near-threshold computing (NTC), and the implementation of hardware-based security measures [1]. This comprehensive analysis not only illuminates the current state of electronic engineering but also outlines the potential future directions of the field, emphasizing the interdisciplinary approaches required to tackle the challenges of modern electronic device design and application.

Evaluating Passive Housing Strategies in Extreme Climates: A Case Study of Dubai Using PHPP and IESVE Models

The increasing global emphasis on sustainable architecture necessitates precise building energy modeling, especially in regions marked by extreme climates. The focus of this study is to evaluate the potential and practicality of passive housing strategies in climates similar to Dubai. In this study, we employed the Passive House Planning Package (PHPP) to create a meticulous representation of the Dubai environmental conditions, ensuring that detailed architectural elements and HVAC systems were captured to provide the most energy-efficient architecture. To validate the accuracy of the model, consumption data from 2020 was used as a benchmark, reflecting the observed hot water and electricity consumption. Additionally, we developed a linear state-space model using IES Virtual Environment software (IESVE) to capture the dynamic thermal behaviour of the proposed building. We assessed the merits of the Passivhaus model in harsh climates and compared them with those of various space calculation methodologies. The model showed significant congruence with the actual consumption data and external temperature metrics for 2020. Furthermore, the state-space model, along with its various state variables, inputs, and outputs, aligned well with the real-world observations. The results indicate that the Passivhaus model possesses significant potential to reduce carbon emissions, highlighted by a detected 10% variance in energy consumption during the simulated summer peak. Differences in space calculation methodologies were also determined, emphasising the necessity of context-driven architectural evaluation. This study provides invaluable insights into the energy dynamics of contemporary buildings and emphasises the transformative potential of passive housing in extreme climates.

Energy Efficient and Reliable High Quality Video Transmission Architecture for Wireless Sensor Networks

Energy Efficient and Reliable High Quality Video Transmission Architecture for Wireless Sensor Networks

Low complexity, high throughput, energy efficient, pipelined and reconfigurable ASIC realization architecture for multi-layer perceptron models

There has been continuously growing research interest in Artificial Neural Networks (ANNs) due to their vast acceptance in many real-world applications. This has led to the appearance of a variety of realization methods for multilayer perceptron (MLP) inference models. In this paper, we propose a generalized 3-stage, configurable, multiplier-less, massive parallel realization architecture for MLP inference models. We use offset binary coded distributive arithmetic (OBC-DA), which uses LUTs to reduce hardware requirements, to realize internal computing units of MLPs. The designing efforts to achieve a reduction in resource requirements are two-fold; (i) reduction in LUT size itself, which is achieved by exploiting symmetry induced by OBC-DA and thereby reducing LUT size by 50%, and (ii) reduction in total number of LUTs which is attained by sharing the LUTs. The resource efficiency of the proposed architecture is further improved by decomposing the LUTs into parallel and smaller LUTs. Moreover, the resource efficiency is also enhanced by utilizing the symmetry among the inputs in the MLP layer. The ASIC synthesis results for underlying MLPs establish that the proposed method for the realization of MLPs is much more efficient than the earlier reported methods and coincides with the findings of the generalized hardware-timing complexities.

Reconstruction of buildings of the first mass series according to green construction standards

The relevance of the research topic is due to the need to introduce systemic solutions into practice to create an environmentally sustainable and energy efficient urban environment. Over the past decades, there has been an urgent need to reconstruct the housing stock according to architectural, urban planning and construction requirements. Based on the results of the author’s scientific research, the fundamental possibility of reconstruction of 5-storey brick buildings of the first mass series according to green construction standards is shown. The results obtained convincingly indicate that the reconstruction of buildings of the first mass series according to the green standard GOST 70346—2022 allows improving almost all green categories. The quality of the architecture and layout of the site, energy efficiency and quality of the atmosphere, and the level of innovation in sustainable development are especially noticeably increasing. Before the reconstruction, the buildings of the first mass series do not meet the requirements of green construction. After the reconstruction of these buildings, a rating of “good” was obtained. Comparison of results obtained according to independent green standards GOST 70346—2022 and STO NOSTROY 2.35.4—2011 shows their consistency. Thus, the reconstruction of buildings of the first mass series according to green construction standards makes it possible to create a fundamentally new, environmentally sustainable, energy-efficient architecture in order to preserve and improve the quality of the environment for future generations.

Area–time–energy efficient architecture of CBNS‐based fast Fourier transform

AbstractA new approach for implementing the fast Fourier transform (FFT) using complex binary number system (CBNS) is presented in this paper. The advantage of using CBNS is that instead of processing the real and imaginary parts of a complex number separately, we can process both as a single entity. A total of four FFT architectures have been developed, which are 16‐, 64‐, 256‐, and 1024‐point FFT architectures. The proposed FFT is designed using Verilog‐HDL and implemented using a Virtex‐7 field‐programmable gate array (FPGA). The maximum clock rate achieved by the proposed FPGA‐based design is 376.1 MHz. The FPGA resource utilization of the FFT is less than the state‐of‐the‐art FFT designs. An application‐specific integrated circuit (ASIC) for the FFT is also designed. The normalized energy per FFT of the proposed ASIC is 0.14 nJ, and the normalized area per FFT of the ASIC is 1.08 mm2 which is less than other existing designs.

Energy efficiency in architecture: Strategies and technologies

Energy efficiency in architecture is a critical consideration in the design and construction of buildings, aiming to reduce energy consumption and minimize environmental impact. This abstract explores various strategies and technologies that can be implemented to enhance energy efficiency in architecture. The importance of energy efficiency in architecture lies in its potential to reduce greenhouse gas emissions, lower energy costs, and create healthier indoor environments. Achieving energy efficiency in architecture involves a combination of passive design strategies, such as orientation, shading, and natural ventilation, as well as active technologies, including high-performance insulation, energy-efficient lighting, and renewable energy systems. Passive design strategies are fundamental to energy-efficient architecture, utilizing the natural elements of sunlight, shade, and airflow to minimize the need for mechanical heating, cooling, and lighting. Proper building orientation, effective shading devices, and strategic placement of windows and openings can maximize natural light and ventilation, reducing the reliance on artificial lighting and mechanical ventilation systems. In addition to passive design strategies, active technologies play a crucial role in enhancing energy efficiency in architecture. High-performance insulation materials, such as aerogel and vacuum insulation panels, can significantly reduce heat loss and gain through building envelopes, improving thermal comfort and reducing energy consumption. Energy-efficient lighting systems, such as light-emitting diodes (LEDs) and daylight harvesting systems, can reduce electricity usage for lighting, while renewable energy systems, such as solar photovoltaic panels and wind turbines, can generate clean energy on-site, further reducing reliance on fossil fuels. Overall, energy efficiency in architecture requires a holistic approach that considers both passive design strategies and active technologies. By incorporating these strategies and technologies into building design and construction, architects and designers can create buildings that are not only environmentally sustainable but also comfortable, healthy, and cost-effective for occupants.

Negative capacitance FET based dual-split control 6T-SRAM cell design for energy efficient and robust computing-in memory architectures

A Negative Capacitance Field effet transistor (NCFET) based Dual split control (DSC) 6T-SRAM cell has been designed and explored with Computing-in memory (CiM) architecture for energy efficient demonstration of Deep neural networks (DNN) basic operation such as Input-Weight (Dot) Product. The impact of ferro electric layer thickness (Tfe) on the SRAM cell perfomance metrics such as read noise margin (RNM), write noise margin (WNM) and energy efficiency for read and write operations have been analyzed at supply voltages of 0.3 V and 0.5 V. It has been observed that due to the steep slope characteristics, the NCFET based DSC 6T-SRAM cell design exhibits better RM, WM, and energy efficiency as compared to the baseline CMOS DSC SRAM cell design at VDD = 0.3 V and 0.5 V respectively (with Tfe range of 1 nm to 3 nm). Further, NCFET dual split control scheme for 6T-SRAM cell demonstrate improved read stability and write ability when compared with NCFET 6 T-SRAM cell design along with improved energy efficiency. NCFET based DSC 6T-SRAM CiM cell design has ∼22.77× and 12.41× lower energy consumption compared to the équivalent baseline 40 nm CMOS/baseline SRAM CiM design and ∼ 25.80× and 22.76× lower energy consumption compared to the NCFET based SRAM CiM at VDD = 0.3 V and 0.5 V respectively. NCFETs have improved steep subthreshold slope characteristics at an optimal Tfe value and NCFET SRAM based CiM circuits are expected to have higher noise margins and lower energy consumption compared to the baseline CMOS designs and are effective for NCFET based computing in-memory architectures with reduced read disturb issues in combination with DSC concept.

Comparative Analysis of Various Topologies for AC and DC Power Distribution Systems on Efficiency Grounds

Efficiency is the factor that once wiped DC out of the power system at the birth of electricity, in nineteenth century. The battle of currents between AC and DC has reignited with the aggravating employment of DC in the sectors of generation, transmission, and utilization. This calls for cutting edge research in the field of comparative efficiency analysis of AC and DC, on distribution scale. The current research effort compares AC and DC distribution systems on efficiency grounds, for various topologies. The two systems are compared employing normal distribution technique for residential load profile. The varying efficiency of power electronic converters (PECs) with stochastic load profiles is modeled using MATLAB/SIMULINK, for each topology. DC takes the lead against AC with efficiency advantage for energy efficient load-based architectures. The architectures with variable speed drive-based loads, the efficiency advantage in favor of DC is between 1% and 2%, however, the efficiency advantage reaches to 12% with inherent DC loads. In contrast, AC takes the lead with conventional distribution, with an efficiency advantage between 4% and 5%. The findings of current research work can prove to be beneficial in making policy decisions for the adoption of DC at distribution scale.

Energy-efficient architecture for high-performance FIR adaptive filter using hybridizing CSDTCSE-CRABRA based distributed arithmetic design: Noise removal application in IoT-based WSN

An energy-efficient architecture of high-performance FIR adaptive filter design using approximate distributed arithmetic (DA), which is integrated with canonic signed digit-based triangular common sub expression elimination (CSDTCSE) and carry-resist adder based Booth recorder adder (CRABRA) is proposed for noise removal in sensor nodes. Distributed arithmetic is coupled with two signed 32-bit, 16-bit radix-8 Booth algorithms and approximate computation under 2-bit adder to design FIR adaptive filter for decreasing partial products (PP) together with accumulation circuits. The truncation of LSB in the PP is presented to approximate the PP to reduce memory complexity and hardware overhead. An approximation recoding adder decreases the energy usage, area, and critical path. Approximate Wallace trees are applied to the PP accumulation to lessen the latency. The canonic signed digit-based triangular common sub-expressions elimination framework is proposed, which significantly reduces a count of logic operators and logic depth in implementing the FIR filter. The proposed algorithm is activated in Verilog coding and synthesized using Xilinx 14.5 ISE simulation software. The proposed design successfully reduces delay, area, and power by maintaining better accuracy with performance.

An energy efficient reconfigurable architecture for multi-lead ECG signal compression

An energy efficient reconfigurable architecture for multi-lead ECG signal compression

Fracture behavior of high‐performance carbon fiber composites toughened by reactive polyetherimide

AbstractCarbon fiber‐reinforced epoxy composites (CFECs) continue to grow in demand for aerospace, mass transportation, electric vehicle, and energy efficient architecture due to their lightweight, high strength, and high modulus. However, CFECs are susceptible to delamination upon impact which can lead to premature structural failure. This paper investigates the interlaminar fracture toughness of unidirectional CFECs based on reactive polyetherimide (rPEI) modified multifunctional epoxy matrix system. The matrices were cured formulations of tetraglycidyl diamino diphenyl methane, triglycidyl para‐amino phenol, rPEI having different molecular weights (MW) and diaminodiphenyl sulfone. Multi‐phase morphologies were observed from the resin castings and CFECs containing different MW rPEI modifiers. Results show that the mode I fracture toughness (GIC) of the rPEI‐toughened CFECs can be increased by as much as 150% over the unmodified CFECs based on the MW and type of phase morphology that promotes crack‐bridging mechanism. In addition, rPEI‐modified CFECs exhibit better property retention (~80% of GIC) after prolonged solvent exposure.Highlights A processing‐structure–property relationship based on CFECs is established. The amine‐terminated rPEI facilitates the formation of a strong bonding. The molecular weight effect of rPEI on the phase morphology was investigated. The rPEI enhances the interlaminar fracture toughness of the composites. The rPEI particle bridging is found to be responsible for the toughening effect.

Circuit implementation of on-chip trainable spiking neural network using CMOS based memristive STDP synapses and LIF neurons

Computation on a large volume of data at high speed and low power requires energy-efficient architectures for edge computing applications. As a result, scientists focus on memristive circuits and systems for area and energy efficiency. Spiking neural network (SNN) with bio-inspired spike-timing-dependent plasticity learning (STDP) is a promising solution for energy-efficient neuromorphic systems than conventional artificial neural network (ANN). Previous works on SNN with STDP learning primarily use memristor macro models, which are software-based and cannot give complete insight into circuit implementation challenges. Some reported works on SNN use memristive devices, which require additional fabrication steps. This article presents a full circuit-level implementation of the SNN system featuring on-chip training and classification using memristive STDP synapse in standard CMOS technology. A new learning rule using the modified STDP is implemented to simplify the weight modification process. It does not involve FPGAs, CPUs, or GPUs to train the neural network. The approach used in this paper to modify the weights does not require any additional combinational or digital circuits attached to the memristive synapse resulting in less consumption of area, energy and time. We demonstrated the complete circuit-level design, implementation and simulation of SNN with on-chip training and pattern classification using 180 nm CMOS technology. A comprehensive comparison of the proposed SNN circuit with the previous related work is also presented. To demonstrate the versatility of the CMOS synapse circuit for application scenarios requiring rate-based learning, we have tuned the pair-based STDP circuit to obtain Bienenstock–Cooper–Munro (BCM) characteristics and applied it to heart rate classification.