Endurance Of Phase Change Memory Research Articles

Design and Simulation of Content-Aware Hybrid DRAM-PCM Memory System

Phase Change Memory (PCM) can directly connect persistent memory to main memory bus, while it achieves high read throughput and low standby power, the critical concerns are its poor write performance and limited durability. A naturally in-spired design is the hybrid memory architecture that fuses DRAM and PCM, so as to exploit the positive aspects of both types of memory. Unfortunately, existing solutions are seriously challenged by the limited main memory size, which is the primary bottleneck of in-memory computing. In this paper, we introduce a novel Content Aware Hybrid DRAM-PCM memory system framework—CAHRAM, which exploits deduplication to improve line sharing with high memory efficiency. It reduces write traffic to hybrid memory by removing unnecessary duplicate line writes, thereby further enhancing the write endurance of PCM. And it also substantially extends available free memory space by coalescing redundant lines in hybrid memory. We also design a reference-based page migration technique to minimize the access overheads caused by the performance gap between DRAM and PCM. Compared with the state-of-the-art in a hybrid memory simulator, our experiment results show that CAHRAM can achieve the highest I/O performance and the longest PCM lifetime with the competitive efficiencies in space and energy.

Investigation of the effect of blade electrode width on performance of phase change memory

The blade bottom electrode contact (BEC) can significantly reduce the programming current of the phase change memory (PCM) and achieve low power consumption compared with the typical T-shaped PCM cell. The method of controlling the electrode width by controlling the thickness of the deposited layer can make the size break through the limit of photolithography. This paper proves that the RESET programming current and power consumption of the PCM decrease linearly with the decrease of the blade BEC width, and builds a theoretical model to verify it by simulating the distribution internal temperature field. Based on the above research, the cell life of PCM with different electrode widths was tested, and it was proved that the endurance of PCM increased with the decrease of the width of the blade electrode, caused by the lower power consumption of the narrower electrode.

TA-CLOCK: Tendency-Aware Page Replacement Policy for Hybrid Main Memory in High-Performance Embedded Systems

Recently, high-performance embedded systems have adopted phase change memory (PCM) as their main memory because PCMs have attractive advantages, such as non-volatility, byte-addressability, high density, and low power consumption. However, PCMs have disadvantages, such as limited write endurance in each cell and high write latency compared to DRAMs. Therefore, researchers have investigated methods for enhancing the limitations of PCMs. In this paper, we propose a page replacement policy called tendency-aware CLOCK (TA-CLOCK) for the hybrid main memory of embedded systems. To improve the limited write endurance of PCMs, TA-CLOCK classifies the page access tendency of the victim page through access pattern analysis and determines the migration location of the victim page. Through the classification of the page access tendency, TA-CLOCK reduces unnecessary page migrations from DRAMs to PCMs. Unnecessary migrations cause an increase in write operations in PCMs and the energy consumption of the hybrid main memory in embedded systems. Thus, our proposed policy improves the limited write endurance of PCMs and enhances the access latency of the hybrid main memory of embedded systems by classifying the page access tendency. We compared the TA-CLOCK with existing page replacement policies to evaluate its performance. In our experiments, TA-CLOCK reduced the number of write operations in PCMs by 71.5% on average, and it enhanced the energy delay product by 38.3% on average compared with other page replacement policies.

Endurance Improvement of Phase Change Memory Based on High and Narrow RESET Currents

Endurance improvement is a crucial work for phase change memory (PCM) which has always been the focus of researchers, but fewer studies concentrate on parameter optimization to improve endurance. In this paper, the correlation between the RESET condition and the endurance of PCM has been investigated systematically based on sample cells of a 4 Mb embedded PCM chip through Statistical analysis. It is evidently clear from the test results that high and narrow RESET condition can bring a significant improvement in endurance. And a new test-time-saving method for optimizing RESET condition to improve endurance is proposed. Further, the power consumption and the temperature distribution of PCM during the RESET process has been studied. The results confirmed that high heating speed and less thermal damage to the operating electrode originated from the high-narrow RESET pulse all together account for the improvement of endurance.

Partial-PreSET: Enhancing Lifetime of PCM-Based Main Memory with Fine-Grained SET Operations

Phase change memory (PCM) is one of promising technology to replace DRAM with its attractive features such as zero leakage power and high scalability. In PCM, a SET operation needs much more time than a RESET operation. A typical write request concurrently writes 64 bytes to a PCM memory line. Therefore, write latency is mainly determined by SET operations. Previously, PreSET has been proposed to improve PCM performance by exploiting asymmetry in write time. A PreSET operation pro-actively SETs all the bits in the memory line before a dirty cache line is written to PCM . Later, when a write request is processed, only RESET operations are actually performed. Consequently, PreSET reduces write latency and improves system performance. However, such PreSET operations are conducted only at a very coarse-grained level, which reduces the endurance of PCM. Through empirical study, we observe that in most applications the number of dirty words in a dirty line is actually quite limited. If we only SET those dirty words, instead of the whole cache line, we would significantly extend the lifetime of PCM while still achieving desirable performance. Inspired by this observation, we propose a scheme called Partial-PreSET which balances performance and endurance of PCM. The core idea of this scheme is to SET those dirty bits of a cache line in a fine-grained fashion. Our experiments show that the proposed Partial-PreSET scheme significantly improves the average lifetime of PCM system, up to 2.79X, while incurring only 2% system performance loss, compared with the state-of-the-art scheme (i.e., PreSET).

Fully Exploiting PCM Write Capacity Within Near Zero Cost Through Segment-Based Page Allocation

Improving the endurance of phase change memory (PCM) is a fundamental issue when PCM technology is considered as an alternative to main memory usage. Existing wear-leveling techniques overcome this challenge through constantly remapping hot virtual pages, thus engendering a fair amount of extra write operations to PCM and imposing considerable performance and energy overhead. Our observation is that it is unnecessary to fully balance the accesses to different physical page frames during the execution of each process. Instead, since endurance is a lifetime factor, the hot virtual pages of different processes can be mapped to different physical pages in the PCM. Leveraging this property, we develop a wear-resistant page allocation algorithm, which exploits the diverse write characteristics of different program segments to improve PCM write endurance within almost no extra remapping cost in terms of energy and performance. The results of experiments conducted based on SPEC benchmarks show that the proposed technique can prolong PCM lifetime by hundreds of times within nearly zero searching and remapping overhead.

Enhancement of a cyclic endurance of phase change memory by application of a high-density C15(Ge21Sb36Te43) film

The lower cyclic endurance of Phase Change Memory (PCM) devices limits the spread of its applications for reliable memory. The findings reported here show that micro-voids and excess vacancies that are produced during the deposition process and the subsequent growth in sputtered carbon-doped GeSbTe films is one of the major causes of device failure in PCM with cycling. We found that the size of voids in C15(Ge21Sb36Te43) films increased with increasing annealing temperature and the activation energy for the growth rate of voids was determined to be 2.22 eV. The film density, which is closely related to voids, varies with the deposition temperature and sputtering power used. The lower heat of vaporization of elemental Sb and Te compared to that for elemental Ge and C is a major cause of the low density of the film. It was possible to suppress void formation to a considerable extent by optimizing the deposition conditions, which leads to a dramatic enhancement in cyclic endurance by 2 orders of magnitude in PCM devices prepared at 300oC-300W compared to one prepared at 240oC-500W without change of compositions.

Energy-Efficient Phase-Change Memory with Graphene as a Thermal Barrier.

Phase-change memory (PCM) is an important class of data storage, yet lowering the programming current of individual devices is known to be a significant challenge. Here we improve the energy-efficiency of PCM by placing a graphene layer at the interface between the phase-change material, Ge2Sb2Te5 (GST), and the bottom electrode (W) heater. Graphene-PCM (G-PCM) devices have ∼40% lower RESET current compared to control devices without the graphene. This is attributed to the graphene as an added interfacial thermal resistance which helps confine the generated heat inside the active PCM volume. The G-PCM achieves programming up to 10(5) cycles, and the graphene could further enhance the PCM endurance by limiting atomic migration or material segregation at the bottom electrode interface.

PB<sup><bold>+</bold></sup>-Tree: PCM-Aware B<sup><bold>+</bold></sup>-Tree

Phase change memory (PCM) is non-volatile memory that is byte-addressable. It is two to four times denser than DRAM, orders of magnitude better than NAND Flash memory in read latency, and 10 times better than NAND Flash memory in write endurance. However, it still limits the number of write operations to at most $10^6$ times per PCM cell. To extend its lifetime, it is necessary to evenly distribute write operations over all the memory cells. Up to now, the $\mathrm{B^{+}}$ -Tree index structure has been used to quickly locate a search key in a relational database management system (RDBMS). All the record keys in each node are sorted and packed upon insertion in, and deletion from, the $\mathrm{B^{+}}$ -Tree. In addition, a counter keeps track of the number of valid keys in the $\mathrm{B^{+}}$ -Tree. Consequently, a $\mathrm{B^{+}}$ -Tree algorithm results in a large number of write operations, which deteriorates the endurance of PCM. This restricts the usage of PCM on a database server and deteriorates performance of database servers. In this paper, we propose a novel PCM-aware $\mathrm{B^{+}}$ -Tree index structure, called $\mathrm{PB^{+}}$ -Tree, to provide wear-leveling in PCM. According to our experiment results, $\mathrm{PB^{+}}$ -Tree is much faster than the existing $\mathrm{B^{+}}$ -Tree algorithms for PCM and NAND Flash memory with versatile workloads. More importantly, our scheme also greatly reduces the number of write operations compared to other $\mathrm{B^{+}}$ -Tree algorithms. All of these results suggest that $\mathrm{PB^{+}}$ -Tree is the $\mathrm{B^{+}}$ -Tree algorithm best fitted to PCM.

Wear Relief for High-Density Phase Change Memory Through Cell Morphing Considering Process Variation

Due to the scalability and large leakage power, dynamic random-access memory (DRAM) has a lot of challenges in scaling. As an alternative, phase change memory (PCM) has demonstrated promising potential to serve as the main memory in deep submicrometer regime. The broad resistance range of PCM cells enables several cell modes with various densities, pertaining to multiple level cell (MLC), triple state cell (TSC), and single level cell (SLC). High-density mode outperforms low-density ones in terms of capacity and cost-per-bit, but suffers from a weaker cell endurance. Wear leveling strategies are proposed to enhance the memory endurance but encounter more challenges with the aggravating process variation. Due to endurance variations, physical domains are fabricated with irregular tenacity. As a result, balanced write traffic, which is the objective of traditional wear leveling, cannot fully exploit the PCM endurance since the weak parts will be worn out sooner than others. In this paper, considering process variation, we propose a cell morphing based wear leveling scheme. Cell morphing refers to the cell mode transformation between high density (e.g., MLC) and low densities (e.g., TSC and SLC). Instead of redistributing write operations, the proposed wear leveling scheme dynamically transforms weak and frequently written portions into low-density mode for endurance benefits. Multitier cell morphing schemes are proposed to support mode transformation among multiple density levels. The experimental results show 236% endurance improvement for single-tier cell morphing and 209% for two-tier cell morphing with 2% low-density page percentage, when compared with the most related work.

Write-Aware Replacement Policies for PCM-Based Systems

The gap between processor and memory speeds is one of the greatest challenges that current designers face in order to develop more powerful computer systems. In addition, the scalability of the Dynamic Random Access Memory (DRAM) technology is very limited nowadays, leading one to consider new memory technologies as candidates for the replacement of conventional DRAM. Phase-Change Memory (PCM) is currently postulated as the prime contender due to its higher scalability and lower leakage. However, compared with DRAM, PCM also exhibits some drawbacks, like lower endurance or higher dynamic energy consumption and write latency, that need to be mitigated before it can be used as the main memory technology for the next generation of computers. This work addresses the PCM endurance constraint. For this purpose, we present an analysis of conventional cache replacement policies in terms of the amount of writebacks to main memory that they imply and we also propose some new replacement algorithms for the last-level cache (LLC) with the goal of cutting down the write traffic to memory and consequently, to increase PCM lifetime without degrading system performance. In this paper, we target general purpose processors provided with this kind of non-volatile main memory and we exhaustively evaluate our proposed policies in both single- and multi-core environments. Experimental results show that, on average, compared with a conventional Least Recently Used (LRU) algorithm, some of our proposals manage to reduce the amount of writes to main memory up to 20–30% depending on the scenario evaluated, which leads to memory endurance extensions of up to 20–45%, also reducing the energy consumption in the memory hierarchy by up to 9% and hardly degrading performance.

Application-Specific Wear Leveling for Extending Lifetime of Phase Change Memory in Embedded Systems

Phase change memory (PCM) has been proposed to replace NOR flash and DRAM in embedded systems because of its attractive features. However, the endurance of PCM greatly limits its adoption in embedded systems. As most embedded systems are application-oriented, we can tackle the endurance problem of PCM by exploring application-specific features such as fixed access patterns and update frequencies. In this paper, we propose an application-specific wear leveling technique, called Curling-PCM, to evenly distribute write activities across the whole PCM chip to improve the endurance of PCM in embedded systems. The basic idea is to exploit application-specific features in embedded systems and periodically move the hot region across the whole PCM chip. To reduce the overhead of moving the hot region and improve the performance of PCM-based embedded systems, a fine-grained partial wear leveling policy is proposed for Curling-PCM, by which only part of the hot region is moved during each request handling period. Experimental results show that Curling-PCM can effectively evenly distribute write traffic for a prime application of PCM in embedded systems. We expect this paper can serve as a first step toward the full exploration of application-specific features in PCM-based embedded systems.

Modified write-and-verify scheme for improving the endurance of multi-level cell phase-change memory using Ge-doped SbTe

In this study, a modified write-and-verify (WAV) scheme is proposed for improving the programming/erasing (P/E) endurance of multi-level cell (MLC) phase-change memory (PCM) using Ge-doped SbTe (GeST). A dual reference data read method is developed to detect the level margin decay during P/E cycling, and a trigger condition is designed to trigger self-repair for the degraded cells before any P/E error for the modified WAV scheme. Experimental results suggest that the modified WAV scheme effectively extends the P/E endurance of PCM using GeST during 4-level P/E by at least 10 times. The modified WAV scheme is expected to improve the endurance of MLC–PCM of system applications.

A durable and energy efficient main memory using phase change memory technology

Using nonvolatile memories in memory hierarchy has been investigated to reduce its energy consumption because nonvolatile memories consume zero leakage power in memory cells. One of the difficulties is, however, that the endurance of most nonvolatile memory technologies is much shorter than the conventional SRAM and DRAM technology. This has limited its usage to only the low levels of a memory hierarchy, e.g., disks, that is far from the CPU. In this paper, we study the use of a new type of nonvolatile memories -- the Phase Change Memory (PCM) as the main memory for a 3D stacked chip. The main challenges we face are the limited PCM endurance, longer access latencies, and higher dynamic power compared to the conventional DRAM technology. We propose techniques to extend the endurance of the PCM to an average of 13 (for MLC PCM cell) to 22 (for SLC PCM) years. We also study the design choices of implementing PCM to achieve the best tradeoff between energy and performance. Our design reduced the total energy of an already low-power DRAM main memory of the same capacity by 65%, and energy-delay 2 product by 60%. These results indicate that it is feasible to use PCM technology in place of DRAM in the main memory for better energy efficiency.