Endurance Failures Research Articles

STATE: A Test Structure for Rapid and Reliable Prediction of Resistive RAM Endurance

Characterizing and quantifying the endurance of Resistive RAM devices is critical to assess their reliability for integration in electronic systems. This paper proposes a novel characterization methodology for rapid detection of RRAMs reliability issues during endurance tests. A test structure consisting of an array of non-addressable RRAM memory cells with parallel connection of all the memory elements is used for this purpose. The test structure fills the gap between isolated cells and circuit level endurance tests as it combines the test speed of an isolated cell while providing at the same time data from multiple devices. Endurance tests are conducted while monitoring RRAM electrical parameters of interest for each switching cycle. Experimental results show that most studies that claimed high endurance without capturing all switching cycles, or by considering an isolated cell, lead to an overestimation of the endurance. Finally, an endurance failures mitigation scheme based on RRAM current sensing in the RESET direction is presented to improve the endurance.

Development of Reflow Fill of CGeSbTe Films for Sub‐20 nm Cells in 3D Cross‐Point Memory

AbstractTo obtain reliable and scalable cells in 3D cross‐point memory, endurance failures caused by voiding from etching damage to memory cells should be resolved to preserve the properties of GeSbTe (GST) phase‐change materials. Herein, the fabrication of a damascene cell without patterning, which relies on the bottom‐up fill of carbon‐doped GST layers into confined cells, is proposed as a promising solution. The reflow fill of the sputtered carbon‐doped GST films into confined cells at high‐temperature and low‐power conditions is demonstrated, and a mechanism in which Sb and Te transfer into the cell through vapor transfer and viscous flow due to capillary pressure is verified. The aspect ratio increases from 2 to 7.7 under enhanced vaporization of Sb and Te as well as the capillary force. The advanced reflow‐fill process using a laser can overcome the limit of the conventional reflow‐fill technology by increasing the atomic mobility above the melting temperature. Based on the proposed method, 19 nm cross‐point memory devices are successfully integrated together with the Ovonyx threshold switch and appropriate memory windows are secured. Furthermore, the 9 nm cells exhibit reliable endurance cycles over 108.

CHIMERA: A 0.92-TOPS, 2.2-TOPS/W Edge AI Accelerator With 2-MByte On-Chip Foundry Resistive RAM for Efficient Training and Inference

Implementing edge artificial intelligence (AI) inference and training is challenging with current memory technologies. As deep neural networks (DNNs) grow in size, this problem is only getting worse. This article presents CHIMERA, the first non-volatile DNN chip for both edge AI training and inference using foundry on-chip resistive RAM (RRAM) macros and no off-chip memory, fabricated in 40-nm CMOS. CHIMERA&#x2019;s DNN accelerator is specifically optimized for RRAM and achieves 0.92-TOPS peak performance and 2.2-TOPS/W energy efficiency. We scale inference up to <inline-formula> <tex-math notation="LaTeX">$6\times $ </tex-math></inline-formula> larger DNNs by connecting six CHIMERAs in an illusion system with just 4&#x0025; overhead in measured execution time and 5&#x0025; in energy, enabled by communication-sparse DNN mappings that exploit RRAM non-volatility through quick chip wake-up and shutdown (<inline-formula> <tex-math notation="LaTeX">$ &lt; 33 ~\mu \text{s}$ </tex-math></inline-formula>). Our incremental edge AI training algorithm, called low-rank training, overcomes RRAM write energy, speed, and endurance challenges and achieves the same accuracy as traditional algorithms with up to <inline-formula> <tex-math notation="LaTeX">$283\times $ </tex-math></inline-formula> fewer RRAM weight update steps and <inline-formula> <tex-math notation="LaTeX">$340\times $ </tex-math></inline-formula> better energy-delay product. Combined with ENDUrance REsiliency using random Remapping (ENDURER), a hardware module that provides resilience to write endurance failures, we enable ten years of 20-samples/min incremental edge AI training.

High Temperature CsPbBrxI3-x Memristors Based on Hybrid Electrical and Optical Resistive Switching Effects.

The emergence of perovskite-based memristors associated with the migration of ions has attracted attention for use in overcoming the limitations of the von Neumann computing architecture and removing the bottleneck of storage density. However, systematic research on the temperature dependence of halide perovskite-based memristors is still required due to the unavoidable thermal stability limits. In this work, mixed halide CsPbBrxI3-x-based (X = 0, 1, 2) memristors with unique electrical and optical resistive switching properties in an ambient atmosphere from room temperature to a 240 °C maximum have been successfully achieved. At room temperature, the CsPbBrxI3-x-based memristors exhibit outstanding resistive switching behaviors such as ultralow operating voltage (∼0.81, ∼0.64, and ∼0.54 V for different devices, respectively), moderate ON/OFF ratio (∼102), stable endurance (103 cycles), and long retention time (104 s). The CsPbBrxI3-x-based memristors maintain excellent repeatability and stability at high temperature. Endurance failures of CsPbI3, CsPbBrI2, and CsPbBr2I memristors occur at 90, 150, and 270 °C, respectively. Finally, nonvolatile imaging employing CsPbBr2I-based memristor arrays based on the electrical-write and optical-erase operation at 100 °C has been demonstrated. This study provides utilization potentiality in the high temperature scenarios for perovskite wearable and large-scale information devices.

Test Methodologies and Test-Time Compression for Emerging Non-Volatile Memory

Emerging nonvolatile memories (NVMs) are considered as suitable candidates to replace conventional memories such as static RAM (SRAM) and dynamic RAM (DRAM) due to high density, high performance, and low (static) power operation. However, NVMs bring new fault issues and call for new tests. For example, NVMs exhibit wide read and write latency distribution, incur high write current (leads to high supply noise), are susceptible to external magnetic/thermal field, show high and stochastic retention time, and are prone to endurance and reliability failures. The conventional tests either cannot capture the faults specific to emerging NVMs or they incur significant test time if implemented on emerging NVMs. In this article, we summarize fault models specific to NVMs and explain the related test issues and challenges. We also propose new tests along with necessary design-for-test techniques to characterize the failures. We further summarize NVM tests proposed in prior works and analyze their test time requirements.

Phase-change memory cycling endurance

Abstract

Resistive RAM-Centric Computing: Design and Modeling Methodology

Memory-centric computing with on-chip non-volatile memories provides unique opportunities for native and local information processing in an energy-efficient manner. Design and modeling methodology based on resistive random access memory (RRAM) is presented in this paper. A hierarchical RRAM SPICE model having different levels of physics realism is described, where the incorporated stochasticity provides a more accurate representation of RRAM operations. Three in-memory operation schemes are developed and experimentally verified for reconfigurable in-memory logic, using RRAM built in 3-D vertical structure (i.e., 3-D RRAM). As a case study for RRAM-centric computing systems, we evaluate the Please note that there were discrepancies between the accepted pdf [TCAS_R1_combined.pdf] and the [TCAS_RRAM-centric computing_hli_FINAL_submit.docx] in the lines 12 and 70. We have followed [TCAS_RRAM-centric computing_hli_FINAL_submit.docx]. use of 3-D RRAMs for a language recognition system using the hyperdimensional (HD) computing model. Utilizing the inherent properties of 3-D RRAM, we demonstrate, using fabricated 3-D RRAM integrated with FinFET, the essential kernels for HD operations: multiplication, addition, and permutation (MAP). RRAM-centric HD systems exhibit strong resilience to hard errors induced by RRAM endurance failures, making a promising case for using various types of RRAM for memory-centric HD systems.

Mechanism of Threshold Voltage Widening in Sub-30 nm MLC NAND FLASH Cells after Erase/Write Cycling

From the investigation of endurance failures in sub-30 nm multi-level NAND flash cells, we observe that the threshold voltage (VTH) distribution of the lowest state cells has the broadest dispersion, leading to failures after erase/write (E/W) cycling. This is due to the combined effect of trapped charges in the tunnel oxide on the cell junction region and to cross coupling between a victim cell and neighbor cells. In the gate edge, the trapped charges that were generated during E/W cycling induce a cell VTH shift by causing a depletion of junction, and neighbor cells have a larger VTH due to victim-cell coupling.

A 128 K flash EEPROM using double-polysilicon technology

An easily manufacturable 128 K flash EEPROM (electrically erasable programmable read-only memory) was developed based on a novel cell. Programming is achieved through hot-electron injection and erasing through electron tunneling from the floating gate to the drain. The cell is 20% larger than an EPROM cell and contains an integral series transistor which ensures selflimited erasing, reduces leakage, and increases the cell current. The flash EEPROM device can withstand thousands of program/erase cycles. Endurance failures are due to threshold window closing caused by electron trapping in the gate oxide. Typical erasure time is 1 s to clear the entire memory.