Resistive RAM-Centric Computing: Design and Modeling Methodology

Abstract

Memory-centric computing with on-chip non-volatile memories provides unique opportunities for native and local information processing in an energy-efficient manner. Design and modeling methodology based on resistive random access memory (RRAM) is presented in this paper. A hierarchical RRAM SPICE model having different levels of physics realism is described, where the incorporated stochasticity provides a more accurate representation of RRAM operations. Three in-memory operation schemes are developed and experimentally verified for reconfigurable in-memory logic, using RRAM built in 3-D vertical structure (i.e., 3-D RRAM). As a case study for RRAM-centric computing systems, we evaluate the Please note that there were discrepancies between the accepted pdf [TCAS_R1_combined.pdf] and the [TCAS_RRAM-centric computing_hli_FINAL_submit.docx] in the lines 12 and 70. We have followed [TCAS_RRAM-centric computing_hli_FINAL_submit.docx]. use of 3-D RRAMs for a language recognition system using the hyperdimensional (HD) computing model. Utilizing the inherent properties of 3-D RRAM, we demonstrate, using fabricated 3-D RRAM integrated with FinFET, the essential kernels for HD operations: multiplication, addition, and permutation (MAP). RRAM-centric HD systems exhibit strong resilience to hard errors induced by RRAM endurance failures, making a promising case for using various types of RRAM for memory-centric HD systems.